DE1240928B - DC-coupled electronic binary counter - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H03k

German KL: 21 al-36/22

Number: 1240928

File number: L 40894 VIII a / 21 al

Filing date: January 9, 1962

Opened on: May 24, 1967

Binary counters are used to count continuously. Known binary counters consist of flip-flop stages, which can be dynamically or galvanically coupled. Such flip-flop stages consisting of Binary counters are coasters that are controlled by square-wave voltages. The flip-flop stages step down in the ratio 1: 2. At the output of a first flip-flop stage a corresponding occurs reduced square wave voltage. This is fed to another flip-flop stage as a control voltage. Correspondingly, a scaled-down square-wave voltage occurs again at their output, and so on If binary counters of this type are designed as static flip-flop stages, difficulties may arise in the transition behavior with the change of state of the individual stages. These can be converted into a wrong switching state. The binary counter in the dynamically capacitively coupled flip-flop stages the respective coupling capacitor arranged between the stages takes over the delay ao of the one control signal, so that the transition behavior of the stages does not cause any difficulties gives. However, the disadvantage of capacitively coupled stages is that they are not only respond to the actual control signals and clock signals, but also to external interference pulses.

In a known binary counter, a flip-flop stage, a half adder and a Delay line used. An entrance to the The flip-flop stage is activated by the sum signal and the other input of the flip-flop stage by the Carry signal of the half adder activated. A signal of one output of the flip-flop stage is connected via a delay line to one input of the half adder and to the other Input for the counting level of the lowest binary digit are the pulses to be counted and for the following ones Counting stages switched the carry signal of the respective preceding counting stage.

This counter is again a dynamic counter that responds to external interference pulses appeals to. Furthermore, by using a delay line in each counting stage, the timing behavior must be affected the incoming pulses in the half adder high demands are made so that the Counting levels do not fall into an incorrect switching state, which means that counting errors also occur.

Another reference is the schematic structure of a register and an adder as Known counter. This corresponds in principle to the counter described in more detail above.

DC coupled electronic
Binary counter

Applicant:

Licentia Patent-Verwaltungs-G. m. b. H.,

Frankfurt / M., Theodor-Stern-Kai 1

Named as inventor:
Dipl.-Ing. Elmar Götz,
Frankfurt / M.-Gravenbruch

There are also dynamic binary counters known, each counting stage from only one half adder and one Delay line serve as a return. These counters also have the disadvantages listed above.

In computing systems, among other things, series connections of several flip-flop stages are also used used, which are arranged before and after a group of logic circuits. The one at the entrance Signals present in such series connections may be lost when the series connection is run through decreased in amplitude, delayed and deformed.

To ensure a secure time lapse between these signals and the clock signal of the computer system reach, so-called clock generators are used, through the clock or gate circuits Clock pulses are given to the flip-flop stages of the series connections. With a well-known The series circuit consisting of three flip-flop stages turns the first and third flip-flop stages through a first clock pulse sequence and the second flip-flop stage by a further one occurring at different times Clock pulse train controlled. In logic circuits, it is known to use DC coupling use. It is also known from two tube flip-flops counting stage that has two signals that occur offset are controlled. If several such counting stages are interconnected, so in such a counter there are jumps which cause the counter to have an incorrect count can fall.

Another disadvantage of a counter consisting of several counting stages is that an whose impulse lines occurring impulses only briefly over the duration of the impulse for the impulse result in the change of state of the respective flip-flop, whereby it is by no means ensured that by

709 587/493

3 4

the impulse that occurs is really a state - the change in the flip-flop circuit has taken place in the lowest binary digit. An output signal from output and buffer stores, for example, which occurs for the first time on a line, formed from the combination of the respective clock pulse, one of the two-tube flip-flops should go into signal and the correspondingly negated clock signal with a switching state, and when a 5 occurs, its own output signal and the output signal further impulse on the same line should be that of the respectively assigned memory, and in the flip-flop with the same sequence in another switching state the higher binary digits is also the output trapping. The two im- signals of the buffer of the respective preceding pulses appearing on the line only give the impetus for this, ensure the binary digit is also used,
however, it does not mean that a change of state also takes place in an expedient manner, both in formation and in realization. Strengthening the carry signal as well as the sum

Another disadvantage is that the memory signals contain two identical and and or / or elements because of the use of a. Negators and non-stages existing logic circuits. One The transfer exists in accordance with the further training required in each counting stage a time delay can be controlled, so 15 supporting circle of three as a holding stage, temporal Nebendaß the result is a counter that works only slowly. final stage and input stage effective AND stages,

In contrast to this, an or / or-not stage is connected downstream of those according to the invention Counter on occurrence of the memory element, at the affirmed output of which the outgoing override is Pulses through this the change of the carry signal is taken off, and the summation circuit Switching state of the counter is forced and the ao also consists of three as a holding stage, temporal Switching state also afterwards by the impulses on shunt stage and input stage acting and maintained. At the moment of activation (clock stages followed by an or / or-not stage) of the storage element there is therefore a stricter switch, at whose aged output the result logical relationship between the memory of the summation and the input stage element driving input signals and the as and the shunt stage of the carry circuit resulting output signal. Through the return through the incoming carry signal and the management within each memory element, this result signal of the assigned summation circuit is on-state maintain. controlled, while the input stage of the summation

There are finally circuit arrangements for the circuit through the incoming carry signal and

Regeneration of short pulses known. The negated outgoing carry signal is activated

is used in this circuit is alternating current, and the shunt stage of the summation circuit

coupled amplifiers. With the subject matter of the invention also by the negated outgoing transfer

on the other hand, it is a direct current signal and the result signal of the summation circuit,

coupled binary counter in which the used The invention is illustrated with reference to in the drawings

Storage elements in themselves and also with each other directly 35 schematically illustrated embodiments in more detail

are coupled. The storage elements used are explained.

also do not serve to regenerate short pulses. The dynamic flip-flops according to FIG. 1 it can be seen, an adder + known circuit are used where used, the output signal S _{v of which is given} in an output-specific signals specific normalized length of time 40 memory AS . The adder should have existed. The dynamic flip-flops operate from a summing circuit whose input terminals a, using a Uhrimpulses with a b u _t Binärziffernsignale (L or 0) are supplied, repetition frequency of 1 MHz. As a result of the result of the delay networks at the output terminal s _{r, a certain temporal summation should occur.} The adder consists of the position of the impulses to be reached. 45 also from a carry circuit with the output

The invention relates to a direct current terminal ü _a .

coupled electronic binary counter after the In the adder + is a binary digit α and b principle of addition, at the outputs of which signals are entered. In addition, in the adder when up in natural binary code in parallel representation exists, the carry u _e of the preceding point contact, depending binary digit of two in themselves and with each 50 input. As indicated above, these are voltages directly coupled to each other, signals of a certain polarity at different times, which are assigned to the values 0 or L by clock signals that are not in line with one another. The result signal is picked up at the output a _{v of} the output memory controlled output and intermediate memories for 1 bit AS. When there is a switching state whose switching state is determined by influencing only the adder of the lowest binary digit, one of the amplifier elements per memory is determined. 55 input signals according to the invention always the The invention consists in that the value L.

The output memory AS is opened at a specific time from setting and holding the memory by a clock signal I ₁ . If the operative logic circuit consists of the clock signal I ₁ (for example L), the clock signals and the memory output signals will form the sum of the adder + partial signals overlapping from the output memory AS , which are taken over together. The detected at the output a _{v a} gap result over the duration of the partial signals is also fed back to a loose signal as an output signal for the memory buffer ZS. This buffer ZS generate, and that the output signal of each intermediate is controlled by a further clock signal t _z . The clock signals I ₁ , t ₂ occur with gaps, as from the output memory and the input circuits of the diagram in FIG. 2 can be seen. So if there is an output / buffer combination, the following is in the output memory AS and thus controls a specific binary digit at a _v. A further training result (L or 0), this is reported via the line

tion a, ' fetched over to the buffer ZS. Sum * the value L; the outgoing carry «It is then when the clock signal t _{2 occurs} in is 0. If only the input b has the value L, then this results in a buffer and thus at α . In which, in turn, the sum s with L, the outgoing adder + becomes, as already indicated above, carry over _a is 0. Have the inputs b and over _{e formed} the a + b . The value α may be L in the present 5 values, the sum s results in the value 0, and in the case of the one coming from the buffer ZS , an outgoing transfer ü _a = L occurs. Have a value, let b in the present case (adding unit all three inputs the value L, then the sum s of the lowest binary digit results) always be the value L. Im the value L, and an outgoing over-addition + results then a + b, and since b carries ü _a = L.

L is always always This value is a club forms a + io L. According to the invention arises through the line _v s upon occurrence of the clock fold increase when g in the binary counter to the F i. 3 also given signals t _x in the output memory AS . In addition to the input b _{0 of} the adding unit + _0, not an outgoing excess value L is formed in the adder unit, but the value 0 is supplied and for this, which occurs at the output u _a . In the present case, the carry ü _eo for the arrangement of the lowest case is the value of the incoming carry «""= 0. 15 binary digit is always L , as is the case with the corresponding

The in the F i g. 1 shown, from adder +, inputs is indicated (not in brackets output memory AS and intermediate memory ZS be values). The adders + "to + ₂ can thus be used for a standing arrangement for a binary digit. be designed as half adder.
If several such arrangements according to FIG. 1 So now act at the inputs b ₀ to b ₂

is used, it follows, as shown in FIG. 3 always sees the values 0. In this case, as indicated, Hch is a complete binary counter. the first incoming carry ü> ₀ = L. Through this

As can be seen, in FIG. 3, for example, training results in the great advantage that all three arrangements are selected, which are associated with the arrangements F i g assigned to the individual positions after the loan. 1 match. It can be simplified as desired and completely arrangements can be provided among one another. Each arrangement 25 are the same. For Table 1, these Maßbesteht turn means from an adder +, one would take the determination of the value of the carry ü _eo downstream output memory AS and a and the value 0 for the inputs b ₀ to b _2, that the fed-back output value receiving intermediate value for b in table 1 is now always 0, ie, schenspeicher ZS. The memory AS and ZS of the three all the combinations in which b has the value L arrangements are common by the clock 3 °, come in the training according to FIG. 3 signals I ₁ , t ₂ activated. The resulting out- not at all. In Table 1, the escaping carry of an adder is switched on with the falling value of the input b , the adder of the next digit is switched on and so on. The frames. Table 2 shows the remaining adders again have the inputs a, b, ü _e . Combinations. As can be seen, the entrance b

How the training after the F i g. 3 shows, 35 is completely omitted. Only the four remaining, the arrangement for the lowest binary digit from the combinations shown. The third, fourth, adder -) - "with its inputs a ₀ , b ₀ , ü _eo and the seventh and eighth combination according to Table 1, the sum output s _r0 . Furthermore, from the output are omitted, since the input b has previously stored the value L AS ₀ with the result output a _v0 . Who had. These combinations are to indicate the input of the memory AS ₀ is with the output s " ₀ 4 ° omitted in table 1 in brackets,
of the adder + "connected. According to Table 2, the sum s in

output a _{r0 of} the memory AS ₀ is carried over the line a ' _{v0 of} the first combination, the value 0, in the second to the intermediate _{memory ZS 0} . Its combination of the value L, in the third combination gear is in turn connected to the input a _{0 of} the adder, in turn, the value L and in the fourth the value 0 work + ₀ . The adder + "indicates 45 to a carry-out L. In the previously also has an output ü _ao for the outgoing over- previous combinations is the outgoing carry to the next digit on. trag = 0. Table 2 shows the function of a

The arrangements for the other binary digits of the half-adder are shown.

are designed in the same way and have the same structure

Differentiation between the indices 1 and 2. As can be seen, this is shown at the result _outputs a v0 to a _{v2 of} the combinations according to table 2 through the addition units. In the three arrangements pending result via table 3, the initial state is denoted by 0000. Buffer returned to the adding units. In the lowest (0-th) digit, the first Am adder + “is the clock signal t _x entered at the input ü _ea, the incoming carry ü _eo = L. Given carry = 0, as indicated by the value in brackets 55 This results in the sum 000Z. = Decimal number 1. When is indicated, while the inputs Zj ₀ with the occurrence of the next clock signal C ₁ , the value L and O ₁ , b ₂ are again subjected to the value 0, the value L of the carry added ü _eo. This turns out to be. At the adder + _{0 the} sum OLO = decimal number 2 results. Then again

η λ- h 4- iJ - <■ nnH ;; ^the carry over ü _eo = L is added, and the result is the

^{+ +} '* " ^v0 " ^α ° · 5o sum OLL = decimal number 3 etc. According to the

Here, s represents _P0, the sum of a + b and u _ao sequence of clock signals I ₁ thus stands at the Ausden carry-out. In Table 1 addressed ^ ₀ ... σ,. ,, of the counter of FIG. 3 this relationship for a full adder still - either the value 0 or L, and represented by the output of the maize. lowest binary digit (a ,. _o ) to the output of the highest

The three input variables the value of 0, 65 _s th binary digit (o ,, ₀ or a _rll) read out results is the sum s and as an outgoing exceeded the full count. The output a _v0 has the value 0. If the inputs a, b den have the valency 2 °, the output a _vl the value 0 and input ü _e the value L, then the valency 2 results ¹ , the output a _r2 the value 2 ² etc.

7 8

In table 4a, the ratios are shown in The counting result of a binary digit is linked to the output _memory assigned to the outputs a r0 to a, _2. This is shown again in greater detail in the output signals that are issued - the assigned buffer is returned, provided. The formation of the sum and the outgoing excess in the counter according to FIG. 3 are in the Austräges now all the binary of FIG. 3 carried out separately, as in the places assigned arrangements in state 0. Steps F i g. 4 is indicated schematically. How the first clock signal I ₁ is generated from this, as can be seen in the detailed FIG. 4, the carry is formed before the carry _eo = L in the output memory AS ₀ via intermediate memory ZS . This interim report. The downstream arrangements have io rather ZS is also used for the summation with the state 0 as before, since the outgoing one is used. The sum then goes into the carry-out where _ao = 0 . If the first cycle t ₂ occurs, the output memory AS. The result at the output of the is the _{result pending at the output o, 0} in the output memory AS is given to the carry stage ü buffer ZS and is thus also fed back. Furthermore, the one from the previous one starts again at the input α of the adder + ₀ . The 15 previous stage occurring carry ü _e, in which the content L of the latch ZS ü ₀ and incoming carry-forming step and in the above, the sum transfer _eo = L obtained in this switching state of the forming step s. The outgoing carry ü _ar for counter an output i, ₀ = 0 with an outgoing - the following stage is taken from the output of the intermediate carry M ₀₀ = L. As can be seen from table 4 - memory ZS is removed.

lent, this is due to the fact that the input a ₀ and the ao When adding, both the sum and

Input ü _eo after the occurrence of the first clock signal i _a the carry are formed. For both processes

have the value L. At the output s _{vl of} the adder, the output a _v and the input _{carry ü e} , are produced

werkes + _x occurs because of the outgoing over- attracted. This goes according to FIG. 4 of the

sluggish ü _ao = L of the first adder + ₀ and the value a, via the transmission stage ü and the

Values 0 at the inputs a _u O _{1 of} the second adder as the intermediate memory ZS on the summation stage s

Work + _t the value L on. This is followed by the second arrangement according to FIG. 4 will therefore be the

Clock signal I ₁ , whereby the sum s _P1 = L of the outgoing carry and the sum are formed separately.

Adding unit + _t at the output a _vl as the result L The carry stage ü is fed with a, and ü _e,

occurs. just like that so far with the adder after the

The value L that is constantly present at ü _eo is shown in FIG. 3. By training after speaking the clock sequence of I ₁ with the other at the F i g. 4 is achieved, however, that the at the input a _{0 of} the first adder + "an- counter according to FIG. 3 required amplifier V is added and the sum output can be avoided, since this function is now taken immediately during the respective resulting value (either the buffers ZS of each binary digit via-0 or L) of the outgoing transfer to the next. The carry formation takes place when the following adder - ^ _{1 is} passed on, etc. The order according to FIG. 4 by the no VerTable 4a shows the tonic at the outputs a _r0 , a, _x , a _ri level ü. The intermediate binary signals of the clock signals 1 to 7 , however, memory ZS causes the amplification at the same time. The counter according to FIG. 3 can arbitrarily expand the outgoing carry signal ü _a,.
will. It is possible, for example, to add another output memory to the adder by dividing the werk + o, adding up to the non-amplifying summers by means of a further clock signal, for example stage s, and the output memory AS , which only starts counting later. The counter according to which, as an amplifier of the output signal s, the summing F i g. 3 shows that the value L acts so often at the initial stage s.

value is added, such as the clock signal I ₁ = L 45 in FIG. 5 is a counter for two binary digits

occurs. shown, which can be expanded as required. the

In the half adders according to FIG. 3 The arrangement of each binary digit corresponds to that after the two operations. First, the formation of the sum F i g. 4 and is again divided into two memories ZS ₀ , and secondly the formation of the outgoing transfer. AS ₀ , as is the case with the arrangement according to FIG. 3, each half-adder has two outputs. In front of the output memory aisles 5 ·, above _a . The outgoing carry is always fed to the AS ₀ , a non-amplifying stage S ₀ to form the next adder, and its sum is arranged, and before the intermediate outgoing carry is again given to the then memory ZS , a non-amplifying stage ü _{0 is given} to the following adder, and so on Arranged through this advanced training of the outgoing transfer. The outgoing carry circuit is fed with the _{outgoing carry ao} is fed to the following over corresponding carry signal, the weaker and weaker carrying stage U ₁ and summing stage S _1. The den. To avoid this, the intermediate store ZS ₁ must be connected between the adders + ₀ and + _x and + ₂ in the transmission carry stage U ₁ , and the output special amplifier is provided for the summing stage S _1. This storage AS _{1 is} connected downstream. For the formation of the total in stronger are shown in FIG. 3 indicated by dashed lines and 60 of this downstream arrangement is also denoted by V. The outgoing carry signal fed back output value a _{v is} used,
is regenerated by this amplifier V again. In the case of the counter according to FIG. 5 is the adding

By means of this additional amplifier V , the plant according to FIG. 3 increased into an independent total expense of the counter. level and transfer level resolved without amplification,

This disadvantage is avoided in that, according to FIG. 65 and the previous intermediate amplifier ZS ₁ , the sum and over-amplification of the outgoing carry signal is split up for a further development. It is also used here. The result of the sum of the following consideration assumed. education is also provided by the output memory

9 10

AS reinforced. Sum and outgoing carry occurs at the output of the AND stage & ₃ the value L. results are available. This is transferred from the OR level ν to the OR transfer levels ü according to the F i g. 4 and 5 non-level E and occurs at output a as do not represent any additional elements compared to signal L. At the output ″, the signal 0, the formation of the adder as shown in FIG. 3, appears. At the AND stage Sc ₂ , the carry stages u according to FIGS. 4 and 5 are in the state of the memory at both inputs the g already in the addition units to the F i. 3 corresponds values L, so that also maintained at the output value of the L elements. the same applies to the summing occurs. can τ the clock signal quiet 0 are gradually s. g In the F i. 6, this is (is then L F), as the value L α at output by hand of the adder + "after the F i g, for example at. 3-yet io the AND circuit & ₂ sure shown schematically over the time of the value. alternating of the clock signals τ, r is held. The AND-It is a half-adder whose stage & ₂ forms a temporal shunt. In the operating principle already explained on the basis of Table 2, the signal e generally lasts longer than the clock has become. As can be seen from this table, signal τ passes through the time lichen shunt of a carry ii _a - L , if a "and ü _ev = L. 15 And stage Sc ₂ can therefore change the value of the clock in FIG. 7 a possible signal τ, T occurs in schematic form without the output α changing its current value. The illustrated. _{An AND holding stage A 1} holds the value at the output α, even stage Sc ' , which supplies the values a _v and u _ev when the clock signal τ, after it had the value L , is carried out for the carry formation. The output of this AND stage Sc ' ao assumes the value 0. Thus the clock signal τ = L, results in the outgoing carry ü _a ». This And- and if, for example, the value L at the output stage Sc ' does not result in an amplification of the carry-over ratio, this is now due to τ "= L and signals. To achieve this, two would have to amplify the output of the holding stage Sc ₁ - L held kende stages (for example, transistor non-steps) g In the counter stage after the F i. 8, two are dervorgesehen as shown by the stages N, N 'reasonable 25 like design memory configurations after the indicated is. F i g 9. The intended AND levels Sc ₁ , the sum s is according to Table 2 - L if Sc ₂ , & ₃ and the AND levels Sc ₁ ', & ₂ ', Sc ₃ ' become a, and ü _e "have opposite valence. In the formation of the outgoing carry-over and to sum adder according to the F i g. 7 are used menbildung for the sum.

Formation of two further And stages Sc ", Sc. '" provided. 30 In the counting stage according to FIG. 8 represents the And-At the output of the And-stage Sc " occurs the Wert_L, stage A ₁ the holding stage, the And-stage Sc ₂ the time when at the input of this stage ü _ev - L and a _v = L borrowed shunt and the And -Stage Sc ₃ the action. At the output of the AND-stage &'"there is an output stage. This is followed by an OR, the value L, if at the input a _r = L and ü _ev - L stage ν and the or-not stage E. The overall effect. In both cases there is the sum L. 35 arrangement is used to form and reinforce the The two And levels Sc ", Sc '" is an OR level ν outgoing transfer. Analogously, the and is connected downstream. The holding stage, the AND stage & ₂ 'of the time a non-stage N ", N'" are inserted into the lines ö "" and _over per stage Sc ₁ , as is the dashed shunt and the AND stage & ₃ 'die The gear stage described above, which is followed by the arrangement consisting of the or stage v 'and the OR elements, for example, represents 40 non-stage E' . Like or level V " is not taken into account for the time being. This can be seen, each adder four non overall arrangement serves for the formation and amplification steps N to N '"is required. In the case of the counters according to the sum. In the holding stage, Sc ₁ is the Taktden F i g. 4 and 5, this non-stage omitted , and signal τ _2. In addition, the lower function goes into this stage, the function of which is carried out by the 45 'output α (ü _av ) of the or-not stage E, which is present anyway. The AND stage & ₂ ( temporal shunt) goes straight-Hereinafter, with reference to FIG. 8, 9 a if the output α {üav) · in addition, is fed to this further particularly advantageous embodiment of the meter and level & _2, the input signal g to the F i. 4 and 5. of two components Schaltungsanord- 50 illustrated 8 is made. This input the g of F i. signal is indicated by a circle and sets voltage corresponds in principle to the _v and after FIG. 4 consists of a u _he , formed by the ü _av and m eight of storage arrangements will be used at. This also corresponds to the training which is avoided by their transition Fig. 7. In Fig. 8 is a. the output of the off behavior (clock signal goes from L to 0 or the common memory at which the result is pending, the other way round) an incorrect switching state (L 55 The pending result at a “and the entered or 0) is assumed. In FIG. 9 is with transfer ü _ev are thus as input signals via, for example, a memory arrangement na: h of FIG. 8 the AND stages & ₃ , Sc ₂ linked to one another and shown. The memory arrangement consists of the it is formed as an outgoing transfer ü _av . In AND levels A ₁ , & ₂ , & ₃ . The outputs of this and the input stage & ₃ is also the clock signal τ ₂ stages are switched to an OR stage ν, which is a 60 input. The outgoing transfer üav is connected downstream in the or-not stage E. At the output α buffer ZS stored and appears on the affirmative and at the output Έ the negated output α correspondingly amplified.
Signal on. At the AND stage Sc ₁ (holding stage), the one assigned to the output memory AS , the signal returned from the output α and the output stage Sc ₃ ' become the negated clock signal τ "from the incoming. On the AND stage & ₃ (input 05 carry and from the buffer ZS gebilstufe) the affirmed clock signal τ and the input signals to be deten via _er and ü _ar supplied as the storing value (L or 0). If a clock signal τ = Z. is indicated by the dashed circle. Furthermore (T is then 0) and an input signal e - L is on, the clock signal X ₁ acts on this input stage & _s '.

The holding stage Sc ₁ is switched in exactly the same way as the holding stage Sc ₁ . It is only supplied with the clock signal T _1. The AND stage Sc ₂ is controlled by the output a "of the output memory AS and also by the negated outgoing carry _{value a} " of the intermediate memory ZS. Finally, in order to reset the counter to the initial position (α, = O), this AND stage Sc ₂ 'can then be activated by a clear signal / = 0, as well as T ₁ , T ₂ and ü _e , = 0.

In the buffer ZS outbound transfer above _a is formed. In the input stage Sc ₃ ' , ü _{} r} and ü _{ar are} entered for the summation.

According to Table 2, as can be seen from the second line, the sum s = L is formed when ü _er and üav - L. According to table 2 ^ _ line 3, the sum s, also = L, if a, and ü _a , = L.

The input and bypass stages & ₃ '&_2' of the counting device according to the Fi ^ ₁ 8 will now be, as shown, with the on _he u, ü _a, or a _y, u _a, applied to values that occur. If the inputs of these stages & _s ', Sc _{2 have} the value L and also the additional inputs T ₁ , /, then the outputs of the AND stages & ₂ ', & ₃ ' = L.

The AND stage Sc ₂ ' is therefore also used to form the sum. In addition, it is also used to create the secondary connection. The AND stage & / _ forms part of the sum, namely üep and üar, and the AND stage & ₂ 'forms the other part of the sum, namely Έ _α , and a _v . The sum will either occur at the output of the AND stage Sc ₂ or Sc ₃ ' . These two elements are followed by an OR stage v ". In reality, this OR stage v" can be contained in the OR stage v 'assigned to the output memory AS. At the output of the OR stage v " , the value s, is thus produced.

10 shows the diagram for the_Taktsignale T ₁ , T ₁ , τ ₂ , T ₂ and the erase signals /, /. The value 0 can represent, for example, a specific negative voltage value and the value L a specific positive voltage value. The situation can also be reversed.

The counting device may be deleted when the clock signals T _1, T _2, the incoming carry signal u / are brought to 0 _he and the clear signal. If the clock signals T ₁ , T ₂ - 0, then the self-holding via the holding stages Sc ₁ , Sc _{1 is} canceled.

Claims (4)

Patent claims: 1. DC-coupled electronic binary counter based on the principle of addition, at the outputs of which signals appear in natural binary code in parallel representation, which for each binary digit consists of two output and buffer memories for 1 bit that are directly coupled in itself and with one another and controlled at different times by mutually incompatible clock signals Switching state is determined by influencing only one amplifier element per memory, characterized in that the input circuit of each memory (AS, ZS) connected to an amplifier element consists of logic circuits (&) which cause the memory to be set and hold and which consist of the clock signals_ (T, T) and the memory output signals (A, H, H) form overlapping partial signals which, when combined (OR stage in Fig. 8, 9) generate a signal without gaps over the duration of the partial signals as an output signal for the memory, and that the Output signal of each buffer both the input controls the input circuit of the assigned output memory as well as the input circuits of the ίο output-buffer combination of the following binary digit. 2. Counter according to claim 1, characterized in that in the lowest binary digit the output signal of output and buffer stores is formed from the combination of the respective clock signal (T ₁ or T ₂ ) and the correspondingly negated clock signal (T ₁ or T ₃ ) with its own output signal and the output signal of the associated memory and in ao the following higher binary digits additionally that Output signal of the buffer of the preceding binary digit is also used. 3. Counter according to claim 1 and 2, characterized in that both the education and Veras Strengthening of the carry signal as well as the sum signal with two equal of And- and Or / Or-non-stages existing logic circuits takes place (Fig. 8). 4. Counter according to claim 1 to 3, characterized in that the carry circuit consists of three and-stages (Sc ₁ , & ₂ , Sc ^) acting as holding stages, temporal shunt stage and input stage, to which an or / or-not stage ( v, E) , at whose affirmative output (a) the outgoing carry signal (üar) is picked up, and that the summing circuit also consists of three AND stages (A ₁ ', & ₂ \ &g') acting as holding stage, temporal shunt stage and input stage, to which an or / or -not stage ( v ', E') , at whose output (a,) the result of the summation occurs, and that the input stage (& ₃ ) and the shunt stage (& ₂ ) of the carry circuit through the incoming carry signal (over) and the result signal (a _v ) of the assigned summing circuit are controlled, while the input stage (& _s ') of the summing circuit is controlled by the incoming carry signal (ü _ev ) and the negated outgoing carry signal (ίΓ _αν ), and the shunt stage (Sc ₂ ) of the summing circuit is also controlled by the negated outgoing carry signal (üar) and the result signal (α,) of the summing circuit. Considered publications: Arithmetic Operation in Digitral Computers, D. van Norhand Comp., Inc. N. Y., 1955, pp. 86, 196, 197; Automatic Digital Computers, Methnen & Co. Ltd., London, 1956, p. 63; Digital computing systems, Springer-Verlag, Berlin, 1961, p. 179; Electronic Digital Computers, McGran Hill Rook comp., Inc., London, New York, 1959, pp. 202 to 205, pp. ₅ 140, 141. 1 sheet of drawings