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US20170373059A1 - Finfet and manufacturing method of the same - Google Patents

Finfet and manufacturing method of the same Download PDF

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Publication number
US20170373059A1
US20170373059A1 US15/299,479 US201615299479A US2017373059A1 US 20170373059 A1 US20170373059 A1 US 20170373059A1 US 201615299479 A US201615299479 A US 201615299479A US 2017373059 A1 US2017373059 A1 US 2017373059A1
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Prior art keywords
gate electrode
structures
finfet
fin
drain
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Abandoned
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US15/299,479
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English (en)
Inventor
Ta-Hsun Yeh
Cheng-Wei Luo
Hsiao-Tsung Yen
Yuh-Sheng Jean
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Assigned to REALTEK SEMICONDUCTOR CORPORATION reassignment REALTEK SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEAN, YUH-SHENG, LUO, CHENG-WEI, YEH, TA-HSUN, YEN, HSIAO-TSUNG
Publication of US20170373059A1 publication Critical patent/US20170373059A1/en
Priority to US16/167,554 priority Critical patent/US10373954B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H01L27/0886—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/823431—
    • H01L29/0847—
    • H01L29/7851—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P50/642—

Definitions

  • the present disclosure relates to a semiconductor technology. More particularly, the present disclosure relates to a FinFET and a manufacturing method of the same.
  • transistors Due to the shrinking size of semiconductor circuits and the higher demand of the driving ability, transistors are required to generate large driving currents under the condition that the size of the transistors becomes smaller. Leakage current is easily generated when the gate length of the conventional transistors becomes smaller than 20 nano meters. Further, the influence of the gate on the channel decreases when the gate length shrinks. Under such a condition, FinFETs that have three-dimensional source structures and drain structures successfully address the above issues and become the mainstream semiconductor technology in recent years.
  • An aspect of the present invention is to provide a fin field effect transistor (FinFET) that comprises a semiconductor substrate, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure.
  • the semiconductor substrate includes a plurality of insulating areas.
  • the fin structure is disposed to extend on the semiconductor substrate between two of the insulating areas.
  • the gate dielectric layer is disposed to extend across two sides of the fin structure.
  • the gate electrode structure is disposed on the gate dielectric layer.
  • the drain structure is disposed at a first side of the fin structure relative to the gate electrode structure and has a first resistance relative to the gate electrode.
  • the source structure is disposed at a second side of the fin structure relative to the gate electrode structure and has a second resistance relative to the gate electrode, wherein the first resistance is larger than the second resistance.
  • a transistor precursor that includes a semiconductor substrate, a fin structure, a gate dielectric layer and a gate electrode structure is provided.
  • the semiconductor substrate includes a plurality of insulating areas.
  • the fin structure is disposed to extend on the semiconductor substrate between two of the insulating areas.
  • the gate dielectric layer is disposed to extend across two sides of the fin structure.
  • the gate electrode structure is disposed on the gate dielectric layer.
  • Etching is performed on a first position and a second position of the fin structure, wherein the first position is at a first side of the fin structure relative to the gate electrode structure and the second position is at a second side of the fin structure relative to the gate electrode structure.
  • a drain structure at the first position is formed and a source structure is formed at the second position, wherein the drain structure has a first resistance relative to the gate electrode and the source structure has a second resistance relative to the gate electrode, and the first resistance is larger than the second resistance.
  • FIG. 1A is a three-dimensional (3-D) diagram of a FinFET in an embodiment of the present invention
  • FIG. 1B is a top view of the FinFET along the direction A in FIG. 1 in an embodiment of the present invention
  • FIG. 2A is a three-dimensional (3-D) diagram of a FinFET in an embodiment of the present invention
  • FIG. 2B is a top view of the FinFET along the direction A in FIG. 2A in an embodiment of the present invention
  • FIG. 2C is a three-dimensional (3-D) diagram of a FinFET in an embodiment of the present invention.
  • FIG. 2D is a top view of the FinFET along the direction A in FIG. 2C in an embodiment of the present invention
  • FIG. 3 is a flow chart of a FinFET manufacturing method in an embodiment of the present invention.
  • FIGS. 4A-4C are top views of the components in each steps of the FinFET manufacturing method in an embodiment of the present invention.
  • FIG. 5 is a three-dimensional (3-D) diagram of the FinFET and the FinFET illustrated in FIG. 4C in an embodiment of the present invention
  • FIG. 6 is a flow chart of a FinFET manufacturing method in an embodiment of the present invention.
  • FIGS. 7A-7C are top views of the components in each steps of the FinFET manufacturing method in an embodiment of the present invention.
  • FIG. 1A is a three-dimensional (3-D) diagram of a fin field effect transistor (FinFET) 1 in an embodiment of the present invention.
  • FIG. 1B is a top view of the FinFET 1 along the direction A in FIG. 1 in an embodiment of the present invention.
  • the FinFET 1 includes a semiconductor substrate 100 , fin structures 102 A and 102 B, a gate dielectric layer 104 , a gate electrode structure 106 , drain structures 108 A and 108 B and source structures 110 A and 110 B. It is appreciated that since the gate dielectric layer 104 is covered by the gate electrode structure 106 , the gate dielectric layer 104 is illustrated by using dashed lines in FIG. 1A and FIG. 1B .
  • the semiconductor substrate 100 is such as, but not limited to a silicon substrate.
  • the semiconductor substrate 100 includes a plurality of insulating areas 101 .
  • the insulating areas 101 include such as, but not limited to shallow trench isolation structures.
  • the insulating areas 101 includes insulating material such as, but not limited to silicon oxide.
  • the silicon oxide is SiO 2 .
  • Each of the fin structures 102 A and 102 B is disposed to extend on the semiconductor substrate 100 between two of the insulating areas 101 .
  • the original semiconductor substrate 100 has a height the same as the height of the fin structures 102 A and 102 B.
  • insulating material is deposited such that the part of the semiconductor substrate 100 between the two insulating areas 101 serves as the fin structures 102 A and 102 B.
  • the fin structures 102 A and 102 B can also be epitaxially grown from the surface of the semiconductor substrate 100 .
  • the gate dielectric layer 104 is disposed to extend across two sides of the fin structures 102 A and 102 B. In an embodiment, the direction of the gate dielectric layer 104 is disposed to be substantially orthogonal to the fin structures 102 A and 102 B. It is appreciated that the term “substantially orthogonal” means that the angle between the gate dielectric layer 104 and the fin structures 102 A and 102 B is not necessarily 90 degrees and can have a reasonable offset from 90 degrees.
  • the gate dielectric layer 104 can include such as, but not limited to high K material.
  • the gate electrode structure 106 is disposed on the gate dielectric layer 104 .
  • the gate electrode structure 106 includes such as, but not limited to metal material.
  • a semiconductor channel is formed at the positions of the fin structures 102 A and 102 B corresponding to the gate electrode structure 106 and the gate dielectric layer 104 to allow the electrical current flowing through.
  • Each of the drain structures 108 A and 108 B is disposed at a first side of the fin structures 102 A and 102 B relative of the gate electrode structure 106 .
  • Each of the source structures 110 A and 110 B is disposed at a second side of the fin structures 102 A and 102 B relative to the gate electrode structure 106 .
  • the drain structures 108 A and 108 B and the source structures 110 A and 110 B are formed by such as, but not limited to epitaxial growth.
  • the material of the drain structures 108 A and 108 B and the source structures 110 A and 110 B includes such as, but not limited to SiGe.
  • the drain structures 108 A and 108 B are electrically coupled to each other.
  • the source structures 110 A and 110 B are electrically coupled to each other.
  • the resistance of each of the drain structures 108 A and 108 B relative to the gate electrode 106 is larger than the resistance of each of the source structures 110 A and 110 B relative to the gate electrode 106 .
  • the drain structures 108 A and 108 B and the gate electrode structure 106 have a first distance D 1 therebetween.
  • the source structures 110 A and 110 B and the gate electrode structure 106 have a second distance D 2 therebetween, wherein the first distance D 1 is larger than the second distance D 2 . Accordingly, by using the disposition of different distances, the resistance of each of the drain structures 108 A and 108 B relative to the gate electrode 106 is larger than the resistance of each of the source structures 110 A and 110 B relative to the gate electrode 106 .
  • the drain structures 108 A and 108 B can be either directly electrically coupled to a first voltage source (not illustrated) or electrically coupled to the first voltage source through other electric components.
  • the source structures 110 A and 110 B can be either directly electrically coupled to a second voltage source (not illustrated) or electrically coupled to the second voltage source through other electric components.
  • the voltage level of the first voltage source is higher than that of the second voltage source.
  • the FinFET 1 of the present invention Since in the FinFET 1 of the present invention, the first distance D 1 between the drain structures 108 A and 108 B and the gate electrode structure 106 is larger than the second distance D 2 , the FinFET 1 has a larger resistance between the drain structures 108 A and 108 B and the gate electrode structure 106 .
  • the FinFET 1 when the FinFET 1 is operated under a high voltage condition, i.e. the first voltage source that the drain structures 108 A and 108 B is electrically coupled to has a higher voltage, a larger voltage can be endured across the region between the drain structures 108 A and 108 B and the gate electrode structure 106 .
  • the high voltage across the semiconductor channel corresponding to the gate electrode structure 106 and the gate dielectric layer 104 can be avoided.
  • the embodiment that has two fin structures 102 A and 102 B and the corresponding two drain structures 108 A and 108 B and two source structures 110 A and 110 B is merely an example.
  • the FinFET 1 has one or more fin structures and correspondingly has one or more drain structures and one or more source structures.
  • FIG. 2A is a three-dimensional (3-D) diagram of a FinFET 2 in an embodiment of the present invention.
  • FIG. 2B is a top view of the FinFET 2 along the direction A in FIG. 2A in an embodiment of the present invention.
  • the FinFET 2 includes the semiconductor substrate 100 , the fin structures 102 A and 102 B, the gate dielectric layer 104 , the gate electrode structures 106 , the drain structures 108 A and 108 B and the source structures 110 A and 110 B.
  • the semiconductor substrate 100 , the gate dielectric layer 104 and the gate electrode structures 106 are identical to those in the FinFET 1 . As a result, the details of these components are not described herein.
  • the distance of the drain structures 108 A and 108 B relative to the gate electrode structure 106 and distance of the source structures 110 A and 110 B relative to the gate electrode structure 106 are the same.
  • the fin structures 102 A and 102 B further include trenches 200 A and 200 B between the gate electrode structure 106 and the drain structures 108 A and 108 B.
  • the current that flows from the drain structures 108 A and 108 B to the channel has to pass through the parts under the trenches 200 A and 200 B. Since the area that the current flows through is smaller, the FinFET 2 has a larger resistance between the drain structures 108 A and 108 and the gate electrode structure 106 .
  • the FinFET 2 in the present embodiment can endure a higher voltage across the drain structures 108 A and 108 B and the gate electrode structure 106 . As a result, FinFET 2 in the present embodiment can be operated under a high voltage condition.
  • FIG. 2C is a three-dimensional (3-D) diagram of a FinFET 2 ′ in an embodiment of the present invention.
  • FIG. 2D is a top view of the FinFET 2 ′ along the direction A in FIG. 2C in an embodiment of the present invention.
  • the FinFET 2 ′ includes the semiconductor substrate 100 , the fin structures 102 A and 102 B, the gate dielectric layer 104 , the gate electrode structures 106 , the drain structures 108 A and 108 B and the source structures 110 A and 110 B. Further, the fin structures 102 A and 102 B of the FinFET 2 ′ also have the trenches 200 A and 200 B. However, in the present embodiment, the first distance D 1 between the drain structures 108 A and 108 B and the gate electrode structure 106 is larger than the second distance D 2 .
  • the FinFET 2 ′ combines the structure of the FinFET 1 illustrated in FIG. 1A and FIG. 1B and the FinFET 2 illustrated in FIG. 2A and FIG. 2B such that an even higher resistance between the drain structures 108 A and 108 B and the gate electrode structure 106 is obtained.
  • the FinFET 2 ′ can endure even larger voltage across the drain structures 108 A and 108 B and the gate electrode structure 106 and is more suitable under the high voltage operation condition.
  • FIG. 3 is a flow chart of a FinFET manufacturing method 300 in an embodiment of the present invention.
  • FIGS. 4A-4C are top views of the components in each steps of the FinFET manufacturing method 300 in an embodiment of the present invention.
  • the FinFET manufacturing method 300 is used to manufacture such as, but not limited to the FinFET 1 illustrated in FIG. 1A and FIG. 1B .
  • the FinFET manufacturing method 300 includes the steps outlined below. The steps are not recited in the sequence in which the steps are performed. That is, unless the sequence of the steps is expressly indicated, the sequence of the steps is interchangeable, and all or part of the steps may be simultaneously, partially simultaneously, or sequentially performed.
  • a transistor precursor 4 illustrated in FIG. 4A is provided.
  • the transistor precursor 4 includes the semiconductor substrate 100 , the gate dielectric layer 104 , the gate electrode structure 106 , and the fin structures 102 A′ and 102 B′ that are not etched yet.
  • step 302 as illustrated in FIG. 4B , etching is performed at first positions 400 A and 400 B and second positions 400 C and 400 D of the fin structure 102 A′ and 102 B′.
  • the first positions 400 A and 400 B are at a first side of the fin structures 102 A′ and 102 B′ relative to the gate electrode structure 106 and has a first distance D 1 from the gate electrode structure 106 .
  • the second positions 400 C and 400 D are at a second side of the fin structures 102 A′ and 102 B′ relative to the gate electrode structure 106 and has a second distance D 2 from the gate electrode structure 106 .
  • the first distance D 1 is larger than the second distance D 2 .
  • the etching step is performed by such as, but not limited to defining the etching region on the transistor precursor 4 by hard mask (not illustrated) such that the etching process is performed thereafter.
  • the drain structures 108 A and 108 B at the first positions are formed and the source structures 110 A and 110 B are formed at the second positions.
  • the drain structures 108 A and 108 B and the source structures 110 A and 110 B are formed by such as, but not limited to epitaxial growth.
  • the semiconductor device that includes the semiconductor substrate 100 , the fin structures 102 A and 102 B, the gate dielectric layer 104 , the gate electrode structure 106 , the drain structures 108 A and 108 B and the source structures 110 A and 110 B is equivalent to the FinFET 1 illustrated in FIG. 1B .
  • the transistor precursor 4 provided in step 301 may further include the fin structures 402 A′ and 402 B′ that are not etched yet, the gate dielectric layer 404 and the gate electrode structure 406 on the semiconductor substrate 100 .
  • the positions 420 A- 420 D that correspond to the first side and the second side of the gate electrode structure 406 and have equal distances therefrom can be etched simultaneously.
  • the distance between each of the etched positions and the gate electrode structure 406 is equivalent to the second distance D 2 .
  • drain structures 408 A and 408 B and the source structures 410 A and 410 B can be simultaneously formed at the etched positions mentioned above. Accordingly, the semiconductor device that includes the semiconductor substrate 100 , the etched fin structures 402 A and 402 B, the gate dielectric layer 404 , the gate electrode structure 406 , the drain structures 408 A and 408 B and the source structures 410 A and 410 B is equivalent to another FinFET 430 .
  • FIG. 5 is a three-dimensional (3-D) diagram of the FinFET 1 and the FinFET 430 illustrated in FIG. 4C in an embodiment of the present invention.
  • the FinFET 1 that includes the drain structures 108 A and 108 B and the source structures 110 A and 110 B having non-equal distances and the FinFET 400 that includes the drain structures 408 A and 408 B and the source structures 410 A and 410 B having equal distances can be formed by using a single manufacturing process.
  • the FinFET 1 not only can be formed by using the same manufacturing method as the FinFET 430 without additional steps, but also can be formed simultaneously with the FinFET 430 .
  • the compatibility of the manufacturing method is ideal.
  • FIG. 6 is a flow chart of a FinFET manufacturing method 600 in an embodiment of the present invention.
  • FIGS. 7A-7C are top views of the components in each steps of the FinFET manufacturing method 600 in an embodiment of the present invention.
  • the FinFET manufacturing method 600 is used to manufacture such as, but not limited to the FinFET 2 illustrated in FIG. 2A and FIG. 2B .
  • the FinFET manufacturing method 600 includes the steps outlined below. The steps are not recited in the sequence in which the steps are performed. That is, unless the sequence of the steps is expressly indicated, the sequence of the steps is interchangeable, and all or part of the steps may be simultaneously, partially simultaneously, or sequentially performed.
  • a transistor precursor 7 illustrated in FIG. 7A is provided.
  • the transistor precursor 7 includes the semiconductor substrate 100 , the gate dielectric layer 104 , the gate electrode structure 106 , and the fin structures 102 A′ and 102 B′ that are not etched yet.
  • step 602 as illustrated in FIG. 7B , etching is performed at first positions 400 A and 400 B and second positions 400 C and 400 D of the fin structure 102 A′ and 102 B′.
  • step 603 etching is performed on the fin structure 102 A′ and 102 B′ between the gate electrode structure 106 and the first positions 400 A and 400 B to form trenches 200 A and 200 B.
  • the etching step mentioned above is performed by such as, but not limited to defining the etching region on the transistor precursor 7 by hard mask (not illustrated) such that the etching process is performed thereafter.
  • the etching in steps 602 and 603 can be performed simultaneously by using a single mask without additional steps.
  • the drain structures 108 A and 108 B are formed at the first positions and the source structures 110 A and 110 B are formed at the second positions.
  • the drain structures 108 A and 108 B and the source structures 110 A and 110 B are formed by such as, but not limited to epitaxial growth.
  • the semiconductor device that includes the semiconductor substrate 100 , the fin structures 102 A and 102 B, the gate dielectric layer 104 , the gate electrode structure 106 , the drain structures 108 A and 108 B, the source structures 110 A and 110 B and the trenches 200 A and 200 B is equivalent to the FinFET 2 illustrated in FIG. 2B .
  • the semiconductor device that includes the components mentioned above is equivalent to the FinFET 2 ′ illustrated in FIG. 2D .
  • another FinFET 430 that includes the drain structures 408 A and 408 B and the source structures 410 A and 410 B having equal distances from the gate electrode structure 406 can also be formed in steps 601 to 603 .
  • the FinFET 2 not only can be formed by using the same manufacturing method as the FinFET 430 without additional steps, but also can be formed simultaneously with the FinFET 430 .
  • the compatibility of the manufacturing method is ideal.
  • the above embodiment is described by using the structure that the depth of the trenches 200 A and 200 B equals to the height of the fin structures 102 A and 102 B relative to the semiconductor substrate 100 as the example.
  • additional masks are required to perform two stages of etching.

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  • Engineering & Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Citations (2)

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US20160056232A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device structure including a fin-embedded isolation region and methods thereof

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US7348642B2 (en) * 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
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