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US20140084413A1 - Package substrate and method of fabricating the same - Google Patents

Package substrate and method of fabricating the same Download PDF

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Publication number
US20140084413A1
US20140084413A1 US13/965,842 US201313965842A US2014084413A1 US 20140084413 A1 US20140084413 A1 US 20140084413A1 US 201313965842 A US201313965842 A US 201313965842A US 2014084413 A1 US2014084413 A1 US 2014084413A1
Authority
US
United States
Prior art keywords
substrate
protective layer
conductive
insulating protective
package substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/965,842
Other languages
English (en)
Inventor
Yu-Hua Chen
Wei-Chung Lo
Dyi-chung Hu
Chang-Hong HSIEH
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Unimicron Technology Corp
Original Assignee
Industrial Technology Research Institute ITRI
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI, Unimicron Technology Corp filed Critical Industrial Technology Research Institute ITRI
Assigned to Unimicron Technology Corporation, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE reassignment Unimicron Technology Corporation ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LO, WEI-CHUNG, HU, DYI-CHUNG, HSIEH, CHANG-HONG, CHEN, YU-HUA
Publication of US20140084413A1 publication Critical patent/US20140084413A1/en
Priority to US15/468,087 priority Critical patent/US10068847B2/en
Priority to US16/036,946 priority patent/US10867907B2/en
Priority to US17/095,744 priority patent/US11854961B2/en
Priority to US17/095,742 priority patent/US11791256B2/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H10W20/42—
    • H10W70/05—
    • H10W70/65—
    • H10W70/685—
    • H10W90/00—
    • H10W90/401—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to package substrates and methods of fabricating the same, and relates to a package substrate having an embedded interposer and a method of fabricating the same.
  • the present disclosure provides a package substrate that integrates an interposer and passive components.
  • the package substrate may include: a substrate with wirings, a first surface and a second surface opposing the first surface, the first surface including a plurality of conductive pads; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in the insulating protective layer and electrically connected to the substrate, the interposer including a plurality of penetrating conductive vias and a wiring redistribution layer exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate.
  • FIG. 1 is a cross-sectional view of a package substrate according to a first embodiment of the present disclosure
  • FIGS. 2A to 2C are cross-sectional views of a package substrate according to a second embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view of a package substrate according to a third embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a package substrate according to a fourth embodiment of the present disclosure.
  • Conductive vias refers to conductive components formed on a substrate, for example, the interposer herein. As shown in the diagrams, the shape of the conductive vias can be columnar.
  • FIG. 1 a cross-sectional view of a package substrate 2 according to a first embodiment of the present disclosure is shown.
  • a substrate 20 having wirings 200 , a top surface (can be regarded as a first surface) 20 a and a bottom surface (can be regarded as a second surface) 20 b is provided.
  • the substrate 20 is a multilayer interconnect base plate.
  • the top surface 20 a has a plurality of conductive pads 21 a.
  • An interposer 22 and an insulating protective layer 23 are formed on the top surface 20 a.
  • the interposer 22 is embedded into the insulating protective layer 23 and exposed from the surface of the insulating protection layer 23 .
  • a plurality of passive components 24 are provided on the interposer 22 .
  • the interposer 22 is a silicon interposer and has a plurality of penetrating conductive vias 221 and a wiring redistribution layer (RDL) 222 exposed from the insulating protective layer 23 .
  • the bottom ends of the conductive vias 221 are each connected to conductive pads 21 a to electrically connect with the wirings 200 , and the passive components 24 are arranged on the wiring redistribution layer 222 to be electrically connected with the interposer 22 .
  • the passive components 24 By disposing the passive components 24 on the wiring redistribution layer 222 , when an active component (not shown) such as a semiconductor chip is provided on the wiring redistribution layer 222 , the active component can be assembled in a way that it is closest to the passive components 24 , thereby reducing the distance between the active component and the passive components 24 .
  • an active component such as a semiconductor chip
  • Signals are transmitted to the substrate 20 through the wiring redistribution layer 222 and the passive components 24 connected in series, and the conductive vias 221 , so that the electrical connection path between the active component and the passive components 24 is made shortest. As a result, the pins of the active component have stable voltage.
  • FIGS. 2A to 2C cross-sectional views of a package substrate 3 according to a second embodiment of the present disclosure are shown.
  • the second embodiment differs from the first embodiment in the locations and the electrical connection method of the passive components 24 .
  • a plurality of holes 230 are formed in the insulating protective layer 23 at locations corresponding to a portion of the exposed conductive pads 21 a by using a fixed-depth mechanical drilling method or a laser drilling method.
  • conductive components 231 such as columns are formed in the holes 230 by electroplating, printing, plugging or spin-coating techniques.
  • the conductive components 231 are made of conductive adhesives or electroplated metals, such as copper paste or silver glue.
  • the passive components 24 are provided on the conductive components 231 .
  • the passive components 24 are electrically connected to the conductive pads 21 a through the conductive components 231 .
  • an active component (not shown) with a larger size can be provided on the wiring redistribution layer 222 .
  • the present disclosure reduces the electrical connection path between the active component and the passive components 24 , and allows the voltage of the pins of the active component to be more stable.
  • FIG. 3 a cross-sectional view of a package substrate 4 according to a third embodiment of the present disclosure is shown.
  • the third embodiment differs from the second embodiment in the locations and the electrical connection method of the passive components 24 .
  • a plurality of holes 232 are formed in the insulating protective layer 23 at locations corresponding to a portion of the exposed conductive pads 21 a by using a fixed-depth mechanical drilling method or a laser drilling method. Then, the passive components 24 are soldered onto the conductive pads 21 a in the holes 232 by dispensing, such that the passive components 24 are in contact with and electrically connected to the conductive pads 21 a.
  • the height of the package substrate 4 can be reduced to facilitate product thinning.
  • the present disclosure reduces the electrical connection path between the active component and the passive components 24 , and allows the voltage of the pins of the active component to be more stable.
  • the wiring redistribution layer 222 of the interposer 22 is used for at least a active component such as a semiconductor chip (not shown) to be disposed, and packaging process is performed to form a semiconductor package.
  • At least a passive component 24 ′ can be buried in the substrate 20 and electrically connected to the wirings 200 , as shown by the package substrate 4 ′ in FIG. 4 .
  • the bottom surface 20 b of the substrate 20 of the present disclosure may also have conductive pads 2 lb for electrical connection to other electrical devices, such as circuit boards or package structures.
  • a coreless substrate 20 is used for illustrating the various embodiments described above, a substrate with a core layer can also be applied in the package substrates of the present disclosure, and is deemed to be within the range of the claims of the present disclosure.
  • the interposer 22 is integrated with the passive components 24 , so when an active component is provided on the interposer 22 , the distance between the active component and the passive components 24 is reduced, i.e., the electrical connection path between the active component and the passive components 24 is shortened. Therefore, the voltage of the pins of the active component can be more stable, and the electrical performance of the final electronic product is enhanced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
US13/965,842 2012-09-26 2013-08-13 Package substrate and method of fabricating the same Abandoned US20140084413A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US15/468,087 US10068847B2 (en) 2012-09-26 2017-03-23 Package substrate and method of fabricating the same
US16/036,946 US10867907B2 (en) 2012-09-26 2018-07-17 Package substrate and method of fabricating the same
US17/095,744 US11854961B2 (en) 2012-09-26 2020-11-12 Package substrate and method of fabricating the same and chip package structure
US17/095,742 US11791256B2 (en) 2012-09-26 2020-11-12 Package substrate and method of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101135246 2012-09-26
TW101135246A TWI483365B (zh) 2012-09-26 2012-09-26 封裝基板及其製法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/468,087 Division US10068847B2 (en) 2012-09-26 2017-03-23 Package substrate and method of fabricating the same

Publications (1)

Publication Number Publication Date
US20140084413A1 true US20140084413A1 (en) 2014-03-27

Family

ID=50318680

Family Applications (4)

Application Number Title Priority Date Filing Date
US13/965,842 Abandoned US20140084413A1 (en) 2012-09-26 2013-08-13 Package substrate and method of fabricating the same
US15/468,087 Active US10068847B2 (en) 2012-09-26 2017-03-23 Package substrate and method of fabricating the same
US16/036,946 Active US10867907B2 (en) 2012-09-26 2018-07-17 Package substrate and method of fabricating the same
US17/095,742 Active 2034-03-02 US11791256B2 (en) 2012-09-26 2020-11-12 Package substrate and method of fabricating the same

Family Applications After (3)

Application Number Title Priority Date Filing Date
US15/468,087 Active US10068847B2 (en) 2012-09-26 2017-03-23 Package substrate and method of fabricating the same
US16/036,946 Active US10867907B2 (en) 2012-09-26 2018-07-17 Package substrate and method of fabricating the same
US17/095,742 Active 2034-03-02 US11791256B2 (en) 2012-09-26 2020-11-12 Package substrate and method of fabricating the same

Country Status (3)

Country Link
US (4) US20140084413A1 (zh)
CN (1) CN103681588B (zh)
TW (1) TWI483365B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150115469A1 (en) * 2013-10-25 2015-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and method for manufacturing the same
EP2978020A1 (en) * 2014-07-25 2016-01-27 Dyi-Chung Hu Package substrate
TWI550814B (zh) * 2015-07-31 2016-09-21 矽品精密工業股份有限公司 承載體、封裝基板、電子封裝件及其製法
US20170047310A1 (en) * 2015-08-13 2017-02-16 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
CN107170730A (zh) * 2016-03-08 2017-09-15 胡迪群 具有双面细线重新分布层的封装基材
US10687419B2 (en) * 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US12538419B2 (en) 2024-04-09 2026-01-27 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
TWI542263B (zh) * 2014-07-31 2016-07-11 恆勁科技股份有限公司 中介基板及其製法
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
TWI557853B (zh) * 2014-11-12 2016-11-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9852994B2 (en) * 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges
KR102487563B1 (ko) * 2015-12-31 2023-01-13 삼성전자주식회사 반도체 패키지 및 그 제조방법
TWI647805B (zh) * 2016-09-09 2019-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
US10510645B2 (en) * 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Planarizing RDLs in RDL-first processes through CMP process
US11527462B2 (en) * 2019-12-13 2022-12-13 International Business Machines Corporation Circuit substrate with mixed pitch wiring
TWI778406B (zh) * 2020-08-26 2022-09-21 矽品精密工業股份有限公司 電子封裝件及其製法

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US7375022B2 (en) * 2004-12-28 2008-05-20 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring board
US20110063806A1 (en) * 2006-05-02 2011-03-17 Ibiden Co., Ltd. Heat resistant substrate incorporated circuit wiring board

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JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US7936567B2 (en) * 2007-05-07 2011-05-03 Ngk Spark Plug Co., Ltd. Wiring board with built-in component and method for manufacturing the same
KR20100037300A (ko) * 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
US8003515B2 (en) * 2009-09-18 2011-08-23 Infineon Technologies Ag Device and manufacturing method
TWI460834B (zh) * 2010-08-26 2014-11-11 欣興電子股份有限公司 嵌埋穿孔晶片之封裝結構及其製法
US20140291001A1 (en) * 2010-11-22 2014-10-02 Bridge Semiconductor Corporation Method of making hybrid wiring board with built-in stiffener and interposer and hybrid wiring board manufactured thereby
TWI418269B (zh) * 2010-12-14 2013-12-01 欣興電子股份有限公司 嵌埋穿孔中介層之封裝基板及其製法
TWI451542B (zh) * 2011-02-10 2014-09-01 Unimicron Technology Corp 嵌埋被動元件之封裝基板
TWM433634U (en) * 2012-03-23 2012-07-11 Unimicron Technology Corp Semiconductor substrate
KR101366461B1 (ko) * 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7375022B2 (en) * 2004-12-28 2008-05-20 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring board
US20110063806A1 (en) * 2006-05-02 2011-03-17 Ibiden Co., Ltd. Heat resistant substrate incorporated circuit wiring board

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150115469A1 (en) * 2013-10-25 2015-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and method for manufacturing the same
US11398421B2 (en) * 2013-10-25 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and method for manufacturing the same
US10181438B2 (en) * 2013-10-25 2019-01-15 Advanced Semiconductor Engineering, Inc. Semiconductor substrate mitigating bridging
US10373918B2 (en) 2014-07-25 2019-08-06 Dyi-chung Hu Package substrate
EP2978020A1 (en) * 2014-07-25 2016-01-27 Dyi-Chung Hu Package substrate
US9627285B2 (en) 2014-07-25 2017-04-18 Dyi-chung Hu Package substrate
TWI550814B (zh) * 2015-07-31 2016-09-21 矽品精密工業股份有限公司 承載體、封裝基板、電子封裝件及其製法
US20170047310A1 (en) * 2015-08-13 2017-02-16 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
CN107170730A (zh) * 2016-03-08 2017-09-15 胡迪群 具有双面细线重新分布层的封装基材
US10687419B2 (en) * 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US11399429B2 (en) 2017-06-13 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor package device
US11956897B2 (en) 2017-06-13 2024-04-09 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US12538419B2 (en) 2024-04-09 2026-01-27 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Also Published As

Publication number Publication date
CN103681588A (zh) 2014-03-26
TW201413894A (zh) 2014-04-01
US20170194249A1 (en) 2017-07-06
US11791256B2 (en) 2023-10-17
US20210066189A1 (en) 2021-03-04
CN103681588B (zh) 2019-02-05
US10867907B2 (en) 2020-12-15
US20180323143A1 (en) 2018-11-08
TWI483365B (zh) 2015-05-01
US10068847B2 (en) 2018-09-04

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AS Assignment

Owner name: UNIMICRON TECHNOLOGY CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, YU-HUA;LO, WEI-CHUNG;HU, DYI-CHUNG;AND OTHERS;SIGNING DATES FROM 20130718 TO 20130731;REEL/FRAME:031022/0053

Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, YU-HUA;LO, WEI-CHUNG;HU, DYI-CHUNG;AND OTHERS;SIGNING DATES FROM 20130718 TO 20130731;REEL/FRAME:031022/0053

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION