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US20140041922A1 - Package carrier and manufacturing method thereof - Google Patents

Package carrier and manufacturing method thereof Download PDF

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Publication number
US20140041922A1
US20140041922A1 US13/615,698 US201213615698A US2014041922A1 US 20140041922 A1 US20140041922 A1 US 20140041922A1 US 201213615698 A US201213615698 A US 201213615698A US 2014041922 A1 US2014041922 A1 US 2014041922A1
Authority
US
United States
Prior art keywords
layer
insulation
insulation substrate
package carrier
patterned circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/615,698
Other languages
English (en)
Inventor
Shih-Hao Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Subtron Technology Co Ltd
Original Assignee
Subtron Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Subtron Technology Co Ltd filed Critical Subtron Technology Co Ltd
Assigned to SUBTRON TECHNOLOGY CO., LTD. reassignment SUBTRON TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SUN, SHIH-HAO
Publication of US20140041922A1 publication Critical patent/US20140041922A1/en
Priority to US14/547,147 priority Critical patent/US9204560B2/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H10P14/40—
    • H10W70/095—
    • H10W70/635—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8582—Means for heat extraction or cooling characterised by their shape
    • H10W90/724—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the invention relates to a package structure and a manufacturing method thereof, and more particularly, to a package carrier and a manufacturing method thereof.
  • chip package The purpose of chip package is to protect exposed chips, to reduce contact density in a chip, and to provide good thermal dissipation for chips.
  • a leadframe serving as a carrier of a chip is usually employed in a conventional wire bonding technique. As contact density in a chip gradually increases, the leadframe which is unable to satisfy current demands on the high contact density is replaced by a package carrier which can achieve favorable contact density.
  • the chip is packaged onto the package carrier by conductive media, such as conductive wires or bumps.
  • LED light-emitting diode
  • the current package technology focuses on decreasing the thermal stress of the package structure to increase the operating life and the reliability of the package structure.
  • the invention provides a package carrier which effectively decreases a thermal expansion difference when the package carrier carries a heating element and increases a using reliability.
  • the invention provides a manufacturing method of a package carrier for manufacturing the aforementioned package carrier.
  • the invention provides a manufacturing method of a package carrier.
  • the manufacturing method includes the following steps.
  • An insulation substrate is provided.
  • the insulation substrate has an upper surface, a lower surface opposite to the upper surface, a plurality of cavities and a plurality of through holes.
  • the cavities are located at the lower surface, and the through holes pass through the insulation substrate and respectively communicate with the cavities to define a plurality of vias.
  • a conductive material is formed in the vias, wherein the conductive material fills up the vias to define a plurality of conductive posts.
  • An insulation layer is formed on the upper surface of the insulation substrate.
  • the insulation layer has a top surface relatively far from the upper surface of the insulation substrate and a plurality of blind vias extending from the top surface to the conductive posts.
  • a patterned circuit layer is formed on the top surface of the insulation layer.
  • the patterned circuit layer fills up the blind vias and is connected to the conductive posts.
  • the patterned circuit layer exposes a portion of the top surface of the insulation layer.
  • a solder mask layer is formed on the patterned circuit layer.
  • the solder mask layer covers the patterned circuit layer and the exposed portion of the top surface of the insulation layer.
  • the solder mask layer has a plurality of openings, wherein the openings expose a portion of the patterned circuit layer so as to define a plurality of pads.
  • a material of the insulation substrate includes ABF resin, polymeric materials, silicon fillers or epoxy resin.
  • a method of forming the cavities of the insulation substrate includes laser drilling or injection molding.
  • a method of forming the through holes of the insulation substrate includes laser drilling.
  • steps of forming the conductive material in the vias include: performing an electroless plating process to form the conductive material on the upper surface, the lower surface and in the vias of the insulation substrate, wherein the conductive material covers the upper surface and the lower surface of the insulation substrate and fills up the vias; and removing a portion of the conductive material on the upper surface and the lower surface of the insulation substrate to expose the upper surface and the lower surface of the insulation substrate so as to define the conductive posts.
  • each of the conductive posts has a first surface and a second surface opposite to each other.
  • the first surface of each of the conductive posts and the upper surface of the insulation substrate are coplanar, and the second surface of each of the conductive posts and the lower surface of the insulation substrate are coplanar.
  • a method of forming the insulation layer includes thermal compression bonding.
  • a material of the insulation layer includes ABF resin, polymeric materials, silicon fillers or epoxy resin.
  • a method of forming the blind vias of the insulation layer includes laser drilling.
  • a method of forming the patterned circuit layer includes electroless plating or a semi-additive process.
  • the manufacturing method further includes forming a surface treatment layer on the pads after the solder mask layer is formed.
  • the surface treatment layer includes an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a nickel-palladium-gold layer or an organic solderability preservatives (OSP) layer.
  • OSP organic solderability preservatives
  • the invention provides a package carrier adapted for carrying a heating element.
  • the package carrier includes an insulation substrate, a plurality of conductive posts, an insulation layer, a patterned circuit layer and a solder mask layer.
  • the insulation substrate has an upper surface, a lower surface opposite to the upper surface, a plurality of cavities and a plurality of through holes.
  • the cavities are located at the lower surface, and the through holes pass through the insulation substrate and respectively communicate with the cavities to define a plurality of vias.
  • the conductive posts are respectively disposed in the vias, and each of the conductive posts has a first surface and a second surface opposite to each other.
  • the first surface of each of the conductive posts and the upper surface of the insulation substrate are coplanar, and the second surface of each of the conductive posts and the lower surface of the insulation substrate are coplanar.
  • An insulation layer is disposed on the upper surface of the insulation substrate.
  • the insulation layer has a top surface relatively far from the upper surface of the insulation substrate and a plurality of blind vias extending from the top surface to the conductive posts.
  • the patterned circuit layer is disposed on the top surface of the insulation layer and exposes a portion of the top surface of the insulation layer.
  • the patterned circuit layer fills up the blind vias and is connected to the conductive posts.
  • a solder mask layer is disposed on the patterned circuit layer.
  • the solder mask layer covers the patterned circuit layer and the exposed portion of the top surface of the insulation layer.
  • the solder mask layer has a plurality of openings, wherein the openings expose a portion of the patterned circuit layer so as to define a plurality of pads, and the heating element is disposed on
  • the package carrier further includes a surface treatment layer disposed on the pads.
  • the surface treatment layer includes an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a nickel-palladium-gold layer or an OSP layer.
  • the package carrier of the invention uses an insulation substrate with an ideal thermal expansion coefficient as a core. Therefore, when the package carrier is used in the package of a heating element (such as a chip) subsequently, a difference in thermal expansion coefficient between the package carrier and the heating element carried on the package carrier is reduced effectively, which prevents a stress between the heating element and the insulation substrate from increasing because of a too great difference in thermal expansion coefficient therebetween and effectively prevents the peeling and damage of the heating element from happening, thereby enhancing the using reliability of the package carrier.
  • a heating element such as a chip
  • FIGS. 1A to 1H are schematic cross-sectional views of a manufacturing method of a package carrier according to an embodiment of the invention.
  • FIG. 2 is a schematic cross-sectional view of the package carrier of FIG. 1H carrying a heating element.
  • FIGS. 1A to 1H are schematic cross-sectional views of a manufacturing method of a package carrier according to an embodiment of the invention.
  • an insulation substrate 110 is provided first.
  • the insulation substrate 110 has an upper surface 112 , a lower surface 114 opposite to the upper surface 112 and a plurality of cavities 116 , wherein the cavities 116 are located at the lower surface 114 of the insulation substrate 110 .
  • a method of forming the cavities 116 of the insulation substrate 110 is, for example, laser drilling or injection molding.
  • a material of the insulation substrate 110 is, for example, ABF resin, polymeric materials, silicon fillers or epoxy resin.
  • each of the through holes 118 and the corresponding cavity 116 define a via T, and a diameter of each of the through holes 118 is substantially less than a diameter of each of the cavities 116 .
  • a method of forming the through holes 118 is, for example, laser drilling.
  • an electroless plating process is performed to form a conductive material 120 on the upper surface 112 , the lower surface 114 and in the vias T of the insulation substrate 110 .
  • the conductive material 120 covers the upper surface 112 and the lower surface 114 of the insulation substrate 110 and fills up the vias T, wherein the conductive material 120 is copper, for example.
  • each of the conductive posts 120 a has a first surface 122 and a second surface 124 opposite to each other.
  • the first surface 122 of each of the conductive posts 120 a and the upper surface 112 of the insulation substrate 110 are substantially coplanar, and the second surface 124 of each of the conductive posts 120 a and the lower surface 114 of the insulation substrate 110 are substantially coplanar.
  • an insulation layer 130 is formed on the upper surface 112 of the insulation substrate 110 , wherein the insulation layer 130 has a top surface 132 relatively far from the upper surface 112 of the insulation substrate 110 .
  • a method of forming the insulation layer 130 is thermal compression bonding, for example.
  • a material of the insulation layer 130 is, for example, ABF resin, polymeric materials, silicon fillers or epoxy resin.
  • blind vias B extending from the top surface 132 of the insulation layer 130 to the conductive posts 120 a are formed, wherein the blind vias B respectively expose the first surface 122 of the conductive posts 120 a .
  • a method of forming the blind vias B of the insulation layer 130 is laser drilling, for example.
  • a patterned circuit layer 140 is formed on the top surface 132 of the insulation layer 130 , wherein the patterned circuit layer 140 fills up the blind vias B and is structurally and electrically connected to the conductive posts 120 a , and the patterned circuit layer 140 exposes a portion of the top surface 132 of the insulation layer 130 .
  • a method of forming the patterned circuit layer 140 is, for example, electroless plating or a semi-additive process, which is not limited herein.
  • a solder mask layer 150 is formed on the patterned circuit layer 140 , wherein the solder mask layer 150 covers the patterned circuit layer 140 and the exposed portion of the top surface 132 of the insulation layer 130 .
  • the solder mask layer 150 has a plurality of openings 152 , wherein the openings 152 expose a portion of the patterned circuit layer 140 to define a plurality of pads 142 .
  • the manufacturing method of the package carrier of the present embodiment may further include forming a surface treatment layer 160 on the pads 142 , wherein the surface treatment layer 160 is, for example, an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a nickel-palladium-gold layer or an organic solderability preservatives (OSP) layer.
  • OSP organic solderability preservatives
  • a method of forming the surface treatment layer 160 is, for example, electro-plating or electroless plating, which is not limited herein. To this point, the manufacturing of the package carrier 100 is completed.
  • the package carrier 100 of the present embodiment includes the insulation substrate 110 , the conductive posts 120 a , the insulation layer 130 , the patterned circuit layer 140 and the solder mask layer 150 .
  • the insulation substrate 110 has an upper surface 112 , a lower surface 114 opposite to the upper surface 112 , a plurality of cavities 116 and a plurality of through holes 118 , wherein the diameter of each of the through holes 118 is substantially less than the diameter of each of the cavities 116 .
  • the cavities 116 are located at the lower surface 114 , and the through holes 118 pass through the insulation substrate 110 and respectively communicate with the cavities 116 to define the vias T.
  • the conductive posts 120 a are respectively disposed in the vias T, and each of the conductive posts 120 a has the first surface 122 and the second surface 124 opposite to each other.
  • the first surface 122 of each of the conductive posts 120 a and the upper surface 112 of the insulation substrate 110 are substantially coplanar, and the second surface 124 of each of the conductive posts 120 a and the lower surface 114 of the insulation substrate 110 are substantially coplanar.
  • the insulation layer 130 is disposed on the upper surface 112 of the insulation substrate 110 .
  • the insulation layer 130 has the top surface 132 relatively far from the upper surface 112 of the insulation substrate 110 and the blind vias B extending from the top surface 132 to the conductive posts 120 a .
  • the patterned circuit layer 140 is disposed on the top surface 132 of the insulation layer 130 and exposes a portion of the top surface 132 of the insulation layer 130 .
  • the patterned circuit layer 140 fills up the blind vias B and is connected to the conductive posts 120 a .
  • the solder mask layer 150 is disposed on the patterned circuit layer 140 , and the solder mask layer 150 covers the patterned circuit layer 140 and the exposed portion of the top surface 132 of the insulation layer 130 .
  • the solder mask layer 150 has the plurality of openings 152 , wherein the openings 152 expose a portion of the patterned circuit layer 140 to define the pads 142 .
  • the package carrier 100 of the present embodiment may further include the surface treatment layer 160 disposed on the pads 142 , wherein the surface treatment layer 160 is, for example, an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a nickel-palladium-gold layer or an OSP layer.
  • the surface treatment layer 160 is, for example, an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a nickel-palladium-gold layer or an OSP layer.
  • the present embodiment uses the insulation substrate 110 as the core of the package carrier 100 , wherein the insulation substrate 110 has an ideal thermal expansion coefficient (similar to a thermal expansion coefficient of a heating element used subsequently, for example), when the package carrier 100 is used in the package of a heating element (not shown) subsequently, a difference in thermal expansion coefficient between the package carrier 100 and the heating element carried on the package carrier 100 is reduced, which prevents a stress between the heating element and the insulation substrate 110 from increasing because of a too great difference in thermal expansion coefficient therebetween and effectively prevents the peeling and damage of the heating element from happening, thereby enhancing the using reliability of the package carrier 100 .
  • the patterned circuit layer 140 of the present embodiment is formed by electroless plating or by the semi-additive process, a width of the patterned circuit layer 140 is able to meet the specification of fine circuits.
  • FIG. 2 is a schematic cross-sectional view of the package carrier of FIG. 1H carrying a heating element.
  • the package carrier 100 is adapted for carrying a heating element 200 , wherein the heating element 200 is disposed on the surface treatment layer 160 on the pads 142 exposed by the openings 152 of the solder mask layer 150 .
  • the heating element 200 is, for example, an electronic chip or a photoelectric device but is not limited thereto.
  • the electronic chip may be an integrated circuit chip, such as a single chip (like a graphic chip, a memory chip, or a semiconductor chip) or a chip module.
  • the photoelectric device is, for example, a LED, a laser diode or a gas-discharge light source.
  • the heating element 200 being a LED serves as an example.
  • the heating element 200 (such as a semiconductor chip) may be electrically connected to the surface treatment layer 160 by flip chip bonding. Since the present embodiment uses the insulation substrate 110 with an ideal thermal expansion coefficient as the core of the package carrier 100 , a difference in thermal expansion coefficient between the package carrier 100 and the heating element 200 is gradually reduced. In this way, a stress between the heating element 200 and the package carrier 100 can be prevented from increasing because of a too great difference in thermal expansion coefficient therebetween, and the peeling and damage of the heating element 200 is effectively prevented from happening, thereby enhancing the using reliability of the package carrier 100 .
  • the package carrier 100 when the heating element 200 is disposed on the package carrier 100 , heat generated by the heating element 200 is transmitted to the outside rapidly through the surface treatment layer 160 , the patterned circuit layer 140 and the conductive posts 120 a . In this way, the package carrier 100 of the present embodiment effectively dissipates the heat generated by the heating element 200 , thereby enhancing the using efficiency and operating life of the heating element 200 .
  • a plurality of solder balls 210 may be disposed on the lower surface 114 of the insulation substrate 110 of the package carrier 100 of the present embodiment, and the package carrier 100 may be electrically connected to an external circuit (not shown) through the solder balls 210 , which effectively enhances the application of the package carrier 100 .
  • the package carrier of the invention uses an insulation substrate with an ideal thermal expansion coefficient as a core. Therefore, when the package carrier is used in the package of a heating element (such as a chip) subsequently, a difference in thermal expansion coefficient between the package carrier and the heating element carried on the package carrier is reduced effectively, which prevents a stress between the heating element and the insulation substrate from increasing because of a too great difference in thermal expansion coefficient therebetween and effectively prevents the peeling and damage of the heating element from happening, thereby enhancing the using reliability of the package carrier.
  • a heating element such as a chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
US13/615,698 2012-08-08 2012-09-14 Package carrier and manufacturing method thereof Abandoned US20140041922A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/547,147 US9204560B2 (en) 2012-08-08 2014-11-19 Manufacturing method of package carrier

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101128619A TWI487041B (zh) 2012-08-08 2012-08-08 封裝載板及其製作方法
TW101128619 2012-08-08

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US20140041922A1 true US20140041922A1 (en) 2014-02-13

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US14/547,147 Expired - Fee Related US9204560B2 (en) 2012-08-08 2014-11-19 Manufacturing method of package carrier

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US (2) US20140041922A1 (zh)
JP (1) JP5509353B2 (zh)
CN (1) CN103579011B (zh)
TW (1) TWI487041B (zh)

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US20150090476A1 (en) * 2013-09-27 2015-04-02 Subtron Technology Co., Ltd. Package carrier and manufacturing method thereof
CN110642220A (zh) * 2018-06-27 2020-01-03 日月光半导体制造股份有限公司 半导体装置封装和其制造方法
US20210359185A1 (en) * 2018-10-19 2021-11-18 Corning Incorporated Device including vias and method and material for fabricating vias
CN113991004A (zh) * 2021-10-26 2022-01-28 东莞市中麒光电技术有限公司 Led基板制作方法、led基板、led器件制作方法及led器件
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CN106298692B (zh) * 2015-04-24 2019-02-01 碁鼎科技秦皇岛有限公司 芯片封装结构的制作方法
CN107613838A (zh) * 2015-05-29 2018-01-19 奥林巴斯株式会社 摄像装置、内窥镜系统以及摄像装置的制造方法
TWI594383B (zh) * 2016-07-04 2017-08-01 欣興電子股份有限公司 封裝基板及其製造方法
CN106376184B (zh) * 2016-07-22 2019-02-01 深南电路股份有限公司 埋入式线路制作方法和封装基板
CN108695266A (zh) * 2017-04-12 2018-10-23 力成科技股份有限公司 封装结构及其制作方法
CN107302826A (zh) * 2017-08-02 2017-10-27 宏齐光电子(深圳)有限公司 一种led封装用pcb基板及其表面处理方法
CN110473944A (zh) * 2018-05-09 2019-11-19 深圳市聚飞光电股份有限公司 多功能led支架及led
TWI682695B (zh) * 2018-07-05 2020-01-11 同泰電子科技股份有限公司 利用防焊限定開窗形成連接端子之電路板結構
CN110752201B (zh) * 2019-10-31 2022-04-15 京东方科技集团股份有限公司 显示背板及其制备方法、显示装置
CN111411323B (zh) * 2020-03-31 2023-01-20 云谷（固安）科技有限公司 一种掩膜板
CN111665982A (zh) * 2020-05-26 2020-09-15 南昌欧菲显示科技有限公司 发光模组、电子设备、传感结构及其制造方法
US20230064560A1 (en) * 2021-08-30 2023-03-02 AUO Corporation Light emitting diode package structure, manufacturing method of light emitting diode package structure and light emitting panel
TWI785856B (zh) * 2021-10-21 2022-12-01 欣興電子股份有限公司 避免翹曲的線路板結構及其製作方法
TWI843121B (zh) * 2022-06-10 2024-05-21 旭德科技股份有限公司 散熱基板
CN116314491A (zh) * 2023-05-25 2023-06-23 江西兆驰半导体有限公司 一种Micro LED灯珠及其制备方法
TWI841502B (zh) * 2023-08-28 2024-05-01 景碩科技股份有限公司 抗彎折強化載板

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CN113991004A (zh) * 2021-10-26 2022-01-28 东莞市中麒光电技术有限公司 Led基板制作方法、led基板、led器件制作方法及led器件

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JP5509353B2 (ja) 2014-06-04
CN103579011B (zh) 2016-05-25

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