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US20130341617A1 - Oxide for semiconductor layer of thin-film transistor, semiconductor layer of thin-film transistor having said oxide, and thin-film transistor - Google Patents

Oxide for semiconductor layer of thin-film transistor, semiconductor layer of thin-film transistor having said oxide, and thin-film transistor Download PDF

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Publication number
US20130341617A1
US20130341617A1 US14/004,020 US201214004020A US2013341617A1 US 20130341617 A1 US20130341617 A1 US 20130341617A1 US 201214004020 A US201214004020 A US 201214004020A US 2013341617 A1 US2013341617 A1 US 2013341617A1
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thin
oxide
semiconductor layer
sputtering
based oxide
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Inventor
Hiroaki Tao
Aya Miki
Shinya Morita
Satoshi Yasuno
Toshihiro Kugimiya
Jae Woo Park
Je Hun Lee
Byung Du Ahn
Gun Hee Kim
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Kobe Steel Ltd
Samsung Display Co Ltd
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Kobe Steel Ltd
Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD., KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.) reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUGIMIYA, TOSHIHIRO, MIKI, AYA, MORITA, SHINYA, TAO, HIROAKI, YASUNO, SATOSHI, LEE, JE HUN, AHN, BYUNG DU, KIM, GUN HEE, PARK, JAE WOO
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    • H10P14/3426—
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H01L29/12—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10P14/22—
    • H10P14/3434—
    • H10P14/3451—
    • H10P95/90—

Definitions

  • the present invention relates to an oxide for a semiconductor layer of a thin-film transistor to be used for display devices such as liquid crystal displays and organic EL displays, and a semiconductor layer; a sputtering target for forming a film of the oxide; and a thin-film transistor having the oxide, and a display device.
  • an amorphous (noncrystalline) oxide semiconductor As compared with widely used amorphous silicon (a-Si), an amorphous (noncrystalline) oxide semiconductor has high carrier mobility, a high optical band gap, and film formability at low temperatures, and therefore, has been highly expected to be applied for next generation displays which are required to have a large size, high resolution, and high-speed drive, resin substrates which has low heat resistance, and the like.
  • Patent Document 1 discloses an amorphous oxide (IZTO) containing elements, such as In, Zn, and Sn, and Mo, where Mo has an atomic composition ratio of 0.1 to 5 atomic % with respect to the total number of metal atoms in the amorphous oxide.
  • IZTO amorphous oxide
  • a TFT including an active layer of IZTO doped with Mo is disclosed in the examples of Patent Document 1.
  • the oxide semiconductor is required not only to have a high electronic carrier concentration but also to be excellent in switching properties (transistor characteristics) of TFT.
  • the oxide semiconductor is required to satisfy (1) high ON-current (maximum drain current when positive voltage is applied to a gate electrode and a drain electrode); (2) low OFF-current (drain current when negative voltage is applied to a gate electrode and positive voltage is applied to a drain voltage); (3) low SS value (Subthreshold Swing, gate voltage required to increase drain current by one digit); (4) stability of threshold voltage when load such as voltage or light irradiation is applied for a long time (voltage at which drain current starts flowing when positive voltage is applied to a drain electrode and either positive or negative voltage is applied to a gate voltage, which is also referred to as threshold voltage); (5) high mobility; (6) uniformity of TFT characteristics in the surface of a large-size grass substrate; and the like.
  • TFT having an oxide layer formed under the oxygen partial pressure (the ratio of oxygen in an atmosphere gas) made constant to about 7% in the sputtering has a high negative value of threshold voltage when the composition thereof has a high In content, thereby making it impossible to obtain satisfactory TFT characteristics.
  • the film-formation rate in the sputtering (the value obtained by dividing the thickness of an oxide formed by the film-formation time, which may hereinafter be referred to as “sputtering rate”) may preferably be increased as much as possible to shorten the film-formation time as much as possible.
  • the sputtering rate may vary depending on the film-formation conditions, but in general, the sputtering rate has a tendency to decrease with an increase in the oxygen partial pressure in the sputtering.
  • an IZTO-based semiconductor layer which fulfils all of the three characteristics required, i.e., (a) excellent TFT switching characteristics (which may hereinafter be abbreviated as TFT characteristics), (b) high sputtering rate in the sputtering, and (c) no occurrence of residue in the wet etching.
  • the present invention has been made in view of the above situation. It is an object of the present invention to provide an oxide thin film for semiconductor layers of thin-film transistors, which can provide TFTs with excellent switching characteristics (TFT characteristics), and which has high sputtering rate in the sputtering and causes no occurrence of residue in the wet etching, and a semiconductor layer; a thin-film transistor having the oxide thin film, and a display device; and a sputtering target to be used for the formation of the oxide thin film.
  • TFT characteristics switching characteristics
  • the oxide for semiconductor layers of thin-film transistors which can solve the above problems, is an In—Zn—Sn-based oxide to be used for a semiconductor layer of a thin-film transistor, comprising In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills,
  • the In—Zn—Sn-based oxide described above is an oxide formed by a sputtering method under the control of oxygen partial pressure to 18% or lower.
  • the In—Zn—Sn-based oxide described above has a thickness of 30 to 200 nm.
  • the semiconductor layer of thin-film transistors which can solve the above problems, is a semiconductor layer of a thin-film transistor having any oxide as set forth above, wherein the semiconductor layer has an electronic carrier concentration in a range of 10 15 to 10 18 cm ⁇ 3 .
  • the semiconductor layer described above is obtained by heating treatment of any In—Zn—Sn-based oxide as set forth above at 250° C. to 350° C. for 15 to 120 minutes.
  • the present invention further includes a thin-film transistor comprising an In—Zn—Sn-based oxide as set forth above for a semiconductor layer of the thin-film transistor.
  • the present invention further includes a display device having a thin-film transistor as set forth above.
  • the In—Zn—Sn-based oxide sputtering target of the present invention which can solve the above problems, is an In—Zn—Sn-based oxide sputtering target comprising In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide sputtering target are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide sputtering target fulfills,
  • the use of the oxide of the present invention makes it possible to provide a thin-film transistor having excellent TFT characteristics, having high sputtering rate in the sputtering, and causing no occurrence of residue in the wet etching, and further provide a display device having the thin-film transistor.
  • FIG. 1 is a schematic cross-sectional view for describing a thin-film transistor having an oxide semiconductor.
  • FIG. 2 is a graph showing the regions fulfilling the ranges of the expressions defined in the present invention.
  • the region marked with rising diagonal lines from bottom left to top right indicates the range of the present invention when the In ratio is not higher than 0.5 [the range of fulfilling the expressions (2) and (4)].
  • the region marked with falling diagonal lines from top left to bottom right indicates the range of the present invention when the In ratio is higher than 0.5 [the range of fulfilling the expressions (1), (3), and (4)].
  • FIG. 3 is a graph showing the relationship between the oxygen partial pressure ratio and the sputtering rate ratio (SR) (when the Zn ratio is 0.5).
  • FIG. 4A is a view showing the results of TFT characteristics for No. 2 in Example 1.
  • FIG. 4B is a view showing the results of TFT characteristics for No. 7 in Example 1.
  • FIG. 4C is a view showing the results of TFT characteristics for No. 10 in Example 1.
  • FIG. 4D is a view showing the results of TFT characteristics for No. 5B in Example 1.
  • FIG. 5A is a view showing the results of TFT characteristics for No. 13A in Example 1.
  • FIG. 5B is a view showing the results of TFT characteristics for No. 13B in Example 1.
  • FIG. 5C is a view showing the results of TFT characteristics for No. 13C in Example 1.
  • FIG. 6 is a top view of a sample for evaluation, in Example 2, of electronic carrier concentration in an oxide semiconductor layer.
  • FIG. 7 is a schematic cross-sectional view of a thin-film transistor having an oxide semiconductor, which transistor was used in Example 2.
  • the present inventors have repeated various studies to provide an In—Zn—Sn-based oxide at least containing Zn, Sn, and In (which oxide may hereinafter be represented by “IZTO”) that, when used in active layers (or semiconductor layers) of TFTs, (i) can provide the TFTs with high switching characteristics (TFT characteristics), (ii) may have high sputtering rate in the sputtering, and (iii) may cause no occurrence of residue in the wet etching.
  • IZTO In—Zn—Sn-based oxide at least containing Zn, Sn, and In
  • the present inventors have found that In—Zn—Sn-based oxides fulfilling the following expressions can achieve the desired object, thereby completing the present invention, i.e., the In—Zn—Sn-based oxides fulfilling, when the respective contents (atomic %) of metal elements contained in each of the In—Zn—Sn-based oxides are expressed by [Zn], [Sn], and [In],
  • [Zn]/([In]+[Zn]+[Sn]) as the left part of (3) above may be referred to as the “Zn ratio in all metal elements” for convenience of description.
  • FIG. 2 shows the regions fulfilling the above expressions (1), (2), (3), and (4).
  • the portions marked with diagonal lines in FIG. 2 are the regions fulfilling all the requirements defined in the present invention. More specifically, the type of diagonal lines is changed above and below the boundary line corresponding to the In ratio of 0.5 (see FIG. 2 ).
  • the region marked with diagonal lines on or below the boundary line is the region fulfilling the requirements of the present invention in the case (a) above [i.e., the region fulfilling the expressions (2) and (4)].
  • the region marked with diagonal lines above the boundary line is the region fulfilling the requirements of the present invention in the case (b) above [i.e., the region fulfilling the expressions (1), (3), and (4)].
  • FIG. 1 shows the regions fulfilling the above expressions (1), (2), (3), and (4).
  • open circles are plots of the results of Examples fulfilling the requirements of the present invention in the case (a) above among the Examples described below, and cross marks are plots of the results of Comparative Examples not fulfilling the requirements of the present invention in the case (a) above.
  • filled circles are plots of the results of Examples fulfilling the requirements of the present invention in the case (b) above among the Examples described below, and filled triangles are plots of the results of Comparative Examples not fulfilling the requirements of the present invention in the case (b) above. It is understood that all the Examples fulfilling the requirements of the present invention are included in the ranges of the above portions marked with diagonal lines.
  • the expression (3) is an expression relating to the prevention of residue occurrence in the wet etching
  • the expressions (1) and (2) are expressions relating to the compatibility between high sputtering rate and satisfactory TFT characteristics (switching characteristics). Regarding the latter characteristics (compatibility between high sputtering rate and satisfactory TFT characteristics), the present invention adopts, depending on the In ratio represented by [In]/([In]+[Sn]), the expression (2) as an index when the In ratio is not higher than 0.5 as in the case (a) above, or the expression (1) as an index when the In ratio is higher than 0.5 as in the case (b) above.
  • These expressions (1) and (2) have been derived as the result of arrangement based on many basic experiments made by present inventors.
  • the above expression (4) defines the lower limit of the In ratio in all metal elements ([In]/([In]+[Zn]+[Sn])), and its lower limit was determined as 0.1 or higher, in both cases (a) and (b) above, for ensuring high mobility.
  • the expression (3) is not defined in the case (a) where the In ratio is not higher than 0.5. This is because even if the expression (3) is not defined, the region fulfilling the expressions (2) and (4) includes the region of the expression (3) (see FIG. 2 ). Therefore, the region fulfilling the expressions (2) and (4) not only can achieve the compatibility between high sputtering rate and satisfactory TFT characteristics but also is also the region exhibiting the effect of preventing residue occurrence in the wet etching [the region fulfilling the expression (3)].
  • IZTO in view of switching characteristics as the conditions precedent when used as TFTs, IZTO easily becomes conductive (does not switching) due to carrier increase in the high In- or Sn-content region, and it was found that In has strong action in the high In-content region. Therefore, it was found that for making IZTO have both high sputtering rate and satisfactory TFT characteristics, it is effective to properly control the In ratio in all metal elements depending on the In ratio represented by [In]/([In]+[Sn]).
  • the wording “have high sputtering rate” means the case where the sputtering rate ratio (SR) represented by SR1/SR2 is 1.0 or higher.
  • SR1 In—Zn—Sn indicates the sputtering rate (nm/min) when an In—Zn—Sn-based oxide film is formed at an oxygen partial pressure of 4% in the sputtering using an In—Zn—Sn-based sputtering target.
  • SR2 In—Ga—Zn indicates the sputtering rate (nm/min) when an In—Ga—Zn-based oxide film (the atomic ratio of In, Ga, and Zn is 1:1:1) is formed, for comparison, with the same sputtering apparatus as used in the calculation of the SR1 (In—Zn—Sn) at the same oxygen partial pressure of 4% in the sputtering using an In—Ga—Zn oxide sputtering target (the atomic ratio of In, Ga, and Zn is 1:1:1).
  • satisfying TFT characteristics means that TFTs having Vth (absolute value) of 17.5 V or lower were evaluated as having excellent TFT characteristics when the voltage at a drain current of around 1 nA between On-current and Off-current is defined as threshold voltage and each TFT is measured for threshold voltage.
  • the above expression (3) is an expression relating to the prevention of residue occurrence in the wet etching.
  • the occurrence of residue mainly involves Zn, and an increase of Zn content in an oxide film causes the occurrence of residue in the wet etching.
  • an IZTO film is etched using oxalic acid that has widely been used as a wet etchant, the occurrence of residue is caused by deposition of poorly-soluble zinc oxalate crystals.
  • the present inventors have made various studies on the requirements for preventing the occurrence of residue in the wet etching.
  • the present inventors have established the above expression (3) in a relationship with the Zn ratio.
  • IZTO having no occurrence of residue by observation after etching was evaluated as having excellent wet etching properties.
  • the Zn ratio in all metal elements is better when it is as small as possible, and for example, it may preferably be 0.8 or lower, more preferably 0.7 or lower.
  • the lower limit of the Zn ratio in all metal elements is not particularly limited form the viewpoint of wet etching properties, but in view of the fact that low etching rates need more time for patterning, the Zn ratio in all metal elements may preferably be 0.40 or higher, more preferably 0.45 or higher.
  • the above oxide is formed into a film by a sputtering method using a sputtering target (which may hereinafter be referred to as a “target”).
  • a sputtering target which may hereinafter be referred to as a “target”.
  • the oxide can also be formed by a chemical film formation method such as a coating method, but the use of a sputtering method makes it easy to form a thin film excellent in film in-plane uniformity of components and film thickness.
  • a target to be used in the sputtering method there may preferably be used a target containing the elements described above and having the same composition as that of a desired oxide, thereby making it possible to form a thin film having a desired component composition without a possibility of a composition gap. More specifically, when the respective contents (atomic %) of metal elements contained in the sputtering target, which are expressed by [Zn], [Sn] and [In], the sputtering target fulfills,
  • film formation may be carried out by a co-sputtering method for simultaneously discharging two targets with different compositions and consequently, a film with a desired composition can be obtained by co-sputtering targets such as In2O 3 , ZnO, and SnO 2 , or a target of their mixture.
  • co-sputtering targets such as In2O 3 , ZnO, and SnO 2 , or a target of their mixture.
  • the above targets can be produced by, for example, a powder sintering process method.
  • the amount of added oxygen to the total atmospheric gas (oxygen partial pressure) is properly controlled in the sputtering.
  • the substrate temperature may be room temperature in the sputtering, or the substrate may be in a heated state in the sputtering.
  • threshold voltage shows a positive shift in the high oxygen partial pressure region, but contrarily, sputtering rate becomes decreased.
  • the oxygen partial pressure in the sputtering may properly be controlled, more specifically, depending on the sputtering apparatus constitution, target composition, or other factors, but may preferably be controlled approximately to 18% or lower, more preferably 15% to lower.
  • the atmospheric gas in the sputtering may include, in addition to oxygen, inert gases such as Ar, Kr, and Xe.
  • the oxygen partial pressure in the present invention means the ratio of oxygen to these total gases.
  • the film thickness of the oxide formed into a film as described above is in a range from 30 nm to 200 nm. In an oxide semiconductor layer having an oxide film thickness beyond the above upper limit, it was found that a desired electronic carrier concentration cannot be obtained to ensure satisfactory TFT characteristics (see Examples described below). On the other hand, when the oxide film thickness is below the above lower limit, the control of film thickness in the film formation becomes difficult.
  • the above film thickness may preferably be in a range from 35 nm to 80 nm.
  • the present invention further includes semiconductor layers of TFTs having the above oxide, and TFTs having these semiconductor layers.
  • TFTs each may at least have a gate electrode, a gate insulator layer, a semiconductor layer of the above oxide, a source electrode, and a drain electrode on a substrate, and their constitution is not particularly limited as long as it is ordinarily used.
  • the semiconductor layer has an electronic carrier concentration of 10 15 to 10 18 cm ⁇ 3 .
  • the electronic carrier concentration of the semiconductor layer is one of the factors determining the TFT switching characteristics. In general, when semiconductor layers have too high electronic carrier concentrations, TFTs having such semiconductor layers become conductive and therefore become not switching. On the other hand, when semiconductor layers have too low electronic carrier concentrations, TFTs having such semiconductor layers have increased insulation properties and therefore have increased resistance. Even if TFTs make switching, TFTs having highly-resistant films cause a problem of On-current increase. Thus, TFT characteristics may greatly vary with electronic carrier concentrations. In the present invention, it was confirmed that electronic carrier concentrations are controlled in a proper range of 10 15 to 10 18 cm ⁇ 3 and therefore TFTs have satisfactory TFT characteristics (in Examples described below, threshold voltage Vth was evaluated).
  • the semiconductor layer of the present invention which has an electronic carrier concentration as described above, can be obtained by heating treatment of an oxide as described above at 250° C. to 350° C. for 15 to 120 minutes (the details will be described below).
  • FIG. 1 shows a TFT with a structure of the bottom gate type structure; however, TFTs are not limited thereto, and TFTs may be those of the top gate type, each having a gate insulator layer and a gate electrode successively on an oxide semiconductor layer.
  • a gate electrode 2 and a gate insulator layer 3 are formed on a substrate 1 , and an oxide semiconductor layer 4 is formed further thereon.
  • a source-drain electrode 5 is formed on the oxide semiconductor layer 4 , and a passivation layer (insulator layer) 6 is formed further thereon, and a transparent conductive film 8 is electrically connected to the drain electrode 5 through a contact hole 7 .
  • a method for forming the gate electrode 2 and the gate insulator layer 3 on the substrate 1 is not particularly limited, and usually used methods can be adopted.
  • the kinds of the gate electrode 2 and the gate insulator layer 3 are also not particularly limited, and widely used ones can be used.
  • metals such as Al and Cu with low electric resistance and their alloys can preferably be used for the gate electrode.
  • Typical examples of the gate insulator layer may include silicon oxide films, silicon nitride films, and silicon oxynitride films.
  • metal oxides such as TiO 2 , Al 2 O 3 and Y 2 O 3 and those formed by layering them can also be used.
  • the oxide semiconductor layer 4 is formed.
  • the oxide semiconductor layer 4 may preferably be formed into a film by, as described above, a DC sputtering method or an RF sputtering method using a sputtering target with the same composition as that of the thin film.
  • the film formation may be carried out by a co-sputtering method.
  • the oxide semiconductor layer 4 is subjected to wet etching and then patterning.
  • heat treatment for improving the film quality of the oxide semiconductor layer 4 is carried out, for example, at a temperature of about 250° C. o 350° C. for a time of about 15 to 120 minutes. This results in an increase of On-current and electric field effect mobility as the transistor characteristics, and an improvement of transistor performance.
  • Preferred pre-annealing conditions are a temperature in a range from about 300° C. to 350° C. and a time in a range from about 60 to 120 minutes.
  • the source-drain electrode 5 is formed.
  • the kind of the source-drain electrode 5 is not particularly limited, and widely used ones can be used.
  • metals such as Al and Cu or their alloys may be used, or pure Ti may be used as in Examples described below.
  • laminated structures of metals, or the like, can also be used.
  • a method for forming the source-drain electrode 5 may be carried out by, for example, forming a metal thin film by a magnetron sputtering method and forming the metal thin film into the source-drain electrode 5 by a lift-off method.
  • a method for forming the source-drain electrode 5 by previously forming a prescribed metal thin film by a sputtering method and thereafter forming the electrode by patterning, not forming the electrode by the lift-off method as described above; however, this method deteriorates the transistor characteristics since the oxide semiconductor layer is damaged at the time of etching of the electrode. Therefore, in order to avoid such problems, a method including previously forming a passivation layer on the oxide semiconductor layer, and subsequently forming the electrode by patterning, is adopted, and this method is used in Examples described below.
  • the passivation layer (insulator layer) 6 is formed on the oxide semiconductor layer 4 by a CVD (Chemical Vapor Deposition) method.
  • the surface of the oxide semiconductor layer is converted easily to be conductive by plasma-induced damage due to CVD (it is supposedly attributed to that oxygen deficiency formed on the surface of the oxide semiconductor becomes an electron donor), and in order to avoid the problems, N 2 O plasma irradiation is carried out before film formation of the passivation layer in Examples described below.
  • the condition described in the following document is adopted as the N 2 O plasma irradiation condition.
  • the transparent conductive film 8 is electrically connected to the drain electrode 5 through the contact hole 7 .
  • the kinds of the transparent conductive film and drain electrode are not particularly limited, and usually used ones can be used.
  • As the drain electrode materials exemplified for the above source-drain electrodes can be used.
  • TFTs thin-film transistors
  • a Mo thin film of 100 nm in thickness was formed as a gate electrode on a glass substrate (EAGLE 2000 available from Corning Incorporated, having a size of 100 mm in diameter and 0.7 mm in thickness), followed by photolithography and wet etching for patterning, on which a gate insulator layer SiO 2 (250 nm) was formed.
  • the gate electrode was formed by using a pure Mo sputtering target by a DC sputtering method under the following conditions: film formation temperature, room temperature; film formation power, 300 W; carrier gas, Ar, and gas pressure, 2 mTorr.
  • the gate insulator layer was formed by a plasma CVD method under the following conditions: carrier gas, mixed gas of SiH 4 and N 2 ; film formation power, 100 W; and film formation temperature, 300° C.
  • IZTO thin films having various compositions as shown in Tables 1 and 2 (the same Nos. shown in Tables 1 and 2 are corresponding to each other, and have the same composition as each other) were formed by a sputtering method, using IZTO sputtering targets, which have compositions corresponding to those shown in the tables above, and varying the oxygen partial pressure as shown in Table 2.
  • Nos. with the letter “A”, “B”, or “C” close behind indicate the cases where the composition of IZTO is substantially the same but the oxygen particle pressure in the thin film formation is different.
  • the letter “A” means film formation at an oxygen partial pressure of 4%
  • the letter “B” means film formation at an oxygen partial pressure of 10%
  • the letter “C” means film formation at an oxygen partial pressure of 50%.
  • Nos. 5A and 5B have the same [In] and substantially the same [Zn] and [Sn], but film formation was carried out at an oxygen partial pressure of 4% in No. 5A or at an oxygen partial pressure of 10% in No. 5B. Therefore, the IZTO thin films obtained, even if they have the same composition, are different in characteristics such as sputtering rate ratio and Vth.
  • the sputtering rate (nm/min) of each of various IZTO thin films shown in Table 2 was calculated by dividing the film thickness by the film formation time when film formation was carried out under the following sputtering conditions. This sputtering rate was designated by SR1 (In—Zn—Sn).
  • Substrate temperature room temperature
  • the sputtering rate (nm/min) of an IGZO thin film was calculated. More specifically, the IGZO thin film was formed under the same sputtering conditions as in the above IZTO thin films, except using an In—Ga—Zn sputtering target, which comprises In, Ga, and Zn [where the contents (atomic %) of In, Ga, and Zn in the sputtering target fulfill the relationship of 1:1:1], and except setting the oxygen partial pressure to 4% (constant). The thickness of the IGZO thin film thus obtained was divided by the film formation time to calculate the sputtering rate. The contents (atomic %) of In, Ga, and Zn in the IGZO thin film obtained in such a manner also fulfill the relationship of 1:1:1. This sputtering rate was designated by SR2 (In—Ga—Zn).
  • ITO-07N available from KANTO CHEMICAL CO., INC. (a mixed solution of oxalic acid and water) was used, and solution temperature was set to 40° C. After the wet etching, the presence of reside occurrence was confirmed by visual observation and optical microscopic observation (50-times magnification power). The results are shown in Table 2.
  • pre-annealing treatment was carried out in air at 350° C. for 1 hour under steam atmosphere for improvement of film quality.
  • a source-drain electrode was formed by a lift-off method using pure Mo. More specifically, after patterning was carried out using a photoresist, a Mo thin film was formed by a DC sputtering method (the film thickness was 100 nm). A method for forming the Mo thin film for a source-drain electrode is the same as that in the case of the gate electrode described above. Then, an unnecessary photoresist was removed by dipping in acetone with an ultrasonic washing apparatus to provide TFTs with a channel length of 10 ⁇ m and a channel width of 200 ⁇ m.
  • a passivation layer was formed to protect each oxide semiconductor layer.
  • a layered film (364 nm in total film thickness) of SiO 2 (114 nm in film thickness) and SiN (250 nm in film thickness) was used.
  • the above SiO 2 and SiN were formed by a plasma CVD method using “PD-220NL” available from SAMCO Inc.
  • N 2 O gas after plasma treatment was carried out by N 2 O gas, the SiO 2 film and the SiN film were successively formed.
  • a mixed gas of N 2 O and SiH 4 was used for the formation of the SiO 2 film, and a mixed gas of SiH 4 , N 2 , and NH 3 was used for the formation of the SiN film.
  • the film formation power was set to 100 W and the film formation temperature was set to 150° C.
  • an ITO film 80 nm in film thickness
  • carrier gas a mixed gas of argon and oxygen gas
  • film formation power 200 W
  • gas pressure 5 mTorr
  • the TFTs thus obtained were each evaluated for the following characteristics.
  • the transistor characteristics were measured using a semiconductor parameter analyzer (“4156C” available from Agilent Technologies). The detailed measurement conditions were as follows:
  • Gate voltage ⁇ 30 to 30V (measurement interval: 0.25V).
  • the threshold voltage is roughly a value of gate voltage at the time when a transistor is shifted from OFF state (i.e., state where drain current is low) to ON state (i.e., state where drain current is high).
  • the voltage in the case where the drain current is around 1 nA between ON-current and OFF-current is defined as the threshold voltage, and the threshold voltage of each TFT was measured.
  • TFTs having a Vth (absolute value) of 17.5 V or lower were evaluated as passing. The results are shown in Table 2.
  • the symbol “-” in Table 2 means TFTs that did not switching (became conductive) in the range of voltage for evaluation (from ⁇ 30 V to 30V).
  • FIGS. 4A No. 2
  • 4 B No. 7
  • 4 C No. 10
  • 4 D No. 5B
  • FIGS. 5A No. 13A
  • 5 B No. 13B
  • 5 C No. 13C
  • Id (A) and Vg (V) were plotted along the longitude axis and the abscissa axis, respectively. The measurement was carried out two times, both of which results are therefore shown in these figures.
  • TFTs fulfilling the requirements of the present invention exhibited an increase in gate voltage Vg by about 8 digits with a variation of gate voltage Vg from ⁇ 30 V to 30V before the formation of the passivation layer, and therefore, these TFTs obtained satisfactory switching characteristics as shown in FIGS. 4A to 4D .
  • the carrier mobility (electron field-effect mobility) was calculated in a saturation region according to the following expression.
  • V th threshold voltage
  • TFTs fulfilling the expression of [In]/([In]+[Sn]) ⁇ 0.5 were designated by (a) and TFTs fulfilling the expression of [In]/([In]+[Sn])>0.5 were designated by (b).
  • TFTs fulfilling the expressions (2) and (4) are examples of the present invention.
  • TFTs fulfilling the expressions (1), (3), and (4) are examples of the present invention.
  • all the examples fulfill the relationship of the expression (4).
  • TFTs fulfilling the relationship of the expression (2) were designated by the mark “o” on the column “Relationship of expression (2)”, and TFTs not fulfilling the relationship of the expression (2) were designated by the mark “x” on the column “Relationship of expression (2)”.
  • TFTs fulfilling the relationship of the expression (1) were designated by the mark “o” on the column “Relationship of expression (1)”, and TFTs not fulfilling the relationship of the expression (1) were designated by the mark “x” on the column “Relationship of expression (1)”; furthermore, TFTs fulfilling the relationship of the expression (3) were designated by the mark “o” on the column “Relationship of expression (3)”, and TFTs not fulfilling the relationship of the expression (3) were designated by the mark “x” on the column “Relationship of expression (3)”.
  • the examples of (a) above are not needed to fulfill the relationship of the expression (3), but for reference, the above judgment results were shown on the column “Relationship of expression (3)”. In this Example, all the examples of (a) above fulfill the relationship of the expression (3) (evaluated as “o”).
  • TFTs fulfilling the passing criteria of this Example were designated by the mark “o”
  • TFTs not fulfilling the passion criteria of this Examples were designated by the mark “x”.
  • TFTs having a Vth (absolute value) of not lower than 17.5 V and an SR of not lower than 1.0 were designated by the mark “o”
  • TFTs not fulfilling either of these requirements were designated by the mark “x”.
  • TFTs having no occurrence of residue were designated by the mark “o”
  • TFTs having occurrence of residue were designated by the mark “x”.
  • Nos. 1, 4, 6A, 6B, 8A, 8B, 9A, and 9B had high sputtering rate ratios because of their fulfilling the relationship of the expression (3) and had no occurrence of residue in the wet etching, but had high absolute values of threshold voltage because of their not fulfilling the relationship of the expression (2), resulting in deterioration of TFT characteristics.
  • Nos. 13A to 13C had high sputtering rate ratios and no occurrence of residue in the wet etching because of their fulfilling the relationship of the expression (3), but had high absolute values of threshold voltage, resulting in deterioration of TFT characteristics, because of their not fulfilling the relationship of the expression (1).
  • TFTs not fulfilling the relationship of the expression (3) had occurrence of residue in the wet etching.
  • the absence of residue in the wet etching was examined, and it was found that the TFT had occurrence of residue because of its not fulfilling the expression (3).
  • the respective combinations of TFTs Nos. 5A and 5B; Nos. 6A and 6B; Nos. 8A and 8B; Nos. 9A and 9B; and Nos. 13A, 13B, and 13C, are examples of TFTs obtained by film formation using approximately the same composition of IZTO and varying the oxygen partial pressure ratio in the sputtering, and there was found a tendency of sputtering rate ratio to become lowered, regardless of the composition of IZTO, with an increase in oxygen partial pressure ratio (in the order of A, B, and C).
  • FIG. 3 is a graph showing the influence of oxygen partial pressure to sputtering rate in the sputtering. More specifically, FIG. 3 shows the results obtained by examining sputtering rate ratio in the same manner as in the method described above, except that TFTs having the compositions of Nos. 1, 4, and 9 in Tables 1 and 2 were used and oxygen partial pressure was varied in a range of 3% to 50% as shown in Table 3. For reference, the results of sputtering rate are also shown in Table 3. In FIG. 3 , oxygen partial pressure is shown by flow rate ratio, not % designation.
  • sputtering rate has almost no variation in the region of low oxygen partial pressure where the upper limit of oxygen partial pressure is near approximately 18%, but sputtering rate drastically decreases from somewhere around higher than about 18% oxygen partial pressure. This therefore finds that oxygen partial pressure in the film formation may preferably be lowered to not higher than about 18% to ensure high sputtering rate as desired.
  • the use of In—Zn—Sn-based oxide semiconductors having the compositions of Nos. 2, 3, 5, 7, and 10 to 12 in Table 2, which fulfill all the requirements defined in the present invention provide TFTs with high threshold voltage, excellent etching characteristics in the wet etching, high sputtering rate in the sputtering, high mobility two times higher than that of the conventional IGZO (having a mobility of 7), and satisfactory TFT characteristics. Therefore, the present invention makes it possible to provide oxide semiconductors capable of providing TFTs with satisfactory TFT characteristics, having high production efficiency and excellent patterning properties in the wet etching, and further having satisfactory yield.
  • Nos. 13A to 13C in Table 2 [the examples of (b) above where the In ratio>0.5] corresponds to a simulated IZTO having a composition as described in Patent Document 2 listed above, for which experiment was carried out with varying oxygen partial pressure.
  • the IZTO having the above composition it is found that TFT characteristics cannot be improved when oxygen partial pressure is not increased as shown in FIGS. 5A to 5C . More specifically, switching is not effected at an oxygen partial pressure of 4%, and Vth becomes equal to ⁇ 28.5 V at an oxygen partial pressure of 10% and ⁇ 23 V at an oxygen partial pressure of 50%, and it is further found that Vth approaches zero with an increase in oxygen partial pressure to improve TFT characteristics.
  • the above IZTO is one of the examples of (b) above, and examined for the relationship of the expression (1) defined in the present invention. As a result, the above IZTO was found not to fulfill the relationship of the above expression (1) as shown in Table 2, and therefore, it was confirmed that the above expression (1) defined in the present invention is a requirement useful for making compatibility between satisfactory TFT characteristics and high sputtering rate.
  • Example 2 various samples were produced with varying sputtering times when oxide films are formed by a sputtering method and further varying per-annealing conditions after the oxide film formation (A1 to A7 in Table 4), and each of the samples was examined for relationship between electronic carrier concentration in each oxide semiconductor layer and TFT characteristics (threshold voltage Vth).
  • the IZTO thin film of No. 7 in Table 1 above (which thin film fulfills the composition of the present invention) was used to produce an evaluation sample as shown in FIG. 6 , followed by measurement of electronic carrier concentration.
  • TFTs as shown in FIG. 1 were produced with the same film thickness and conditions as in the case of the evaluation sample, and then each TFT was measured for threshold voltage Vth in the same manner as described in Example 1.
  • pre-annealing treatment was carried out in air under steam atmosphere for improvement of film quality.
  • the heat treatment temperatures and times for the respective samples at this time were as follows.
  • pre-annealing treatment was not carried out in A3 below.
  • an electrode film was formed by a sputtering method using pure Au.
  • An apparatus used for the sputtering was “CS-200” available from available from ULVAC, Inc., and the electrode film was patterned by musk sputtering.
  • the formation of a pure Au electrode in such a manner was followed by division to obtain samples for measurement of Hall effects (samples for evaluation of electronic carrier concentrations in the oxide semiconductor layers) as shown in FIG. 6 .
  • TFTs as shown in FIG. 7 were produced with the same film thicknesses and heat treatment conditions as the samples for measurement of Hall effects in FIG. 6 above, and then evaluated for threshold voltage Vth in the same manner as described in Example 1.
  • TFTs as shown in FIG. 7 and TFTs as shown in FIG. 1 which were used in Example 1, are different only in that a surface passivation layer is formed on the oxide semiconductor layer in FIG. 7 (no surface passivation layer is formed on the oxide semiconductor layer 4 in FIG. 1 ).
  • Oxide semiconductor layers are easily damaged by, for example, heating treatment in the film formation, and therefore, surface passivation layers are usually formed from SiO 2 or other materials.
  • an Mo thin film of 100 nm in thickness and a gate insulator layer of SiO 2 (250 nm) were formed successively on a glass substrate (EAGLE 2000 available from Corning Incorporated, having a size of 100 mm in diameter and 0.7 mm in thickness) in the same manner as described above in Example 1.
  • a surface passivation layer (SiO 2 , 100 nm in film thickness) was formed in such a manner as described below.
  • the above SiO 2 film was formed by a plasma CVD method using “PD-220NL” available from SAMCO Inc.
  • PD-220NL available from SAMCO Inc.
  • a mixed gas of N 2 O and SiH 4 was used, and film formation power and temperature were set to 100 W and 200° C., respectively.
  • the surface passivation layer thus formed was patterned by photolithography and dry etching for electrode formation to make contact between the semiconductor layer and the source-drain electrode described below.
  • a pure Mo source-drain electrode was formed in the same manner as described above in Example 1, after which the channel length and width of each TFT were set to 10 ⁇ m and 25 ⁇ m, respectively, and a passivation layer [a layered film (364 nm in total film thickness) of SiO 2 (114 nm in film thickness) and SiN (250 nm in film thickness)] for protection of the oxide semiconductors layer was formed. After that, a contact hole for probing for evaluation of transistor characteristics and an ITO film were formed in the same manner as described above in Example 1 to produce TFTs as shown in FIG. 7 .
  • Table 4 is provided with a judgment column, on which column TFTs fulfilling the range (10 15 to 10 18 cm ⁇ 3 ) of electric carrier concentration in the oxide semiconductor layer are designated by the mark “o” and TFTs not fulfilling such a range are designated by the mark “x”.
  • threshold voltage Vth may vary with electric carrier concentration, and all Nos. A2 and A4 to A7, of which electronic carrier concentrations fulfill the requirements of the present inventions (judgment of electronic carrier concentration was “o”), had Vth (absolute values) of not higher than 17.5 V to fulfill the passing criteria of the present inventions.
  • TFTs of which electronic carrier concentrations fulfill the requirements of the present invention, had small absolute values of Vth and therefore had excellent TFT characteristics.

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