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US20120313234A1 - Qfn package and manufacturing process thereof - Google Patents

Qfn package and manufacturing process thereof Download PDF

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Publication number
US20120313234A1
US20120313234A1 US13/158,124 US201113158124A US2012313234A1 US 20120313234 A1 US20120313234 A1 US 20120313234A1 US 201113158124 A US201113158124 A US 201113158124A US 2012313234 A1 US2012313234 A1 US 2012313234A1
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US
United States
Prior art keywords
conductive layer
lead frame
leads
chip
qfn package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/158,124
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English (en)
Inventor
Geng-Shin Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US13/158,124 priority Critical patent/US20120313234A1/en
Assigned to CHIPMOS TECHNOLOGIES INC. reassignment CHIPMOS TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHEN, GENG-SHIN
Priority to TW101118113A priority patent/TWI550741B/zh
Priority to CN201210186496.7A priority patent/CN102820276B/zh
Publication of US20120313234A1 publication Critical patent/US20120313234A1/en
Priority to US13/918,518 priority patent/US8962395B2/en
Abandoned legal-status Critical Current

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    • H10W72/012—
    • H10W70/427—
    • H10W70/479—
    • H10W74/01—
    • H10W74/014—
    • H10W74/111—
    • H10W70/415—
    • H10W72/01271—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/221—
    • H10W72/222—
    • H10W72/223—
    • H10W72/242—
    • H10W72/245—
    • H10W72/252—
    • H10W72/255—
    • H10W72/29—
    • H10W72/9415—
    • H10W72/942—
    • H10W72/952—
    • H10W74/00—
    • H10W90/726—

Definitions

  • the present invention relates to a QFN package and manufacturing process thereof, and more particularly, to a QFN package with composite bumps.
  • Packaging processes have been widely used to electrically connect a semiconductor chip to an external component with a better reliability and also to protect the semiconductor chip from damages caused by external conditions.
  • packaging materials and the packaging processes used are not only associated with the manufacturing cost, but also have an influence on operational performance of the packaged chip. For this reason, the packaging structure and materials thereof selected for use become very important.
  • Quad Flat No-Leaded (QFN) semiconductor packages have achieved wide popularity in recent years because of their smaller package size.
  • a chip is electrically connected to a lead frame by wire, with each bond pad of the chip being electrically connected to a corresponding lead of the lead frame respectively.
  • a flip chip QFN package 10 a chip 101 is electrically connected to a lead frame 103 by bumps 105 as shown in FIG. 1A or FIG. 1C .
  • the chip 101 is flipped and bonded on the lead frame 103 by solder joining of solder bump ( FIG. 1A ) or copper pillar with solder cap.
  • the lead width will be limited to enough space for avoid the melting solder over flow to the opposite side of lead during the reflow process ( FIG. 1B ). That melting solder 107 over flow on the opposite side of lead will induce assembly defect of further process, for example encapsulation, or SMT (Surface Mount Technology).
  • the lead width may not be designed with enough space to avoid the melting solder over flow.
  • the primary objective of the present invention is to provide a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant.
  • the chip has a plurality of pads
  • the lead frame has a plurality of leads.
  • a semi-cured encapsulant is formed in the spaces between the leads of the lead frame before the chip is bonded to the lead frame.
  • Each of the plurality of composite bumps has a first conductive layer and a second conductive layer.
  • the first conductive layer is electrically connected between one of the pads and the second conductive layer
  • the second conductive layer is electrically connected between the first conductive layer and one of the leads.
  • the encapsulant encapsulates the chip, the leads and the composite bumps.
  • the manufacturing process of the present invention comprises the following steps of: forming a plurality of lead frame module; forming a plurality of chip modules, each having a chip being connected with a plurality of composite bumps; bonding the lead frame modules to the chip modules by connecting the composite bumps to the leads respectively; and forming a plurality of QFN packages by encapsulating and singulating the chip modules and the lead frame modules.
  • the step of forming a plurality of lead frame modules comprises the following steps of: forming an upper unit by semi cured encapsulant onto a top carrier; forming a lower unit by disposing a matrix lead frame on a bottom carrier, wherein the matrix lead frame comprises a plurality of leads; bonding the upper unit and the lower unit by laminating the semi cured encapsulant with the matrix lead frame to have the leads be in contact with the top carrier; forming the plurality of lead frame modules by fully curing the encapsulant and removing the top carrier to make sure the top surface of lead is not lower than the encapsulant.
  • the step of bonding the lead frame modules to the chip modules may be proceeded by one of thermo-ultrasonic bonding, reflowing and applying conductive paste.
  • the present invention provides the following benefits: the QFN package and a manufacturing process thereof of the present invention replaces the conventional bumps with the composite bumps and a encapsulated matrix lead frame, so the pitch between and the height of the composite bumps of the QFN package could be controlled, and the short interconnection loop formed by the composite bumps could reduce the resistance and inductance and improve the performance of the whole QFN package.
  • FIG. 1A to FIG. 1C are schematic views of conventional flip chip QFN packages
  • FIG. 2B is a cross sectional view of another QFN package structure in accordance with a preferred embodiment of the present invention.
  • FIG. 3A to FIG. 3E are schematic views illustrating a manufacturing process of a lead frame module of a QFN package in accordance with an embodiment of the present invention.
  • FIG. 4A to FIG. 4C are schematic views illustrating a manufacturing process of a chip, electrically connected with plural composite bumps, of a QFN package in accordance with an embodiment of the present invention
  • FIG. 5A to FIG. 5B are schematic views illustrating a manufacturing process of a QFN package in accordance with an embodiment of the present invention
  • FIG. 6 is a schematic view of a matrix lead frame of the present invention.
  • FIG. 7 is a cross sectional view of a composite bump in accordance with another aspect of the preferred embodiment of the present invention.
  • FIG. 8 is a cross sectional view of a chip in accordance with another aspect of the preferred embodiment of the present invention.
  • the QFN package 1 comprises a chip 11 , a lead frame 13 , a plurality of composite bumps 15 and an encapsulant 17 .
  • the chip 11 has an active surface 113 , a plurality of pads 111 and a passivation layer.
  • the pads 111 are formed on the active surface 113 of the chip 11 . More specifically, the pads 111 are arranged at four sides of the active surface 113 , and the pads 111 may be only arranged at two parallel sides of the active surface 113 in other aspects. Each of the pads 111 is partially covered by the passivation layer 115 , and some portion of each of the pads 111 is exposed for electrical connection thereby.
  • the chip 11 may be, for example, a display driver circuit IC, an image sensor IC, a memory IC, a logic IC, an analog IC, an ultra-high frequency (UHF) or a radio frequency (RF) IC, but it is not limited thereto.
  • a display driver circuit IC an image sensor IC
  • a memory IC a memory IC
  • a logic IC an analog IC
  • UHF ultra-high frequency
  • RF radio frequency
  • the lead frame 13 has a plurality of leads 131 , which are arranged at four sides to form a square in this embodiment (not shown).
  • Each lead 131 has an inner lead portion 131 a and an outer lead portion 131 b .
  • Each of the inner lead portions 131 a and each of the outer lead portions 131 b have a height difference that the inner lead portions 131 a are higher than the outer lead portions 131 b as shown in FIG. 2A .
  • the composite bumps 15 are electrically connected between the chip 11 and the lead frame 13 .
  • Each composite bump 15 has a first conductive layer 151 and a second conductive layer 153 , and the second conductive layer 153 is softer than the first conductive layer 151 .
  • the first conductive layer 151 is electrically connected between a corresponding pad 111 of the pads 111 of the chip 11 and the second conductive layer 153 .
  • the second conductive layer 153 is electrically connected between the first conductive layer 151 and a corresponding inner lead portion 131 a of the inner lead portions 131 a of the leads 131 of the lead frame 13 .
  • the composite bumps 15 electrically connect to the pads 111 of the chip 11 with the first conductive layers, and the composite bumps 15 electrically connect to the inner lead portions 131 a of the leads 131 of the lead frame 13 with the second conductive layers 153 .
  • the first conductive layer 151 may be made of a material selected from a group consisting of copper, nickel, aluminum, zinc, and combinations thereof.
  • the second conductive layer 153 may be made of a material selected from a group consisting of gold, copper, silver, tin, zinc, indium, and combinations thereof.
  • the second conductive layer 153 made of gold forms a thickness which is at least less than a half of the total height of the composite bump 15 . The reduction of gold results in reducing the manufacture cost.
  • the composite bumps 15 disclosed above are only provided as an example, and as may be appreciated by those of ordinary skill in the art, the composite bumps 15 may also be “composite” bump structures formed by other existing bumps in combination (for example, the composite bumps are formed by two layers of stud bumps) to satisfy different demands for electrical connection between different kinds of flip chips and the substrate and to lower the manufacturing cost by reducing use of gold.
  • the encapsulant 17 encapsulates the chip 11 , the leads 131 and the composite bumps 15 .
  • the encapsulant 17 is formed around the chip 11 and the composite bumps 15 and covers almost the whole surface of the lead frame 13 except for the bottom surface of outer lead portion 131 b of lead 131 of lead frame 13 thereof.
  • the material of the encapsulant 17 is a material of which may be selected from thermoplastic resins such as acrylic resins, polyimide resins or polysulfone resins, or thermosetting resins such as epoxy resins, phenolic resins, tripolycyanamide resins or polyester resins, or combinations thereof.
  • the encapsulant 17 is preferably made of low coefficient of thermal expansion (CTE) and low modulus material.
  • each of the composite bumps 15 connects to the top surface of the corresponding inner lead portion 131 a of the lead 131 of the lead frame 13 by thermo-ultrasonic bonding, reflowing, or applying conductive paste therebetween.
  • the composite bumps 15 connect to the leads 131 by thermo-ultrasonic bonding.
  • the QFN package further comprises a plurality of plated structures, one of which is adhered between the second conductive layer and the lead for connecting each of the composite bumps to the corresponding inner lead portion of the lead of the lead frame by reflowing.
  • the encapsulant of such modification would not have any encapsulation interface.
  • the plated structure is solder or a copper pillar with a solder cap.
  • the QFN package further comprises a plurality of conductive paste, respectively disposed between and adhering each of the composite bumps and a corresponding lead of the leads.
  • the conductive paste may be silver paste or solder. Neither the encapsulant of such modification would have any encapsulation interface.
  • the present invention further provides a QFN package 1 ′, which adopts specific manufacturing process and would be describe in detail later, further has an encapsulation interface 19 which is not higher than a top surface of the lead frame 13 as shown in FIG. 2B .
  • the encapsulant 17 is only formed around the chip and the composite bump, fully cured encapsulant 17 ′ is formed around the leads 131 of the lead frames 13 under the encapsulant 17 , and the interface between the encapsulant 17 and the fully cured encapsulant 17 ′ is the encapsulation interface 19 .
  • FIG. 3A As shown therein, forming an upper unit 3 a by forming a semi cured encapsulant 17 ′′ onto a top carrier 41 is executed.
  • a top carrier 41 could be metal, glass, organic film, or plastic, which could provide a flat surface and appropriate strength for the semi cured encapsulant 17 ′′.
  • FIG. 3B shows that a lower unit 3 b is formed by disposing a matrix lead frame 6 (as shown in FIG. 6 ) on a bottom carrier 31 , which could be organic film, glass, plastic, or metal.
  • a matrix lead frame 6 as shown in FIG. 6
  • the matrix lead frame 6 comprises a plurality of lead frames 13 , each of the lead frames 13 comprises a plurality leads 131 , and each lead 131 has an inner lead portion 131 a and an outer lead portion 131 b .
  • Appropriate adhesion between the bottom carrier 31 and the lead frame 13 is necessary for further process. It should be noted that the executing priority of the processes illustrated in FIG. 3A and FIG. 3B are not limited.
  • FIG. 3C features that bonding the upper unit 3 a and the lower unit 3 b by laminating the semi cured encapsulant 17 ′′ with the matrix lead frame to have the leads 131 be in contact with the top carrier 41 .
  • the top carrier 41 contacts the top surface of the inner lead portions 131 a of the leads 131 . Since the semi cured encapsulant 17 ′′ is partially cured and is a semifluid substance, the leads 131 would be enclosed except for the top surface of the inner lead portions 131 a and the bottom surface of the outer lead portions 131 b.
  • a lead frame module 3 d (or 3 e shown in FIG. 3E ) on each lead frame 13 of the matrix lead frame by fully cured the semi cured encapsulant 17 ′′ to fully cured encapsulant 17 ′ and removing the top carrier 41 .
  • the top surface of the fully cured encapsulant 17 ′ may be as high as (or lower than shown in FIG. 3E ) the top surface of the inner lead portions 131 a of the leads 131 .
  • the lead frame module 3 d (or 3 e shown in FIG. 3E ) on the matrix lead frame is formed.
  • a wafer 30 is provided.
  • the wafer 30 is formed with internal circuits, an active surface 113 , a plurality of pads 111 and a passivation layer 115 .
  • the pads 111 are disposed on the active surface 113 and are partially covered by the passivation layer 115 to provide exposed areas (or named “openings”). Signals would be transmitted from or to the internal circuits through the exposed areas of the pads 111 .
  • each of the composite bumps 15 comprises a first conductive layer 151 and a second conductive layer 153 , and the first conductive layer 151 is directly connected to and disposed between a corresponding pad 111 of the pads 111 and the second conductive layer 153 .
  • the internal circuits of the wafer 30 and the composite bumps 15 are electrically connected via the exposed areas of the pads 111 .
  • the wafer 30 is saw to provide a plurality of chips 11 , each of which is electrically connected with plural composite bumps 15 .
  • other existing processes for composite bumps may also be applied in the present invention, and this will not be further described herein.
  • a plurality of lead frame module which is disposed and formed on the matrix lead frame 6 on a bottom carrier 31 , is provided according to the steps FIGS. 3A-3E .
  • the matrix lead frame 6 (as shown in FIG. 6 ) comprises a plurality of lead frames 13 , and each of the lead frames 13 has a plurality of leads 131 as depicted above. And the leads 131 of the matrix lead frame 13 are enclosed with the fully cured encapsulant 17 ′ except for the top surface of the inner lead portions 131 a and the bottom surface of the outer lead portions 131 b .
  • each of the chips 11 is electrically connected to a part of the leads 131 of the matrix lead frame by a plurality of composite bumps 15 .
  • the second conductive layer 153 of each composite bump 15 is directly connected to the top surface of the inner lead portion 131 a of the corresponding lead 131 of the lead frame 13 by thermo-ultrasonic bonding, reflowing or applying conductive paste. It is known that there would be solder between the composite bumps 15 and the inner leads 131 a , and such solder is not shown in FIG. 5A if reflow is applied.
  • the chip 11 , the lead frames 13 on the matrix lead frame and the composite bumps 15 are encapsulated.
  • the encapsulant 17 is formed around the chip 11 and the composite bumps 15 and covers almost the whole surface of the lead frame 13 except for the bottom surface of outer lead portion 131 b of lead 131 by transfer molding, screen printing, coating, or injection, etc.
  • the encapsulation interface 19 would be formed in such case, no matter whether the encapsulant 17 is the same material as the fully cured encapsulant 17 ′ or not.
  • singulating the matrix lead frame and stripping off the bottom carrier 31 to the QFN packages 1 is executed as shown in FIG. 2 .
  • the QFN package 1 comprises one of the encapsulated chips 11 and a part of the encapsulated matrix lead frame.
  • thermo-ultrasonic bonding there would be thermal stress arisen after thermo-ultrasonic boding, and the top surface of the inner lead portion 131 a would be not bent, cracked or even fractured. And no more melting solder overflows in the present invention
  • the composite bump may further comprise at least an under bump metallization (UBM) layer, or a covering third conductive layer and a barrier layer.
  • UBM under bump metallization
  • the chip 11 is electrically connected to plural composite bumps through plural pads 111 .
  • Each of the composite bumps 2 comprises an under bump metallization (UBM) layer 21 , a first conductive layer 23 , a second conductive layer 25 , a covering third conductive layer 27 and a barrier layer 29 .
  • the UBM layer 21 is disposed between the first conductive layer 23 and the pad 111 of the chip 11 .
  • the first conductive layer 23 is located on the UBM layer 21
  • the second conductive layer 25 is in turn located on the first conductive layer 23 .
  • the covering third conductive layer 27 that covers the surface each of the composite bumps 2 , which includes the second conductive layer 25 , and the first conductive layer 23 .
  • the barrier layer 29 located between the first conductive layer 23 and the second conductive layer 25 .
  • the UBM layer 21 may be made of a material selected from titanium, tungsten, copper, gold, and alloys thereof.
  • the covering third conductive layer 27 may be made of gold, but it is not limited thereto.
  • the barrier layer 29 may be made of nickel, but it is not limited thereto.
  • the step of forming the wafer 30 shown in FIG. 4A may further comprises the following steps of forming a redistribution layer (RDL) 51 on each of the pads 111 of the chips 11 for electrical connection between the first conductive layer 151 of each of the composite bumps 2 ; and forming the composite bump 15 by forming a first conductive layer 151 on each of the RDL layers 51 and forming a second conductive layer 153 on the first conductive layer 151 to re-layout the bump position as shown in FIG. 8 .
  • RDL redistribution layer
  • the pitch between and the height of the composite bumps 15 of the QFN package 1 could be controlled, and the short interconnection loop formed by the composite bumps 15 could reduce the resistance and inductance and improve the performance of the whole QFN package.
  • pre-molding the lead frame could avoid the different leveling issue of inner lead portions and protect the lead surface.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
US13/158,124 2011-06-10 2011-06-10 Qfn package and manufacturing process thereof Abandoned US20120313234A1 (en)

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US13/158,124 US20120313234A1 (en) 2011-06-10 2011-06-10 Qfn package and manufacturing process thereof
TW101118113A TWI550741B (zh) 2011-06-10 2012-05-22 四方扁平無接腳封裝及其製造方法
CN201210186496.7A CN102820276B (zh) 2011-06-10 2012-06-07 四方扁平无接脚封装及其制造方法
US13/918,518 US8962395B2 (en) 2011-06-10 2013-06-14 QFN package and manufacturing process thereof

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