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US20100181847A1 - Method for reducing supply voltage drop in digital circuit block and related layout architecture - Google Patents

Method for reducing supply voltage drop in digital circuit block and related layout architecture Download PDF

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Publication number
US20100181847A1
US20100181847A1 US12/358,215 US35821509A US2010181847A1 US 20100181847 A1 US20100181847 A1 US 20100181847A1 US 35821509 A US35821509 A US 35821509A US 2010181847 A1 US2010181847 A1 US 2010181847A1
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US
United States
Prior art keywords
conducting
supply voltage
conducting segment
segment
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/358,215
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English (en)
Inventor
Shen-Yu Huang
Chih-Ching Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US12/358,215 priority Critical patent/US20100181847A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, SHEN-YU, LIN, CHIH-CHING
Priority to TW098112643A priority patent/TWI385921B/zh
Priority to CN2009101375136A priority patent/CN101789779B/zh
Publication of US20100181847A1 publication Critical patent/US20100181847A1/en
Priority to US13/298,315 priority patent/US8640074B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H10W20/427—
    • H10W20/496—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Definitions

  • the present invention is related to supplying a supply voltage to a digital circuit, and more particularly, to a layout architecture for reducing leakage current of the supply voltage path of the supply voltage of the digital circuit and a method thereof.
  • FIG. 1 is a diagram illustrating a prior art digital circuit 10 after performing the APR process.
  • the digital circuit 10 comprises a plurality of functional digital cells 11 a ⁇ 11 d, a power rail 12 , and a ground rail 13 , in which the power rail 12 is coupled to a supply voltage VDD to supply power to each of the functional digital cells 11 a ⁇ 11 d, and the ground rail 13 provides a ground voltage GND for the functional digital cells 11 a ⁇ 11 d.
  • the APR process may generate a gap between some of the two functional digital cells, such as the gap 14 between the functional digital cells 11 b and 11 c, when optimizing the whole digital circuit 10 . If this happens, the gap 14 will be filled up by a filler capacitor 15 in order to stabilize the supply voltage VDD for the functional digital cells 11 b and 11 c.
  • the filler capacitor 15 is implemented by a CMOS (Complementary Metal Oxide Semiconductor) transistor, and the electric charge of the filler capacitor is accumulated on the gate terminal and the substrate of the CMOS transistor, the electric charge may leak from the gate terminal to the substrate of the CMOS transistor. Therefore, a significant leakage current may be induced if the digital circuit 10 includes a large number of filler capacitors. Accordingly, to reduce the leakage current problem of the digital circuit 10 is becoming one of the most urgent problems in the field of digital circuit design.
  • CMOS Complementary Metal Oxide Semiconductor
  • One of the objectives of the present invention is provide a layout architecture for reducing leakage current of the supply voltage path of a supply voltage of a digital circuit and a method thereof.
  • a method for reducing a supply voltage drop in a digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment.
  • the method comprises the following steps: constructing a third conducting segment having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer, and an dielectric layer is between the first conducting layer and a second conducting layer; and constructing a fourth conducting segment having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the second conducting layer, whereby a first capacitive element is formed between the first portion and the second portion.
  • a method for reducing a supply voltage drop in a digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the method comprising the following steps: constructing a third conducting segment having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a conducting layer; and constructing a fourth conducting segment having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the conducting layer, whereby a capacitive element is formed between the first portion and the second portion.
  • a layout architecture for reducing a supply voltage drop in a digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the layout architecture comprises a third conducting segment and a fourth conducting segment.
  • the third conducting segment has a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer, and an dielectric layer is between the first conducting layer and a second conducting layer; and the fourth conducting segment has a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the second conducting layer, whereby a first capacitive element is formed between the first portion and the second portion.
  • a layout architecture for reducing a supply voltage drop in a digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, and the layout comprises a third conducting segment and a fourth conducting segment.
  • the third conducting segment has a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a conducting layer.
  • the fourth conducting segment has a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.
  • FIG. 1 is a diagram illustrating a prior art digital circuit after performing an APR process.
  • FIG. 2 is a top view diagram illustrating a layout architecture for reducing a supply voltage drop in a digital circuit block according to an embodiment of the present invention.
  • FIG. 3 is a space diagram illustrating the layout architecture of the digital circuit block as shown in FIG. 2 .
  • FIG. 4 is a diagram illustrating a side view diagram of a Metal-dielectric-metal capacitor of the digital circuit block as shown in FIG. 2 .
  • FIG. 5 is a flowchart illustrating a method for reducing a supply voltage drop in the digital circuit block of the embodiment as shown in FIG. 2 .
  • FIG. 2 is a top view diagram illustrating a layout architecture 202 for reducing a supply voltage drop in a digital circuit block 200 according to an embodiment of the present invention, wherein the digital circuit block 200 comprises a first conducting path 2022 having a first end coupled to a first supply voltage, such as Vdd, a second conducting path 2024 having a first end coupled to a second supply voltage, such as ground voltage Vgnd, and a digital logic 2026 coupled between a second end of the first conducting path 2022 and a second end of the second conducting path 2024 .
  • FIG. 3 is a space diagram illustrating the layout architecture 202 of the digital circuit block 200 as shown in FIG. 2 .
  • the layout architecture 202 provides a capacitance block between the first conducting path 2022 and the second conducting path 2024 in order to reduce the supply voltage Vdd IR drop (e.g., dynamic voltage drop) to the digital logic 2026 .
  • the layout architecture 202 comprises conducting segments 202 a, 202 b, 202 c, 202 d, 202 e, 202 f, vias 202 g, 202 h, 202 i, 202 j, and a metal-dielectric-metal capacitor 202 k.
  • the conducting segments 202 a, 202 b have a first end electrically connected to the first conducting path 2022 and a second end not electrically connected to the second conducting path 2024
  • the conducting segments 202 c, 202 d have a first end electrically connected to the second conducting path 2024 and a second end not electrically connected to the first conducting path 2022 .
  • the conducting segment 202 e coupled to the conducting segments 202 a and 202 b through the vias 202 g and 202 i respectively, and the conducting segment 202 f coupled to the conducting segments 202 c and 202 d through the vias 202 h and 202 j respectively.
  • the metal-dielectric-metal capacitor 202 k is constructed under the region between the conducting segments 202 a and 202 c.
  • the first conducting path 2022 , the second conducting path 2024 , the conducting segments 202 a, 202 b, 202 c, 202 d are located at the same conducting layer L 6 , such as the top conducting layer (e.g., layer 6 ) of a semiconductor process; and the conducting segments 202 e, 202 f are located at the other conducting layer L 5 , such as layer 5 of the semiconductor process, as shown in FIG. 3 .
  • the layer L 6 is adjacent to the layer L 5 .
  • the two conducting layers could also not adjacent to each other.
  • the metal-dielectric-metal capacitor 202 k could be implemented between any two conducting layers.
  • a dielectric layer L IN may be between the conducting layer L 6 and the conducting layer L 5 , in which the dielectric layer L IN can be implemented by an oxide layer.
  • the layout architecture 202 is just an example of the embodiment of the digital circuit block 200 , and is not meant to be a limitation of the present invention. In other words, the number of the conducting segments, vias, and metal-dielectric-metal capacitors and the arrangement between the conducting segments, vias, and metal-dielectric-metal capacitors can be adjusted according to practical conditions, such as the area required by the layout architecture 202 , of the implementation of the digital circuit block 200 .
  • a capacitor C 1 may be formed between the overlapped region of the conducting segments 202 d and 202 e, which is an oblique line portion 202 d ′; and a capacitor C 2 may be formed between the overlapped region of the conducting segments 202 b and 202 f, which is the oblique line portion 202 b ′.
  • a capacitor C 3 may be formed between the conducting segments 202 b and 202 d.
  • a capacitor C 4 may be formed between the conducting segments 202 e and 202 f.
  • FIG. 4 is a diagram illustrating a side view diagram of the metal-dielectric-metal capacitor 202 k of the digital circuit block 200 along line I-I′ as shown in FIG. 2 .
  • the via 202 h and the capacitor C 2 is omitted in the side view diagram of FIG. 4 for the purpose of illustration, and the vias 202 h ′ and 202 i illustrated in dotted line represents that the vias 202 h ′ and 202 i are in the background from the line I-I′ and the via 202 g ′ is in the foreground from the line I-I′.
  • the metal-dielectric-metal capacitor 202 k comprises the conducting segment 202 a, the conducting segment 202 c, a top plate 402 , a bottom plate 404 , and a dielectric plate 406 , in which the dielectric plate 406 can be implemented by an oxide layer.
  • the conducting segment 202 a is electrically connected with the top plate 402 through the via 202 g ′
  • the conducting segment 202 c is electrically connected with the bottom plate 404 through the via 202 h ′.
  • the metal-dielectric-metal capacitor 202 k provides another capacitive element between the first conducting path 2022 and the second conducting path 2024 .
  • the metal-dielectric-metal capacitor can be implemented between any two conducting layers, such as the conducting layer L 6 and L 5 of the above-mentioned embodiment, and can be rearranged into any appropriate shape depending on the configuration between the first conducting path 2022 and the second conducting path 2024 . Besides, it is not necessary for the two conducting layers to be adjacent to each other. Since the metal-dielectric-metal capacitor is well-known to those skilled in this art, a detailed description is omitted here for brevity.
  • the digital logic 2026 loads the current from the supply voltage Vdd at the first conducting path 2022 , the energy that is stored in the capacitors C 1 , C 2 , C 3 , and C 4 can provide the required current to the digital logic 2026 instantaneously. Therefore, the supply voltage Vdd IR drop (e.g., dynamic voltage drop) of the digital logic 2026 can be minimized. Furthermore, since the capacitors C 1 , C 2 , C 3 , and C 4 store the energy (i.e., electric charge) in the region of the conducting layer of the semiconductor architecture, but do not utilize the substrate of the semiconductor architecture to store the energy as in the prior art, the leakage current of the layout architecture 202 of the digital circuit block 200 is much smaller than the prior art current.
  • FIG. 5 is a flowchart illustrating a method 500 for reducing the supply voltage drop in the digital circuit block 202 of the embodiment as shown in FIG. 2 .
  • the method 500 comprises:
  • Step 502 performing a supply voltage path routing, such as an auto placement and routing (APR) process upon the digital logic 2026 to generate the first conducting path 2022 and the second conducting path 2024 ;
  • APR auto placement and routing
  • Step 504 determining a region between the first conducting path 2022 and the second conducting path 2024 for the layout architecture 202 ;
  • Step 506 constructing the conducting segment 202 a, 202 b having the first end electrically connected to the first conducting path 2022 and a second end not electrically connected to the second conducting path 2024 , wherein the conducting segment 202 a, 202 b are located in layer L 6 ;
  • Step 508 constructing the conducting segment 202 c, 202 d having a first end electrically connected to the second conducting path 2024 and a second end not electrically connected to the first conducting path 2022 , wherein the conducting segment 202 c, 202 d are located in layer L 6 ;
  • Step 510 constructing the conducting segment 202 e, 202 f in the layer L 5 ;
  • Step 512 utilizing the vias 202 h and 202 j to couple the conducting segments 202 c and 202 d to the conducting segment 202 f respectively, and utilizing the vias 202 g and 202 i to couple the conducting segments 202 a and 202 b to the conducting segment 202 e respectively; and
  • Step 514 constructing the metal-dielectric-metal capacitor 202 k under the region between the conducting segments 202 a and 202 c.
  • the first conducting path 2022 may be coupled to the supply voltage Vdd and the second conducting path 2024 may be coupled to the ground voltage Vgnd (Step 502 ).
  • one of the embodiments of the present invention may have filler capacitor cells between the region of the first conducting path 2022 and the second conducting path 2024 , and it may be necessary for the method 500 to remove the filler capacitor cells first.
  • the region between the first conducting path 2022 and the second conducting path 2024 can be utilized for constructing the layout architecture 202 (Step 504 ).
  • this is just an optional step of the embodiment, and not a limitation of the present invention.
  • the APR process may automatically provide the regions for the layout architecture 202 after performing the APR process upon the digital circuit block 200 .
  • the capacitor C 1 is formed between the overlapped region of the conducting segments 202 d and 202 e, which is formed by a portion 202 d ′; and the capacitor C 2 is formed between the overlapped region of the conducting segments 202 b and 202 f, which is formed by a portion 202 b ′. Furthermore, the capacitor C 3 is formed between the conducting segments 202 b and 202 d. Similarly, the capacitor C 4 is formed between the conducting segments 202 e and 202 f.
  • the metal-dielectric-metal capacitor 202 k is constructed under the region between the conducting segments 202 a and 202 c, and comprises the conducting segment 202 a, the conducting segment 202 c, a top plate 402 , a bottom plate 404 , and a dielectric plate 406 as shown in FIG. 4 .
  • the method 500 utilizes the via 202 g ′ to electrically connect the conducting segment 202 a with the top plate 402 , and utilizes the via 202 h ′ to electrically connect the conducting segment 202 c with the bottom plate 404 . Therefore, the metal-dielectric-metal capacitor 202 k provides another capacitive element between the first conducting path 2022 and the second conducting path 2024 .
  • the metal-dielectric-metal capacitor can be implemented between any two conducting layers, such as the conducting layer L 6 and L 5 in the above-mentioned embodiment, and can be rearranged into any appropriate shape depending on the configuration between the first conducting path 2022 and the second conducting path 2024 . Besides, it is not necessary for the two conducting layers to be adjacent to each other. Since the Metal-dielectric-metal capacitor is well-known to those skilled in this art, a detailed description is omitted here for brevity.
  • the layout architecture 202 generated under the method 500 is just an example of the present invention, and not a limitation of the present invention.
  • the number of the conducting segments, vias, and metal-dielectric-metal capacitors and the arrangement between the conducting segments, vias, and metal-dielectric-metal capacitors can be adjusted according to practical conditions, such as the area available for the layout architecture 202 , of the implementation of the digital circuit block 202 .

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US12/358,215 2009-01-22 2009-01-22 Method for reducing supply voltage drop in digital circuit block and related layout architecture Abandoned US20100181847A1 (en)

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US12/358,215 US20100181847A1 (en) 2009-01-22 2009-01-22 Method for reducing supply voltage drop in digital circuit block and related layout architecture
TW098112643A TWI385921B (zh) 2009-01-22 2009-04-16 減少數位電路區塊供應電壓降的方法及其佈局架構
CN2009101375136A CN101789779B (zh) 2009-01-22 2009-04-28 减少数字电路区块供应电压降的方法及其布局结构
US13/298,315 US8640074B2 (en) 2009-01-22 2011-11-17 Digital circuit block having reducing supply voltage drop and method for constructing the same

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102643003B1 (ko) * 2016-12-14 2024-03-05 삼성전자주식회사 파워 레일의 오믹 강하를 감소하는 회로 체인을 포함하는 집적 회로
US11322491B1 (en) 2020-10-15 2022-05-03 Nxp Usa, Inc. Integrated grid cell

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569745A (en) * 1968-11-06 1971-03-09 Sylvania Electric Prod Transistor logic circuit
US4404059A (en) * 1982-05-26 1983-09-13 Livshits Vladimir I Process for manufacturing panels to be used in microelectronic systems
US4937649A (en) * 1986-09-12 1990-06-26 Nec Corporation Semiconductor integrated circuit having a capacitor for stabilizing a voltage at a power supplying wiring
US5298802A (en) * 1988-04-02 1994-03-29 Hitachi, Ltd. Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions
US6232154B1 (en) * 1999-11-18 2001-05-15 Infineon Technologies North America Corp. Optimized decoupling capacitor using lithographic dummy filler
US6330044B1 (en) * 1997-02-27 2001-12-11 Seiko Epson Corporation Apparatus for providing light shielding in a liquid crystal display
US6496021B2 (en) * 1996-02-14 2002-12-17 Stmicroelectronics, Inc. Method for making a capacitive distance sensor
US6876208B2 (en) * 2001-12-25 2005-04-05 Renesas Technology Corp. Semiconductor device and method of checking semiconductor storage device
US6898769B2 (en) * 2002-10-10 2005-05-24 International Business Machines Corporation Decoupling capacitor sizing and placement
US20080047743A1 (en) * 2004-11-19 2008-02-28 Akeyuki Komatsu Multilayer Substrate With Built-In Capacitors, Method For Manufacturing The Same, And Cold-Cathode Tube Lighting Device
US20090001369A1 (en) * 2007-06-28 2009-01-01 Lin Wallace W Evaluation method for interconnects interacted with integrated-circuit manufacture
US20090027328A1 (en) * 2004-08-23 2009-01-29 Koninklijke Philips Electronics, N.V. Active matrix devices
US20090057746A1 (en) * 2007-09-05 2009-03-05 Renesas Technology Corp. Semiconductor device
US20090109597A1 (en) * 2006-06-02 2009-04-30 Anthony Michael P Metal-insulator-metal capacitors
US7683627B2 (en) * 2006-07-13 2010-03-23 Nec Electronics Corporation Semiconductor device having a function of detection breakages on a periphery thereof
US7730434B2 (en) * 2003-08-25 2010-06-01 Tau-Metrix, Inc. Contactless technique for evaluating a fabrication of a wafer
US20100148304A1 (en) * 2008-12-11 2010-06-17 Irfan Rahim Integrated circuit decoupling capacitors
US7741700B2 (en) * 2004-03-30 2010-06-22 Nec Corporation Transistor with heat dissipating means
US20100295138A1 (en) * 2009-05-20 2010-11-25 Baolab Microsystems Sl Methods and systems for fabrication of mems cmos devices

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548224A (en) * 1995-01-20 1996-08-20 Vlsi Technology, Inc Method and apparatus for wafer level prediction of thin oxide reliability
DE69515669T2 (de) * 1995-10-31 2000-07-27 Stmicroelectronics S.R.L., Agrate Brianza Negative Ladungspumpenschaltung für elektrisch löschbare Halbleiterspeichervorrichtung
AU2003900746A0 (en) * 2003-02-17 2003-03-06 Silverbrook Research Pty Ltd Methods, systems and apparatus (NPS041)
AU2003207078A1 (en) * 2002-02-07 2003-09-02 Yokowo Co., Ltd. Capacity load type probe, and test jig using the same
US6904582B1 (en) * 2002-02-28 2005-06-07 Dupont Photomasks, Inc. Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same
JP4003750B2 (ja) * 2003-04-17 2007-11-07 セイコーエプソン株式会社 静電容量検出装置
KR100942841B1 (ko) * 2003-06-02 2010-02-18 엘지디스플레이 주식회사 액정표시소자의 검사 방법 및 장치와 리페어방법 및 장치
US7319341B1 (en) * 2003-08-28 2008-01-15 Altera Corporation Method of maintaining signal integrity across a capacitive coupled solder bump
JP3858864B2 (ja) * 2003-08-29 2006-12-20 セイコーエプソン株式会社 静電容量検出装置
US7181966B2 (en) * 2004-09-08 2007-02-27 Nippon Soken, Inc. Physical quantity sensor and method for manufacturing the same
KR100752289B1 (ko) * 2004-12-28 2007-08-29 세이코 엡슨 가부시키가이샤 단위 회로, 그 제어 방법, 전자 장치 및 전자 기기
JP2006190889A (ja) * 2005-01-07 2006-07-20 Fujitsu Ltd 半導体装置とその製造方法
US7395717B2 (en) * 2006-02-10 2008-07-08 Milliken & Company Flexible capacitive sensor
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US7935965B1 (en) * 2008-05-16 2011-05-03 Pdf Solutions, Inc. Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569745A (en) * 1968-11-06 1971-03-09 Sylvania Electric Prod Transistor logic circuit
US4404059A (en) * 1982-05-26 1983-09-13 Livshits Vladimir I Process for manufacturing panels to be used in microelectronic systems
US4937649A (en) * 1986-09-12 1990-06-26 Nec Corporation Semiconductor integrated circuit having a capacitor for stabilizing a voltage at a power supplying wiring
US5298802A (en) * 1988-04-02 1994-03-29 Hitachi, Ltd. Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions
US6496021B2 (en) * 1996-02-14 2002-12-17 Stmicroelectronics, Inc. Method for making a capacitive distance sensor
US6330044B1 (en) * 1997-02-27 2001-12-11 Seiko Epson Corporation Apparatus for providing light shielding in a liquid crystal display
US6232154B1 (en) * 1999-11-18 2001-05-15 Infineon Technologies North America Corp. Optimized decoupling capacitor using lithographic dummy filler
US6876208B2 (en) * 2001-12-25 2005-04-05 Renesas Technology Corp. Semiconductor device and method of checking semiconductor storage device
US6898769B2 (en) * 2002-10-10 2005-05-24 International Business Machines Corporation Decoupling capacitor sizing and placement
US7730434B2 (en) * 2003-08-25 2010-06-01 Tau-Metrix, Inc. Contactless technique for evaluating a fabrication of a wafer
US7741700B2 (en) * 2004-03-30 2010-06-22 Nec Corporation Transistor with heat dissipating means
US20090027328A1 (en) * 2004-08-23 2009-01-29 Koninklijke Philips Electronics, N.V. Active matrix devices
US20080047743A1 (en) * 2004-11-19 2008-02-28 Akeyuki Komatsu Multilayer Substrate With Built-In Capacitors, Method For Manufacturing The Same, And Cold-Cathode Tube Lighting Device
US20090109597A1 (en) * 2006-06-02 2009-04-30 Anthony Michael P Metal-insulator-metal capacitors
US7683627B2 (en) * 2006-07-13 2010-03-23 Nec Electronics Corporation Semiconductor device having a function of detection breakages on a periphery thereof
US20090001369A1 (en) * 2007-06-28 2009-01-01 Lin Wallace W Evaluation method for interconnects interacted with integrated-circuit manufacture
US20090057746A1 (en) * 2007-09-05 2009-03-05 Renesas Technology Corp. Semiconductor device
US20100148304A1 (en) * 2008-12-11 2010-06-17 Irfan Rahim Integrated circuit decoupling capacitors
US20100295138A1 (en) * 2009-05-20 2010-11-25 Baolab Microsystems Sl Methods and systems for fabrication of mems cmos devices

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CN101789779B (zh) 2012-07-04
CN101789779A (zh) 2010-07-28
US8640074B2 (en) 2014-01-28
TWI385921B (zh) 2013-02-11
TW201028875A (en) 2010-08-01
US20120056488A1 (en) 2012-03-08

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