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US20080194183A1 - Planarization polishing method and method for manufacturing semiconductor device - Google Patents

Planarization polishing method and method for manufacturing semiconductor device Download PDF

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Publication number
US20080194183A1
US20080194183A1 US12/010,922 US1092208A US2008194183A1 US 20080194183 A1 US20080194183 A1 US 20080194183A1 US 1092208 A US1092208 A US 1092208A US 2008194183 A1 US2008194183 A1 US 2008194183A1
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United States
Prior art keywords
polishing
surfactant
planarization
slurry
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US12/010,922
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English (en)
Inventor
Mika Fujii
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Sony Corp
Original Assignee
Sony Corp
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Filing date
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Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJII, MIKA
Publication of US20080194183A1 publication Critical patent/US20080194183A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
    • H02G3/00—Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
    • H02G3/02—Details
    • H02G3/04—Protective tubing or conduits, e.g. cable ladders or cable troughs
    • H02G3/0456—Ladders or other supports
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B24B37/044—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor characterised by the composition of the lapping agent
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
    • F16B17/00—Connecting constructional elements or machine parts by a part of or on one member entering a hole in the other and involving plastic deformation
    • F16B17/006—Connecting constructional elements or machine parts by a part of or on one member entering a hole in the other and involving plastic deformation of rods or tubes to sheets or plates
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
    • F16B37/00—Nuts or like thread-engaging members
    • F16B37/04—Devices for fastening nuts to surfaces, e.g. sheets, plates
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
    • H02G3/00—Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
    • H02G3/02—Details
    • H02G3/04—Protective tubing or conduits, e.g. cable ladders or cable troughs
    • H02G3/0406—Details thereof
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
    • H02G3/00—Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
    • H02G3/30—Installations of cables or lines on walls, floors or ceilings
    • H10P95/062—

Definitions

  • the present invention contains subject matter related to Japanese Patent Application JP 2007-029798 filed in the Japan Patent Office on Feb. 8, 2007, the entire contents of which being incorporated herein by reference.
  • the present invention relates to a planarization polishing method used in a semiconductor manufacturing process and a method for manufacturing a semiconductor device.
  • a chemical mechanical polishing (CMP) technique is widely used as a technique for surface planarization in a step for forming shallow trench isolation (STI) regions serving as element isolation regions of the semiconductor integrated circuit.
  • CMP chemical mechanical polishing
  • STI regions in a semiconductor device are formed in the manner shown in FIG. 6 .
  • a silicon nitride (SiN) film 2 is deposited on a surface of a silicon semiconductor substrate 1 .
  • a resist mask (not shown) is formed on the silicon nitride film 2 by using a photolithography technique.
  • This resist mask has a required pattern having apertures in the areas corresponding to the STI regions that are to be formed.
  • the silicon nitride film 2 is patterned by dry etching through the resist mask, and trenches 3 with the required pattern are formed in the silicon substrate 1 by dry etching with use of the silicon nitride film 2 as the etching mask.
  • the regions in which the silicon nitride film 2 is formed will serve as element formation regions later.
  • a silicon oxide (SiO2) film 4 is buried in the trenches 3 by chemical vapor deposition (CVD). In this burying, the silicon oxide film 4 is deposited also on the substrate surface (i.e., the silicon nitride film 2 ) outside the trenches 3 .
  • the silicon oxide (SiO2) film deposited on the substrate surface outside the trenches 3 is polished and removed by CMP. This forms STI regions (element isolation regions) 5 arising from the burying of the silicon oxide film 4 in the trenches 3 .
  • the silicon nitride film 2 is removed, followed by formation of required semiconductor elements in the areas from which the silicon nitride film 2 has been removed.
  • Recent enhancement in the integration degree of semiconductor elements requires CMP treatment for the formation of the STI regions 5 (so-called STI-CMP process) to have higher planarization performance.
  • silica-based slurry which is used for polishing of an oxide film in related arts, is becoming incapable of meeting the required performance. This is due to unevenness, in the semiconductor wafer plane, of the area rate of the silicon nitride film 2 on which the silicon oxide film 4 is formed into a projection shape, i.e., the area rate of the region that will serve as the element formation region later.
  • a silicon oxide film 4 a with a large-height projection shape is deposited.
  • a silicon oxide film 4 b with a small-height projection shape is deposited.
  • the silicon oxide film 4 in the trenches 3 around a region in which the area rate of a projection is low is excessively polished due to the selection ratio of the silicon oxide film 4 to the silicon nitride film 2 .
  • This excessive polishing causes so-called dishing 6 as shown in FIG. 6E , which deteriorates the planarity.
  • the planarity deterioration causes the lowering of the reliability and yield of semiconductor elements.
  • a polishing method employs ceria-based slurry containing ceria (cerium oxide: CeO2) abrasive grains and an additive agent (so-called surfactant).
  • ceria-based slurry containing ceria (cerium oxide: CeO2) abrasive grains and an additive agent (so-called surfactant).
  • the additive agent in a projection part on a polishing-target surface, the additive agent is dislodged due to pressure concentration in the polishing and thus the polishing proceeds.
  • the polishing is suppressed by the additive agent absorbed in the recess part. That is, this method is intended to selectively polish the projection part to thereby obtain a polished surface with high planarity.
  • This ceria-based slurry is advantageous over the silica-based slurry not only in the planarity but also in the polishing rate and the selection ratio.
  • a high-planarization polishing method employing ceria abrasive grains is disclosed in e.g. Japanese Patent Laid-open No. 2004-14624 (hereinafter refereed to as Patent Document 1).
  • a CMP polishing liquid polishing slurry
  • cerium oxide particles and a surfactant having selective absorbability to a silicon nitride film is used, and high-planarization polishing is carried out by using an effect of decreasing the polishing rate of a silicon nitride film due to the surfactant.
  • the ceria-based slurry has also a problem of causing more scratches compared with silica-based slurry.
  • the yield is problematically deteriorated.
  • planarization polishing method that allows polishing based on CMP to offer higher planarity, and a method for manufacturing a semiconductor device with use of this planarization polishing method.
  • a planarization polishing method for polishing a polishing-target wafer for a planarized surface.
  • the method includes the step of polishing a polishing target surface into a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.
  • the polishing-target surface is an oxide film.
  • a method for manufacturing a semiconductor device includes the step of, for formation of an STI region serving as an element isolation region, polishing an oxide film deposited on a region other than a trench of a semiconductor substrate for a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.
  • the surfactant contained in the polishing slurry is encapsulated through coating of its surface. Therefore, the surfactant is selectively supplied only to a small-height region that should be protected by the surfactant through the breaking of the capsules. In contrast, in the other region, the capsules are not broken, so that no protection effect is provided and thus the polishing proceeds. This feature allows high-planarization polishing.
  • the surfactant directly acts on the polishing-target surface in linkage with the progression of polishing in the polishing-target wafer plane, and thus high-planarization polishing can be carried out.
  • the surfactant directly acts on the polishing-target surface in linkage with the progression of polishing in the polishing-target wafer plane, and thus high-planarization polishing free from the influence of difference in the density of the element formation region can be carried out.
  • FIG. 1 is a structural diagram showing the schematic structure of CMP apparatus used in embodiments of the present invention.
  • FIG. 2 is a schematic sectional view of an encapsulated surfactant
  • FIGS. 3A to 3C are manufacturing step diagrams showing a planarization polishing method and a method for manufacturing a semiconductor device with use of this polishing method according to one embodiment of the present invention
  • FIGS. 4D to 4G are manufacturing step diagrams showing the planarization polishing method and the method for manufacturing a semiconductor device with use of this polishing method according to the embodiment;
  • FIG. 5 is a step diagram showing a halfway state in a planarization polishing method and a method for manufacturing a semiconductor device with use of this polishing method according to another embodiment of the present invention
  • FIGS. 6A to 6E are manufacturing step diagrams showing an example of a method for manufacturing a semiconductor device with use of a related-art planarization polishing method.
  • FIGS. 7A and 7B are diagrams for explaining polished states in a related art.
  • the embodiments are applied to manufacturing of a semiconductor device, specifically, a so-called semiconductor integrated circuit, and particularly to planarization polishing of an oxide film by CMP for formation of element isolation regions based on STI for the semiconductor integrated circuit.
  • the polishing-target film is a high-density plasma SiO2 film as one example.
  • FIG. 1 shows the schematic structure of general CMP apparatus used for the polishing of the embodiments.
  • This CMP apparatus 21 has a platen 23 that is disposed rotatably around a rotation shaft 22 , and a polishing pad 24 is disposed on the platen 23 .
  • a slurry feed pipe 26 for supplying polishing slurry 25 according to the embodiments is disposed above the polishing pad 24 .
  • a polishing target that is to be subjected to planarization polishing, i.e., a semiconductor wafer 27 in the present example, is so disposed that its polishing-target surface abuts against the polishing pad 24 .
  • a polishing head 28 is brought into abutting contact with the backside of the semiconductor wafer 27 with a required load.
  • the polishing head 28 is so configured as to be rotated around a shaft 29 together with the semiconductor wafer 27 while applying the required load to the semiconductor wafer 27 .
  • the semiconductor wafer 27 as the polishing-target wafer has a structure similar to the above-described structure shown in FIG. 6C .
  • a silicon nitride (SiN) film 31 is deposited on a surface of a silicon semiconductor substrate 27 a, and a resist mask having apertures based on a required pattern is formed on the silicon nitride film 31 by using a photolithography technique.
  • the silicon nitride film 31 is patterned by dry etching through this resist mask, and then trenches 32 based on the required pattern are formed in the silicon substrate 27 a by using the silicon nitride film 31 as the etching mask.
  • trenches 32 are formed at the positions corresponding to STI regions serving as element isolation regions.
  • a silicon oxide (SiO2) film 33 is deposited by CVD across the entire substrate surface in such a manner as to be buried in the trenches 32 .
  • the semiconductor wafer 27 is formed that has projection regions 33 a and 33 b of the silicon oxide film depending on difference in the area rate of the silicon nitride film 31 , i.e., the projection region 33 a that has a high area rate and large height and the projection regions 33 b that exist near the projection region 33 a and has a low area rate and small height.
  • planarization polishing method employing the CMP apparatus 21 in FIG. 1 according to one embodiment of the present invention and a method for manufacturing a semiconductor device in which the semiconductor wafer 27 is subjected to planarization polishing by using this planarization polishing method to thereby form STI regions.
  • the above-described semiconductor wafer 27 is so disposed that its polishing-target surface abuts on the polishing pad 24 of the CMP apparatus 21 .
  • polishing is started in such a way that the polishing slurry 25 according to the present embodiment is dropped on the polishing pad 24 from the slurry feed pipe 26 and the polishing-target surface of the semiconductor wafer 27 held by the polishing head 28 is pressed against the polishing pad 24 to thereby apply a load to the semiconductor wafer 27 as shown in FIGS. 3A and 3B .
  • the polishing slurry 25 contains ceria abrasive grains (not shown) and a surfactant 36 (indicated by the white circles) that is encapsulated through coating of its surface. This surfactant has an effect of protecting the silicon oxide film 33 that is to be polished. As shown in FIG. 2 , this encapsulated surfactant 36 is formed by covering a surfactant 37 by a coating wall 35 .
  • the specific slurry composition will be described later.
  • the encapsulated surfactant 36 is attached to the whole of the polishing-target surface, including the projection regions 33 a and 33 b.
  • the encapsulated surfactant 36 attached to the projection regions 33 a and 33 b on the polishing-target surface contacts with the polishing pad 24 and thus is pushed away by the polishing pad 24 , so that the dislodged surfactant 36 attaches to recess regions 33 c on the polishing-target surface.
  • polishing of the projection regions is progressed as shown in FIG. 3C .
  • the polishing for the projection regions 33 b which have a low area rate and small height, proceeds fast. Therefore, as shown in enlarged view A, pressure and shear force are applied to the encapsulated surfactant 36 existing in the vicinity of the recess regions.
  • the capsules are broken by the pressure and shear force, so that the surfactant 37 (indicated by the black circles) is discharged.
  • the recesses 33 c are protected by the surfactant 37 and thus the progression of polishing of the recesses 33 c is suppressed.
  • the capsules are broken in linkage with the progression of the polishing of the projection region 33 a, so that the surfactant 37 works sequentially.
  • planarization polishing is carried out across the entire region eventually irrespective of difference in the area rate of the silicon nitride film 31 , i.e., difference in the density of the element formation region, and the planarization polishing treatment is completed at the timing when the silicon nitride film 31 is exposed.
  • a polished surface with high planarity is obtained.
  • favorable STI regions 38 are formed without the occurrence of dishing.
  • the silicon nitride film 31 is removed, and then required semiconductor elements are formed in the element formation regions arising from the removal of the silicon nitride film 31 , so that an intended semiconductor device is obtained.
  • the planarization polishing until the silicon nitride film 31 is exposed is carried out in one time of polishing treatment. However, it is also possible to carry out it in two times of treatment.
  • first polishing treatment until projection regions 33 a and 33 b of a silicon oxide film 33 on the polishing-target surface are planarized is carried out by using polishing slurry prepared by adding a capsulated surfactant to ceria-based slurry.
  • polishing slurry prepared by adding a capsulated surfactant to ceria-based slurry is carried out by using polishing slurry prepared by adding a capsulated surfactant to ceria-based slurry.
  • the procedure of the present embodiment leads to, through the above-described step of FIG. 4F , a step of FIG. 5 in which the silicon oxide film 33 is planarized.
  • second polishing treatment until the silicon nitride film 31 is exposed is carried out, so that the high-planarization polishing for the above-described state of FIG. 4G is completed.
  • This second polishing treatment may be carried out by using only polishing slurry to which no surfactant is added.
  • the polishing-target surface has been already planarized and the remaining film is thin. Therefore, without a surfactant, the polishing can be completed in such a way that a polished surface having high planarity is kept (see FIG. 4G ).
  • the same ceria-based slurry as that used in the first treatment may be used.
  • silica-based, alumina-based, or ferric nitrate-based slurry can be used. In terms of scratches, it is desirable to complete a polished surface by using silica-based slurry in particular.
  • polishing slurry containing a surfactant encapsulated through coating thereof employs polishing slurry containing a surfactant encapsulated through coating thereof.
  • the required amount (2 wt %, in the present example) of the coated surfactant is added to the polishing slurry in advance, and polishing is carried out under the following condition in such a way that the polishing slurry is supplied on a polishing-target wafer via a polishing pad.
  • the diameter of the ceria particles i.e., the particle diameter of cerium oxide (CeO2), can be set to 50 nm to 250 nm.
  • acid ceria-based slurry is used as the polishing slurry in the present example
  • silica-based slurry, alumina-based slurry, ferric nitrate-based slurry, or the like may be used instead of the ceria-based slurry.
  • the additive amount of the coated surfactant be in the range of 0.1 to 10 wt %. This concentration range offers favorable polishing characteristics (planarity, polishing rate).
  • the coated surfactant As a method for supplying the coated surfactant, a method is available in which the coated surfactant is mixed into the polishing slurry in advance and the resultant slurry is supplied. As another method, the coated surfactant may be supplied as an aqueous solution separately from the polishing slurry. Alternatively, a surfactant feed pipe for supplying the surfactant aqueous solution may be communicated with a slurry feed pipe for the supply of the coated surfactant.
  • the material of the surfactant that is to be coated a substance having an effect of suppressing polishing of an oxide film is used.
  • alkylbenzene sulfonate is used as the surfactant.
  • any of the following substances may be used: a fatty acid sodium salt, alkyl sulfate, sulfate ester salt, fatty acid potassium salt, polyoxyethylene alkyl ether sulfate, fatty acid ester, a-olefin sulfonate, monoalkyl phosphate ester salt, alkane sulfonate, amino acid, polyacrylate, polyacrylate ammonium salt, polycarboxylate ammonium salt, sulfosuccinate diester salt, alkylamine hydrochloride, and alkyl ether sulfonate.
  • the coating material for encapsulation a substance that can be easily treated in coating processing and will not alter the surfactant and polishing slurry is used.
  • polyurethane resin is used.
  • any of the following polymer materials may be used as long as the material offers an unreactive combination with the surfactant and slurry: polystyrene resin, polyester resin, polyurea resin, polyamide resin, polyethylene resin, polyvinyl alcohol resin, polycarbonate resin, melamine resin, urea resin, and gelatin.
  • the size of the surfactant molecules is about 2 nm to 3 nm.
  • the size of the coated surfactant can be set to about 10 nm to 5000 nm.
  • the term “encapsulated surfactant” encompasses a coated single-substance surfactant and a matter arising from coating of an aggregation of plural single-substance surfactants.
  • the thickness of the coating film with respect to the encapsulated surfactant is so designed that the coating film has such mechanical strength as to be broken by polishing pressure and shear force applied to the film at the time of polishing. That is, the mechanical strength of the coating film is set equal to or lower than that by the polishing pressure and shear force.
  • the methods for coating the surfactant are roughly categorized into chemical methods, physicochemical methods, and mechanical methods.
  • Examples of the surfactant coating method according to the embodiments include seamless encapsulation, interfacial polymerization, in-situ polymerization, drying-in-liquid, coacervation, spray drying, and dry mixing.
  • a method for coating the surfactant as a liquid interfacial polymerization, in-situ polymerization, coacervation, seamless encapsulation, and so on are suitable.
  • polishing slurry to which a coated surfactant is added is used. Therefore, the surfactant as an additive agent directly acts on a polishing-target surface selectively in linkage with the progression of polishing in the polishing-target wafer plane. This allows high-planarization polishing free from the influence of difference in the density of the element formation region with high accuracy and efficiency, which enhances the reliability and yield of semiconductor elements. Furthermore, the use amount of the surfactant can be suppressed to the necessary minimum, and thus the manufacturing cost of the semiconductor device can be reduced.
  • the planarization polishing method according to the embodiments is carried out by using polishing slurry that contains abrasive grains and a surfactant encapsulated through surface coating.
  • polishing pressure and shear force are applied to the encapsulated surfactant attached to recesses in the vicinity of the projections. Consequently, the coating film is broken and thus the surfactant is discharged, so that the discharged surfactant selectively suppresses the progression of polishing of the vicinity.
  • the surfactant sequentially works in linkage with the progression of polishing of projections. This allows high-planarization polishing free from the influence of difference in the density of the element formation region, and thus enhances the reliability and yield of semiconductor elements.
  • the surfactant selectively works depending on the kind of film of a polishing-target surface.
  • the surfactant works in linkage with the progression of polishing dependent upon difference in the pattern density.
  • planarization can be carried out for a polishing-target surface of which entire region is composed of the same material, appearing before exposure of a different kind of material (e.g., when a polishing-target surface is composed of SiO2, SiN is the different kind of material) through the polishing-target surface, and thus higher-planarization polishing is possible.
  • the remaining film is thin at the timing when the high-planarization polishing has been completed, it is also possible to carry out finishing polishing, with the high planarity kept, by using e.g. silica-based slurry involving fewer scratches. This can reduce scratches, which are a problem in ceria-based slurry, and thus enhances the flexibility in the polishing process.
  • the planarization polishing method of the embodiments is applied to polishing of a semiconductor wafer.
  • the method can be applied also to polishing of another substrate (wafer) of which polishing-target surface has an oxide film.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Civil Engineering (AREA)
  • Structural Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
US12/010,922 2007-02-08 2008-01-31 Planarization polishing method and method for manufacturing semiconductor device Abandoned US20080194183A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-029798 2007-02-08
JP2007029798A JP2008198668A (ja) 2007-02-08 2007-02-08 平坦化研磨方法及び半導体装置の製造方法

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US (1) US20080194183A1 (zh)
JP (1) JP2008198668A (zh)
KR (1) KR20080074722A (zh)
CN (1) CN101239453A (zh)
TW (1) TW200845168A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104108072A (zh) * 2013-04-16 2014-10-22 陈炤彰 气体添加研磨液的供应系统及其方法
CN109590820A (zh) * 2019-01-02 2019-04-09 中国科学院上海光学精密机械研究所 超硬激光晶体表面粗糙度的加工方法
US20200298363A1 (en) * 2019-03-19 2020-09-24 Toshiba Memory Corporation Polishing device and polishing method

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171409A (ja) * 2010-02-17 2011-09-01 Disco Corp ウエーハの研磨方法
TWI443741B (zh) * 2011-01-14 2014-07-01 國立交通大學 一種平整化氮化物基板的方法
CN105199668A (zh) * 2015-08-14 2015-12-30 芜湖真空科技有限公司 Low-e玻璃用磨边材料及其制备方法
US10199255B2 (en) * 2016-03-10 2019-02-05 Infineon Technologioes AG Method for providing a planarizable workpiece support, a workpiece planarization arrangement, and a chuck

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104108072A (zh) * 2013-04-16 2014-10-22 陈炤彰 气体添加研磨液的供应系统及其方法
CN109590820A (zh) * 2019-01-02 2019-04-09 中国科学院上海光学精密机械研究所 超硬激光晶体表面粗糙度的加工方法
US20200298363A1 (en) * 2019-03-19 2020-09-24 Toshiba Memory Corporation Polishing device and polishing method

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KR20080074722A (ko) 2008-08-13
JP2008198668A (ja) 2008-08-28
CN101239453A (zh) 2008-08-13

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