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US20070075385A1 - Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same - Google Patents

Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same Download PDF

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Publication number
US20070075385A1
US20070075385A1 US11/243,165 US24316505A US2007075385A1 US 20070075385 A1 US20070075385 A1 US 20070075385A1 US 24316505 A US24316505 A US 24316505A US 2007075385 A1 US2007075385 A1 US 2007075385A1
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Prior art keywords
oxide
gate
forming
substrate
layer
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Abandoned
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US11/243,165
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English (en)
Inventor
Tzyh-Cheang Lee
Jiunn-Ren Hwang
Tsung-Lin Lee
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US11/243,165 priority Critical patent/US20070075385A1/en
Priority to TW095102589A priority patent/TWI267201B/zh
Priority to CNA2006100649648A priority patent/CN1945851A/zh
Publication of US20070075385A1 publication Critical patent/US20070075385A1/en
Priority to US12/648,598 priority patent/US8653576B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

  • the present invention relates to nonvolatile memory devices, and particularly to a sidewall SONOS.(silicon-oxide-nitride-oxide-silicon) gate structure with dual-thickness oxide and methods of fabricating a nonvolatile memory device having the same.
  • Nonvolatile memories are classified into a stacked gate structure and a SONOS (silicon-oxide-nitride-oxide-silicon) gate structure depending on the type of its gate structure.
  • the SONOS gate structure has gained increased interest due to the simplicity of the bitcell structure and process, low-voltage operation and its immunity to extrinsic charge loss as compared to traditional floating gate based nonvolatile memories.
  • the SONOS gate structure nonvolatility is achieved by storing charge in nitride traps and surrounding the nitride with oxide to form an oxide-nitride-oxide stack on the sidewall of a gate electrode, also named a sidewall SONOS gate structure, which does not include a floating gate and is compatible with standard logic CMOS fabrication processes.
  • the sidewall SONOS gate structure typically utilizes thin and uniform tunnel oxide for both electron program and hole erase operations resulting in programming time slower than desired for many high-density embedded flash applications. Since the tunnel oxide is formed after the gate formation, the use of a thin bottom oxide grown on the silicon substrate for providing a thin tunnel oxide, however, also provides a thin sidewall oxide grown on the gate sidewall, which causes severe read disturb in the selected bitcell and gate disturb in the unselected bitcells sharing the same word line during a read operation.
  • One approach to minimize gate disturb for the sidewall SONOS gate structure would be to increase the thickness of the tunnel oxide, but the use of the much thicker tunnel oxide will lower program/erase (P/E) speed. It is therefore desirable to provide a novel SONOS gate structure for inhibiting gate disturb and keeping high program/erase efficiency simultaneously.
  • Embodiments of the present invention include a sidewall SONOS gate structure with dual-thickness oxide for reducing impacts of tunnel thickness on gate disturb and program/erase speed and methods of fabricating the same.
  • the present invention provides a SONOS gate structure comprising: a gate pattern with sidewalls on a substrate, wherein the gate pattern comprises a gate dielectric layer and a gate electrode; an oxide structure on the substrate and the sidewalls of the gate pattern, wherein the oxide structure comprises a relatively thinner oxide portion on the substrate and a relatively thicker oxide portion on one of the sidewalls of the gate pattern; and trapping dielectric spacers on the oxide structure laterally adjacent to the sidewalls of the gate pattern respectively.
  • the present invention provides a method of forming a SONOS gate structure, comprising: forming a gate pattern with sidewalls on a substrate, wherein the gate pattern comprises a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer; forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers, wherein the second oxide layer on the substrate is a relatively thinner oxide portion, and a combination of the oxide spacer and the second oxide layer along one of the sidewalls of the gate pattern is a relatively thicker oxide portion; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.
  • the present invention provides a method of forming a SONOS gate structure, comprising: forming a gate pattern with sidewalls on a substrate, wherein the gate pattern comprises a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer; forming a first oxide layer on the gate pattern and the substrate; forming a first dielectric layer on the first oxide layer; etching back the first dielectric layer to expose the first oxide layer, leaving first dielectric spacers on the first oxide layer adjacent to the sidewalls of the gate pattern respectively; etching back the first oxide layer and the first dielectric spacers to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively, and leaving the first dielectric spacers on the oxide spacers respectively; forming a second oxide layer on the exposed portions of the substrate, the gate electrode and the oxide spacers; forming a second dielectric layer on the first dielectric spacers and the second oxide layer; and etching back the second oxide layer on
  • FIG. 1 is a cross-sectional diagram illustrating an exemplary embodiment of a sidewall SONOS gate structure with dual-thickness oxide
  • FIGS. 2A to 2 F are cross-sectional diagrams illustrating a method of forming the dual-thickness oxide scheme for the sidewall SONOS gate structure in accordance with one embodiment of the present invention.
  • FIGS. 3A to 3 F are cross-sectional diagrams illustrating another method of forming the dual-thickness oxide scheme for the sidewall SONOS gate structure in accordance with one embodiment of the present invention.
  • Preferred embodiments of the present invention provide a sidewall SONOS gate structure with dual-thickness oxide for reducing impacts of tunnel thickness on gate disturb and program/erase speed and methods of fabricating the same.
  • the dual-thickness oxide comprises a relatively thinner oxide portion overlying a substrate, serving as a thin tunnel oxide layer for keeping good program/erase efficiency, and a relatively thicker oxide portion overlying sidewalls of a gate electrode for reducing gate disturb.
  • the dual-thickness oxide therefore can inhibit gate disturb and keep high program/erase speed simultaneously.
  • the dual-thickness oxide is intended to include silicon oxide or any other oxide-based dielectric materials.
  • the embodiments of the present invention illustrate an oxide layer for forming a tunnel layer of the SONOS gate structure, the present invention also provides value when using any other dielectric materials for forming the tunnel layer.
  • FIG. 1 illustrates an exemplary embodiment of a sidewall SONOS gate structure with dual-thickness oxide.
  • An example of a sidewall SONOS gate structure comprises a gate pattern with sidewalls 15 on a substrate 10 .
  • the gate pattern includes a gate dielectric layer 12 patterned on a substrate 10 , and a gate electrode 14 patterned on the gate dielectric layer 12 .
  • a dual-thickness oxide structure 16 is provided to line the substrate 10 and the sidewalls 15 of the gate pattern.
  • Trapping dielectric spacers 18 is patterned on the dual-thickness oxide structure 16 laterally adjacent to the sidewalls 15 respectively.
  • Source/drain regions 20 are formed in the substrate 10 separated apart from each other laterally adjacent to the trapping dielectric spacers 18 .
  • the substrate 10 may comprise an elementary semiconductor such as silicon, germanium, or a compound semiconductor.
  • the substrate 10 may include an epitaxial layer overlying a bulk semiconductor, a silicon germanium layer overlying a bulk silicon, a silicon layer overlying a bulk silicon germanium, or a semiconductor-on-insulator (SOI) structure.
  • SOI semiconductor-on-insulator
  • the substrate 10 may comprise an isolation feature to separate different devices formed thereon.
  • the gate dielectric layer 12 may comprises a silicon oxide layer, which may be formed through a thermal oxidation process or a chemical vapor deposition (CVD) process.
  • the gate dielectric layer 12 is also to be appreciated other well-known dielectric material such as nitrides, oxynitride, high-k materials, any other non-conductive materials, and combinations thereof.
  • the thickness of the gate dielectric layer 12 is chosen specifically for the scaling requirements of the sidewall SONOS memory device technology.
  • the gate electrode 14 may comprise a polysilicon layer formed through, for example Low Pressure CVD (LPCVD) methods, CVD methods and Physical Vapor Deposition (PVD) sputtering methods employing suitable silicon source materials. If desired the polysilicon layer may be ion implanted to the desired conductive type. It is to be appreciated other well-known gate electrode material such as metal, metal alloys, single crystalline silicon, or any combinations thereof.
  • the dual-thickness oxide structure 16 includes a thinner oxide portion 16 a on the substrate 10 and a thicker oxide portion 16 b on the sidewalls 15 .
  • the thinner oxide portion 16 a serving as a thin tunnel oxide layer, may reaches to a thickness T 1 , less than or equal to about 60 Angstroms (for example, about 20 ⁇ 60 Angstroms), which can keep good program/erase efficiency.
  • the thicker oxide portion 16 b may reaches to a thickness T 2 greater than or equal to about 70 Angstroms (for example, about 70 ⁇ 200 Angstroms), which can inhibit gate disturb.
  • the dual-thickness oxide structure 16 is preferably made of silicon oxide through the use of a thermal oxidation process or a chemical vapor deposition (CVD) process. Other suitable dielectric materials may be used in place of silicon oxide, for example high-k dielectric materials, metal oxide materials or any other oxide-based materials.
  • the trapping dielectric spacers 18 are formed through advances in deposition, lithography and masking techniques and dry etch processes.
  • the trapping dielectric spacer 18 is preferably a silicon nitride layer.
  • Other suitable dielectric materials may be used in place of silicon nitride, for example silicon oxynitride, boron nitride, or high-k dielectric materials with a high amount of trap-sites.
  • FIGS. 2A to 2 F illustrate a method of forming the dual-thickness oxide scheme for the sidewall SONOS gate structure in accordance with one embodiment of the present invention. Explanation of the same or similar portions to the description in FIG. 1 is omitted herein.
  • a dielectric material, a gate material and a hard mask material are successively deposited on an active area of the substrate 10 , and then those stacked layers are patterned to form a gate pattern 11 with the sidewalls 15 .
  • the gate pattern 11 includes the gate dielectric layer 12 and the gate electrode 14 .
  • the hard mask material is then removed.
  • the patterning step may be accomplished using photolithography and etching to transfer the pattern defined by a photomask to the deposited materials.
  • the photolithography process may include photoresist coating, soft baking, mask aligning, exposing, post-exposure baking, developing photoresist, hard baking, and photoresist stripping.
  • the etching process may include wet etch, dry etch, ion-reactive-etch (RIE), and other suitable processing.
  • a first oxide layer 22 is formed on the substrate 10 , which covers at least the sidewalls 15 .
  • the first oxide layer 22 is grown on the exposed portions of the substrate 10 and the gate electrode 14 through a thermal oxidation process to reach a thickness t 3 from about 100 Angstroms to about 300 Angstroms.
  • the first oxide layer 22 is preferably made of silicon oxide through the use of a thermal oxidation process or a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • Other suitable dielectric materials may be used in place of silicon oxide, for example high-k dielectric materials, metal oxide materials or any other oxide-based materials.
  • the first oxide layer 22 is etched back to expose the top of the gate electrode 14 , leaving oxide spacers 22 a on the sidewalls 15 respectively.
  • certain regions (horizontal portions) of the first oxide layer 22 are etched to expose the substrate 10 and the top of the gate electrode 14 , leaving certain regions (vertical portions) of the first oxide layer 22 laterally adjacent to the gate electrode 14 and the gate dielectric layer 12 .
  • the etch back process may use an anisotropic etch process, such as dry etch, RIE (Reactive Ion Etching), or other plasma etching processes.
  • a second oxide layer 24 is formed on the substrate 10 to line the oxide spacers 22 a and the top of the gate electrode 14 .
  • the second oxide layer 24 is conformally grown on the exposed portions of the substrate 10 , the oxide spacers 24 and the gate electrode 14 through an oxidation process to reach a thickness t 4 from about 20 Angstroms to about 60 Angstroms.
  • the combination of the oxide spacer 22 a and the second oxide layer 24 therefore functions as the dual-thickness oxide structure 16 as described in FIG. 1 , wherein the second oxide layer 24 on the substrate 10 is for the thinner oxide portion 16 a application, and the oxide spacer 22 a combined with the second oxide layer 24 along the sidewall 15 is for the thicker oxide portion 16 b application.
  • the second oxide layer 24 is preferably made of silicon oxide through the use of a thermal oxidation process or a chemical vapor deposition (CVD) process.
  • Other suitable dielectric materials may be used in place of silicon oxide, for example high-k dielectric materials, metal oxide materials or any other oxide-based materials.
  • the second oxide layer 24 is intended to use an oxide material the same as the first oxide layer 22 .
  • the present invention also provides value when the second oxide layer 24 uses an oxide material different from that used in the first oxide layer 22 .
  • a trapping dielectric material 18 a is deposited on the substrate 10 to cover the second oxide layer 24 , and then the trapping dielectric material 18 a is patterned as the dielectric spacers 18 laterally adjacent to the sidewalls 15 respectively, as depicted in FIG. 2F , through advances in lithography and masking techniques and dry etch processes.
  • the trapping dielectric material 18 a is preferably a silicon nitride layer.
  • Other suitable dielectric materials may be used in place of silicon nitride, for example silicon oxynitride, boron nitride, or high-k dielectric materials with a high amount of trap-sites.
  • source/drain regions will be formed in the substrate 10 by implanting ion dopants into the substrate 10 with the trapping dielectric spacers 18 as the implantation mask.
  • the second oxide layer 24 remaining on the top of the gate electrode 14 may be retained or removed, which is not limited in the present invention.
  • FIGS. 3A to 3 F illustrate another method of forming the dual-thickness oxide scheme for the sidewall SONOS gate structure in accordance with one embodiment of the present invention. Explanation of the same or similar portions to the description in FIG. 1 is omitted herein.
  • a dielectric material, a gate material and a hard mask material are successively deposited on an active area of the substrate 10 , and then those stacked layers are patterned to form the gate pattern 11 with the sidewalls 15 .
  • the gate pattern 11 includes the gate dielectric layer 12 and the gate electrode 14 which are sequentially stacked.
  • the hard mask material is then removed.
  • the patterning step including the photolithography process and the etching process is similar to that described in FIG. 2A , thus omitted herein.
  • a first oxide layer 32 and a first dielectric layer 34 are successively formed on the substrate 10 .
  • the first oxide layer 32 is grown on the exposed portions of the substrate 10 and the gate electrode 14 through a thermal oxidation process to reach a thickness t 5 from about 70 Angstroms to about 200 Angstroms.
  • the first oxide layer 32 is preferably made of silicon oxide through the use of a thermal oxidation process or a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • Other suitable dielectric materials may be used in place of silicon oxide, for example high-k dielectric materials, metal oxide materials or any other oxide-based materials.
  • the first dielectric layer 34 is conformally deposited on the first oxide layer 32 through the use of CVD.
  • the first dielectric layer 34 is a silicon nitride layer with a thickness t 6 of about 80 ⁇ 120 Angstroms.
  • Other suitable dielectric materials may be used in place of silicon nitride, for example silicon oxynitride, boron nitride, or high-k dielectric materials with a high amount of trap-sites.
  • the first dielectric layer 34 is etched back to expose horizontal regions of the first oxide layer 32 , leaving dielectric spacers 34 a on the vertical regions of the first oxide layer 32 laterally adjacent to the sidewalls 15 respectively.
  • the etch back process may use an anisotropic etch process, such as dry etch, RIE (Reactive Ion Etching), or other plasma etching processes.
  • the first oxide layer 32 is etched back to expose the substrate 10 and the top of the gate electrode 14 , leaving oxide spacers 32 a on the sidewalls 15 respectively.
  • horizontal portions of the first oxide layer 32 are etched to expose the substrate 10 and the top of the gate electrode 14 , leaving vertical portions of the first oxide layer 32 laterally adjacent to the gate electrode 14 and the gate dielectric layer 12 .
  • portions of the dielectric spacers 34 are etched to be leveled off with the oxide spacers 32 a , leaving the dielectric spacers 34 a ′′ on the oxide spacers 32 a respectively.
  • the etch back process may use an anisotropic etch process, such as dry etch, RIE (Reactive Ion Etching), or other plasma etching processes.
  • a second oxide layer 36 is selectively formed on the exposed portions of the oxide spacers 32 a , the gate electrode 14 and the substrate 10 .
  • the second oxide layer 36 is selectively grown on the exposed portions of the substrate 10 , the oxide spacers 24 and the gate electrode 14 through an oxidation process to reach a thickness from about 20 Angstroms to about 60 Angstroms.
  • the second oxide layer 36 is preferably made of silicon oxide through the use of a thermal oxidation process. Other suitable dielectric materials may be used in place of silicon oxide, for example high-k dielectric materials, metal oxide materials or any other. oxide-based materials.
  • the second oxide layer 36 is intended to use an oxide material the same as the first oxide layer 32 .
  • the present invention also provides value when the second oxide layer 36 uses an oxide material different from that used in the first oxide layer 32 . Therefore, the combination of the oxide spacer 32 a and the second oxide layer 36 functions as the dual-thickness oxide structure 16 as described in FIG. 1 , wherein the second oxide layer 36 with a relatively thinner thickness disposed on the substrate 10 is for the thinner oxide portion 16 a application, and the oxide spacer 32 a with a relatively thicker thickness disposed along the sidewall 15 is for the thicker oxide portion 16 b application.
  • a second dielectric layer 38 is deposited on the substrate 10 to cover the second oxide layer 36 and the dielectric spacers 34 a ′′.
  • the second dielectric layer 38 is a silicon nitride layer.
  • Other suitable dielectric materials may be used in place of silicon nitride, for example silicon oxynitride, boron nitride, or high-k dielectric materials with a high amount of trap-sites.
  • the second dielectric layer 38 is intended to use a trapping dielectric material the same as the first dielectric layer 34 .
  • the present invention also provides value when the second dielectric layer 38 uses a trapping dielectric material different from that used in the first dielectric layer 34 .
  • the combination of the second dielectric layer 38 and the dielectric spacers 34 a ′′ therefore functions as a trapping dielectric material, which is then patterned as the trapping dielectric spacers 18 laterally adjacent to the sidewalls 15 respectively, as described in FIG. 3F , through advances in lithography and masking techniques and dry etch processes.
  • source/drain regions will be formed in the substrate 10 by implanting ion dopants into the substrate 10 with the trapping dielectric spacers 18 as the implantation mask.
  • the second oxide layer 36 remaining on the top of the gate electrode 14 may be retained or removed, which is not limited in the present invention.

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  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US11/243,165 2005-10-04 2005-10-04 Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same Abandoned US20070075385A1 (en)

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US11/243,165 US20070075385A1 (en) 2005-10-04 2005-10-04 Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same
TW095102589A TWI267201B (en) 2005-10-04 2006-01-24 Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same
CNA2006100649648A CN1945851A (zh) 2005-10-04 2006-03-20 Sonos栅极结构及其形成方法
US12/648,598 US8653576B2 (en) 2005-10-04 2009-12-29 Method of fabricating a SONOS gate structure with dual-thickness oxide

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128789A1 (en) * 2006-12-04 2008-06-05 Hynix Semiconductor Inc. Semiconductor memory device and method of manufacturing the same
US20120146175A1 (en) * 2010-12-09 2012-06-14 Nicolas Loubet Insulating region for a semiconductor substrate
US8796147B2 (en) 2010-12-17 2014-08-05 Stmicroelectronics, Inc. Layer formation with reduced channel loss
US20160027658A1 (en) * 2013-10-25 2016-01-28 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using Multilayer Spacer for Reduced Spacer Footing

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CN101459139B (zh) * 2007-12-10 2010-11-03 上海华虹Nec电子有限公司 电荷囚禁器件的制作工艺方法
CN101483154B (zh) * 2008-01-07 2010-08-25 中芯国际集成电路制造(上海)有限公司 一种双栅氧器件的栅极侧墙制造方法
CN103165615B (zh) * 2011-12-19 2016-01-06 中芯国际集成电路制造(上海)有限公司 分栅快闪存储器及其形成方法
CN104934306B (zh) * 2014-03-18 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件间隙壁的制造方法

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US20040232477A1 (en) * 2003-05-20 2004-11-25 Hiroshi Iwata Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card
US7151293B1 (en) * 2004-08-27 2006-12-19 Spansion, Llc SONOS memory with inversion bit-lines

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232477A1 (en) * 2003-05-20 2004-11-25 Hiroshi Iwata Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card
US7151293B1 (en) * 2004-08-27 2006-12-19 Spansion, Llc SONOS memory with inversion bit-lines

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128789A1 (en) * 2006-12-04 2008-06-05 Hynix Semiconductor Inc. Semiconductor memory device and method of manufacturing the same
US20120146175A1 (en) * 2010-12-09 2012-06-14 Nicolas Loubet Insulating region for a semiconductor substrate
US8796147B2 (en) 2010-12-17 2014-08-05 Stmicroelectronics, Inc. Layer formation with reduced channel loss
US9000491B2 (en) 2010-12-17 2015-04-07 Stmicroelectronics, Inc. Layer formation with reduced channel loss
US20160027658A1 (en) * 2013-10-25 2016-01-28 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using Multilayer Spacer for Reduced Spacer Footing
US9892933B2 (en) * 2013-10-25 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using multilayer spacer for reduced spacer footing

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TWI267201B (en) 2006-11-21
US20100136779A1 (en) 2010-06-03
CN1945851A (zh) 2007-04-11
US8653576B2 (en) 2014-02-18
TW200715573A (en) 2007-04-16

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