TWM678588U - Chip carrier disk - Google Patents

Abstract

A wafer carrier is used to support larger-sized wafers. It includes a bottom and a plurality of first sidewalls and a plurality of second sidewalls respectively arranged around the upper and lower edges of the bottom to form a support groove and a receiving groove. When a wafer is clamped between the two wafer carriers, the wafer position is maintained by generating a plurality of interference portions with the wafer. These interference portions are provided with elastic antistatic materials to position the wafer and prevent the wafer from being damaged.

Description

Chip carrier disk

This invention relates to a chip carrier disk, and more particularly to a carrier disk for holding large-sized chips.

As chips become increasingly larger, robotic arms are frequently used for handling and parallel movement during manufacturing and packaging to prevent breakage due to weight and uneven stress. Existing substrates, mostly made of glass or ceramic, provide basic rigidity, but relative friction still occurs between the chip and substrate surfaces during movement and positioning. Compared to smaller chips, larger chips, with their wider contact area and greater weight, are more prone to slippage and wear during handling, exacerbating the friction problem and increasing the likelihood of debris or particle generation. If these foreign objects adhere to the chip surface or enter the circuit area, they can contaminate subsequent processes, affecting product yield and reliability.

Furthermore, most existing substrates rely solely on planar contact to support the chip, lacking effective fixation and cushioning designs. In applications involving large-size chips, due to their high value, complex circuitry, and stringent yield requirements, once dust or particles are generated and accumulate on the chip surface, they are not only more difficult to remove but also have a wider impact on the circuit area, potentially leading to the scrapping of the entire chip and causing severe economic losses.

Based on the above deficiencies, the purpose of this invention is to provide a chip carrier that overcomes the problems of friction and debris generation when used with a robotic arm to move large chips in parallel.

According to the purpose of this invention, a wafer carrier tray is provided, comprising: a bottom having a plurality of through holes; a plurality of first sidewalls disposed on the upper surface of the bottom, near the periphery of the bottom and forming a support groove with the bottom, each of the first sidewalls having abutting surface, a wafer abutting against the abutting surfaces and positioned above the support groove, the first sidewalls being provided with a plurality of fasteners; and a plurality of second sidewalls disposed on the lower surface of the bottom, near the bottom. The periphery of the wafer carrier and the wafer carrier form a receiving groove corresponding to the support groove. The lower surface of the bottom is provided with a plurality of positioning members located inside the second sidewalls. The two wafer carriers are stacked on top of each other. The wafer is supported in the support groove of the wafer carrier and the receiving groove of the other wafer carrier. The fixing members and/or the positioning members contact the wafer to define a plurality of interference portions. The interference portions are provided with elastic antistatic materials.

The height of these positioning components is greater than the height of these second side walls.

Each of the first side walls also includes two side sections, with the top surface located between the two side sections.

These fasteners are respectively connected to the side near the upper surface of the support groove.

It also includes a plurality of anchors located on the outside of these second side walls.

It also includes a plurality of alignment portions, each of which is disposed on the outer side of each of the first side walls. When the chip carrier tray is stacked on top of another chip carrier tray, the legs abut against the upper surface of the first side walls and are located between the two adjacent alignment portions.

The outer surfaces of the first side walls are each provided with at least one alignment portion. Each column includes a protrusion and a base. When the wafer carrier is stacked on top of another wafer carrier, the base abuts against the upper surface of the alignment portion. The two adjacent protrusions are located between the two alignment portions of the adjacent side walls.

The outer surfaces of the first side walls are provided with a plurality of alignment portions, which are spaced apart to form a plurality of recesses. Each recess contains a stopper. When the wafer carrier is stacked on top of another wafer carrier, each of the legs corresponds to the recess and abuts against the upper surface of the stopper.

The elastic antistatic material of these interference parts is selected from antistatic cotton, antistatic silicone, polyurethane, or other thermoplastic elastomers.

The area of the chip is greater than or equal to 50 x 50 mm.

To clearly illustrate the specific implementation, structure, and effects achieved by this invention, examples and diagrams are provided below:

Please refer to Figures 1 and 2, which illustrate a chip carrier 10, including a bottom 11 with a plurality of through holes 112. A plurality of first sidewalls 12 are provided around the periphery of the upper surface of the bottom 11, forming a support groove 13 with the bottom 11. A plurality of second sidewalls 14 are provided around the periphery of the lower surface of the bottom 11, forming a receiving groove 15 with the bottom 11. After the two chip carrier platters 10 are stacked together, the adjacent support grooves 13 and receiving grooves 15 correspond to each other to form a space for accommodating a chip 20. Each of the first side walls 12 has a top surface 121. In this embodiment, the top surfaces 121 are inclined surfaces. The periphery of the chip 20 abuts against the top surfaces 121 with a small area, so that most of the surface of the chip 20 does not contact the chip carrier platters 10.

Please continue to refer to FIG. 3 , which is a partially enlarged view of the first embodiment of the present invention. In order to prevent the chip 20 from rubbing against the wafer carrier 10 , a plurality of positioning members 111 are provided on the lower surface of the bottom 11 . Each positioning member 111 uses gravity to exert downward force to contact the wafer 20 to define an interference portion A, and the The interference part A is provided with an elastic antistatic material, which may be but is not limited to antistatic cotton, antistatic silicone, polyurethane, or other thermoplastic elastomers, to position the wafer 20 and prevent the wafer 20 from being displaced and causing friction when the robot arm clamps the wafer carrier 10 and moves it in parallel, and at the same time avoids damage to the wafer or microcircuit. In this embodiment, the surface area of the chip 20 is 50 x 50 mm, but is not limited thereto, and the height of the positioning members 111 is greater than the height of the second side walls 14, so that the interference portions A generate sufficient downward pressure to reinforce the chip 20.

In a preferred embodiment, each first side wall 12 further includes two side portions 122 , and the top surface 121 is provided between the two side portions 122 . A fixing member 122 a is connected to the side portion 122 close to the upper surface of the first side wall 12 , wherein the width of the fixing members 122 a is larger than that of the chip 20 and the side portion 1 The distance between the fasteners 122a and the wafer 20 creates a plurality of interference portions B, and the interference portions B are provided with elastic antistatic materials, which can be but are not limited to antistatic cotton, antistatic silicone, polyurethane, or other thermoplastic elastomers to prevent the wafers 20 from shaking horizontally and avoid damage to the wafer or microcircuit.

To further explain, the outer side of the second side wall 14 is provided with a plurality of feet 141, which abut against the upper surface of the first side walls 12 when the two chip carrier disks 10 are stacked. In other embodiments, each of the first sidewalls 12 is further provided with a plurality of alignment portions 123 spaced apart from each other. Each foot 141 includes a protrusion 141a and a base 141b. The protrusion 141a extends downward from the upper surface of the base 141b. When the two wafer carrier trays 10 are stacked, the two protrusions 141a, which are adjacent to each other but located on different second sidewalls 14, are limited between the two alignment portions 123. The two alignment portions 123 are adjacent to each other but located on different first sidewalls 12, and the bases 141b abut against the upper surfaces of the alignment portions 123 to stabilize the two stacked wafer carrier trays 10.

Next, please refer to Figures 4 to 6, which illustrate the second embodiment of the invention. The chip 20 has an area of 93 x 93 mm and is also sandwiched between the two chip carriers 10. The difference from the first embodiment is that the abutment surfaces 121 are parallel to the bottom 11, and the alignment portions 123 are spaced apart to form a plurality of recesses 124. Each recess 124 has a stop 124a, and the legs 141 are inserted into the recesses 124 and abut against the upper surface of the stop 124a.

To further explain, the surfaces of the positioning members 111 and the fixing members 122a are made of elastic and antistatic material, which may be but not limited to silicone, polyurethane or other thermoplastic elastomers with antistatic properties.

Accordingly, the wafer carrier 10 of this invention provides a stable support for larger wafers 20, especially during stacking and parallel movement by a robotic arm, preventing the wafers 20 from rubbing against the wafer carrier 10 and generating debris and dust. Furthermore, the matching contours of the first sidewalls 12 and the second sidewalls 14 make the stacking structure of the wafer carrier 10 more stable, improving the overall process yield of large-size wafers and reducing consumable costs.

10: Wafer carrier plate 11: Bottom 111: Positioning element 112: Through hole 12: First side wall 121: Top surface 122: Side 122a: Fixing element 123: Alignment part 124: Recess 124a: Stopping element 13: Support groove 14: Second side wall 141: Foot 141a: Protrusion 141b: Base 15: Receiving groove 20: Wafer A,B: Interference part 2-2,6-6: Section lines

Figure 1 is a schematic diagram of the first embodiment of the chip carrier disk of this invention.

Figure 2 is a cross-sectional view of the first embodiment of the chip carrier disk of this invention.

Figure 3 is a partially enlarged cross-sectional view of the first embodiment of the chip carrier disk of this invention.

Figure 4 is a schematic diagram of a second embodiment of the chip carrier disk of this invention.

Figure 5 is a cross-sectional view of a second embodiment of the chip carrier disk of this invention.

Figure 6 is a partially enlarged cross-sectional view of a second embodiment of the chip carrier disk of this invention.

10: Chip Carrier Disk

11: Bottom

112: Through hole

12: First side wall

123: Opposing part

13: Support groove

141: Foot Pillar

141a:convex part

141b: Base

2-2: Section Lines

Claims (10)

A chip carrier tray includes: a bottom having a plurality of through holes; a plurality of first sidewalls disposed on the upper surface of the bottom, near the periphery of the bottom and forming a support groove with the bottom, each of the first sidewalls having abutting surface, a chip abutting against the abutting surfaces and positioned above the support groove, the first sidewalls being provided with a plurality of fixing members; and a plurality of second sidewalls disposed on the lower surface of the bottom, near the periphery of the bottom and forming a receiving groove therewith, the receiving groove corresponding to the support groove, the lower surface of the bottom being provided with a plurality of positioning members, the positioning members being positioned inside the second sidewalls; When two wafer carriers are stacked together, the wafer is supported in the support groove of one wafer carrier and the receiving groove of the other wafer carrier. The fixing members and/or the positioning members contact the wafer to define a plurality of interference portions, and the interference portions are provided with elastic antistatic materials. The chip carrier as described in claim 1, wherein the height of the positioning elements is greater than the height of the second sidewalls. The chip carrier disk as described in claim 1, wherein each of the first sidewalls further includes two sides, and the abutment surface is disposed between the two sides. The wafer carrier as described in claim 3, wherein the fasteners are respectively connected to the side near the upper surface of the support groove. The chip carrier as described in claim 1 further includes a plurality of feet disposed on the outer side of the second sidewalls. The chip carrier as described in claim 5 further includes a plurality of alignment portions, each of which is disposed on the outer surface of each of the first side walls. When the chip carrier is stacked on top of another chip carrier, the legs abut against the upper surface of the first side walls and are located between adjacent alignment portions. As described in claim 6, the outer surfaces of the first sidewalls are each provided with at least one alignment portion. The legs include a protrusion and a base. When the chip carrier is stacked on top of another chip carrier, the base abuts against the upper surface of the alignment portion, and the two adjacent protrusions are located between the two alignment portions of the adjacent sidewalls. As described in claim 6, the outer surfaces of the first sidewalls are provided with a plurality of alignment portions, which are spaced apart to form a plurality of recesses. Each recess contains a stop member. When the wafer carrier is stacked on top of another wafer carrier, each of the legs corresponds to the recess and abuts against the upper surface of the stop member. The wafer carrier disk as described in any one of claims 1 to 8, wherein the elastic antistatic material of the interference portions is selected from antistatic cotton, antistatic silicone, polyurethane, or other thermoplastic elastomers. The chip carrier as described in claim 9, wherein the area of the chip is greater than or equal to 50 x 50 mm.