TWM677995U - High-speed level shifting circuit - Google Patents

Abstract

This invention proposes a high-speed potentiometer circuit, which comprises an input circuit (1), a latching circuit (2), a clock input transistor (3), a clock input transistor (4), and a clock input transistor (5). The input circuit (1) provides a differential input signal; the latching circuit (2) serves as the output potential for storage conversion; the clock input transistor (3) raises the potential of the first node (N1); the clock input transistor (4) raises the potential of the second node (N2); and the clock input transistor (5) lowers the potential of the third node (N3).

The high-speed potentiometer circuit proposed in this invention can not only quickly convert a first signal into a second signal, but also effectively reduce power consumption.

Description

High-speed potentiometer circuit

This invention proposes a high-speed potentiometer circuit, which consists of an input circuit (1), a latching circuit (2), a clock input transistor (3), a clock input transistor (4), and a clock input transistor (5), aiming to achieve rapid and accurate voltage level conversion while effectively reducing power consumption.

A potentiometer is an electronic circuit used to communicate signals between different integrated circuits (ICs). In many applications, when a system needs to transmit signals from a core logic circuit with a lower voltage level to a peripheral device with a higher voltage level, the potentiometer is responsible for converting low-voltage operating signals to high-voltage operating signals.

Figure 1 shows a prior art latch-up potentiometer circuit, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) to form a potentiometer circuit. The inverter (INV) is biased between a second high potential voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. Therefore, at any given time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be on. Furthermore, due to the cross-coupled nature of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), no static current is generated in the latch-up potentiometer when the output (OUT) of the potentiometer is in a stable state. Specifically, when the first NMOS transistor (MN1) is off and the second NMOS transistor (MN2) is on, the gate potential of the first PMOS transistor (MP1) is pulled down, causing the first PMOS transistor (MP1) to conduct, which in turn pulls up the gate potential of the second PMOS transistor (MP2) and turns off the second PMOS transistor (MP2); furthermore, when the first NMOS transistor (MN1) is on and the second NMOS transistor (MN2) is off, the gate potential of the second PMOS transistor (MP2) is pulled down, causing the second PMOS transistor (MP2) to conduct, which in turn pulls up the gate potential of the first PMOS transistor (MP1) and turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1), or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the conventional potential converter described above, during the process of the second PMOS transistor (MP2) approaching turn-on (or turn-off) and the second NMOS transistor (MN2) approaching turn-off (or turn-on), there is a contention phenomenon in the potential rise and fall at the output terminal (OUT). Therefore, the second signal (V(OUT)) transitions to a low potential more slowly. Furthermore, considering that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) turns on, and the gate of the second PMOS transistor (MP2) becomes low, causing the second PMOS transistor (MP2) to turn on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be instantaneously switched to 1.8 volts, the lower first signal (V(IN)) during the switching period may not be able to fully turn on or off the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and the second NMOS transistor (MN2). This results in a static current between the first high potential voltage (VDDH) and ground (GND), which increases power loss.

Furthermore, the performance of a latch-up potentiometer is affected by the first high potential voltage (VDDH). Since the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is the first high potential voltage (VDDH), while the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high potential voltage (VDDL), the range of the first high potential voltage (VDDH) that allows the latch-up potentiometer to operate normally is limited.

Figure 2 shows a mirror-type potentiometer circuit, a prior art technique. This potentiometer connects the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together to the drain of the first PMOS transistor (MP1), forming a current mirror circuit. The first PMOS transistor (MP1) is in its saturation region, and its gate voltage ensures that the saturation current is equal to the current flowing into the first NMOS transistor (MN1). The currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of a mirror-type potentiometer is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), the performance of the potentiometer will not change significantly even if the first high potential voltage (VDDH) of the output changes. Therefore, mirror-type potentiometers can be used in various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, causing both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) to turn on. This creates a quiescent current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

Given the competition for potentials at the output terminals of latch-up potentiometers, the main objective of this invention is to propose a high-speed potentiometer circuit that can accurately and quickly convert a first signal into a second signal while effectively reducing power consumption.

This invention proposes a high-speed potentiometer circuit, which comprises an input circuit (1), a latching circuit (2), a clock input transistor (3), a clock input transistor (4), and a clock input transistor (5). The input circuit (1) provides a differential input signal; the latching circuit (2) serves as the output potential for storage conversion; the clock input transistor (3) raises the potential of the first node (N1); the clock input transistor (4) raises the potential of the second node (N2); and the clock input transistor (5) lowers the potential of the third node (N3).

Simulation results confirm that the high-speed potentiometer circuit proposed in this invention can not only accurately and quickly convert a first signal into a second signal, but also has multiple advantages such as simple circuit structure and advantages for device miniaturization, while effectively reducing power loss.

1: Input Circuit

2: Lockout Circuit

3: Clock input transistor

4: Clock Input Transistor

5: Clock input transistor

N1: First node

N2: Second node

N3: Third node

MP1: First PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

I1: First inverter

MN1: First NMOS transistor

MN2: Second NMOS transistor

MN3: Third NMOS transistor

MN4: Fourth NMOS transistor

MN5: Fifth NMOS transistor

CK: Clock Input

GND: Earth

V(IN): First signal

IN: First input terminal

OUT: Output terminal

V(OUT): Second signal

V(OUTB): Inverted second signal

OUTB: Inverting output terminal

INB: Second Input Terminal

VDDL: Second highest power supply voltage

VDDH: Highest power supply voltage

Figure 1 is a circuit diagram showing a potential converter in a first prior art; Figure 2 is a circuit diagram showing a potential converter in a second prior art; Figure 3 is a circuit diagram showing a high-speed potential converter circuit of a preferred embodiment of the present invention;

In accordance with the above objectives, this invention proposes a high-speed potentiometer circuit, as shown in Figure 3, which consists of an input circuit (1), a latching circuit (2), a clock input transistor (3), a clock input transistor (4), and a clock input transistor (5). The input circuit (1) is used to provide a differential input signal; the latching circuit (2) is used to store the output potential of the switch; and the clock input transistor (3) is used to raise the potential of the first node (N1). The clock input transistor (4) is used to raise the potential of the second node (N2); the clock input transistor (5) is used to lower the potential of the third node (N3); the input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the third node (N3), and its gate is connected to the first input terminal (IN), and its The drain is connected to the source of the third NMOS transistor (MN3); the source of the second NMOS transistor (MN2) is connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the fourth NMOS transistor (MN4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V(IN)) and provide the inverse signal of the first signal (V(IN)); the latching circuit... Circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4). The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node (N1). The source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node (N1). The first high power supply voltage (VDDH) is connected to the first node (N1), and its drain is connected to the second node (N2); the source of the third NMOS transistor (MN3) is connected to the drain of the first NMOS transistor (MN1), its gate is connected to the second node (N2), and its drain is connected to the first node (N1); the source of the fourth NMOS transistor (MN4) is connected to the drain of the second NMOS transistor (MN2). The clock input transistor (3) is composed of a third PMOS transistor (MP3), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the clock input terminal (CK), and whose drain is connected to the first node (N1); the clock input transistor (4) is composed of a fourth PMOS transistor (MP4), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the clock input terminal (CK), and whose drain is connected to the first node (N1); A first high power supply voltage (VDDH) is connected to the clock input terminal (CK) at its gate, and its drain is connected to the second node (N2). This first high power supply voltage (VDDH) provides the first high power supply voltage required by the high-speed potentiometer circuit. A second high power supply voltage (VDDL) provides the second high power supply voltage required by the high-speed potentiometer circuit. The level of the second high power supply voltage (VDDL) is lower than that of the first high power supply voltage. The voltage levels (VDDH) are as follows: the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts. The first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts. The first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again. When the clock input (CK) is at a logical low level, the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are turned on, the fifth NMOS transistor (MN5) is turned off, and the output (OUT) and the inverting output (OUTB) are pre-charged to the first high power supply voltage (VDDH). When the clock input (CK) rises from a logical low level to a logical high level, the fifth NMOS transistor (MN5) is turned on, and the potential converter circuit is activated. Now consider the steady-state operation of the high-speed potentiometer circuit when the first signal (V(IN)) is at a logically low level (0 volts): the logically low level at the first input (IN) is simultaneously transmitted to the gate of the first NMOS transistor (MN1) and the input of the first inverter (I1), causing the first NMOS transistor (MN1) to be off. Meanwhile, the first inverter (I1) transmits a logically high level (VDDL) to the gate of the second NMOS transistor (MN2), causing the second NMOS transistor (MN2) to be on. Due to the logically high level at the first node (N1), the fourth NMOS transistor (MN4) is on, and the second PMOS transistor (MP2) is off. When the first node (N1) is turned off, the second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are also turned on. Therefore, the potential of the second node (N2) is pulled down to a logically low level (0 volts) and output from the output terminal (OUT). The logically low level of the second node (N2) causes the first PMOS transistor (MP1) to turn on and the third NMOS transistor (MN3) to turn off. At this time, because the first PMOS transistor (MP1) is turned on, the potential of the first node (N1) will remain at a logically high level and output from the inverting output terminal (OUTB). That is, the potential of the output terminal (OUT) will remain at a logically low level (0 volts) in a steady state. In short, when the first signal (V(IN)) is at a logically low level (0 volts), it is converted into a second signal with a logically low level (0 volts) by a high-speed potentiometer circuit and output from the output terminal (OUT).

Considering the steady-state operation of the high-speed potentiometer circuit when the first signal (V(IN)) is at a logical high level (VDDL): the logical high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1) and the gate of the first NMOS transistor (MN1), causing the first NMOS transistor (MN1) to be turned on (ON). Meanwhile, the first inverter (I1) transmits a logical low level to the gate of the second NMOS transistor (MN2), causing the second NMOS transistor (MN2) to be turned off (OFF). At this time, due to the logical high level of the second node (N2), the third NMOS transistor (MN3) is turned on (ON). Because the first NMOS transistor (MN1) and the fifth... When all NMOS transistors (MN5) are turned on, the potential of the first node (N1) is pulled down to a logically low level (0 volts) and output from the inverting output terminal (OUTB). The logically low level of the first node (N1) causes the second PMOS transistor (MP2) to be turned on, and the fourth NMOS transistor (MN4) to be turned off. At this time, since the second PMOS transistor (MP2) is turned on, and the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off, the potential of the second node (N2) is pulled up to a logically high level and output from the output terminal (OUT). Therefore, the potential of the output terminal (OUT) will maintain a steady value at a logically high level. In short, when the first signal (V(IN)) is at a logically high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) by a high-speed potentiometer circuit and output from the output terminal (OUT).

In summary, when the first signal (V(IN)) is at a logically low level (0 volts), the second signal (V(OUT)) is also at a logically low level (0 volts); and when the first signal (V(IN)) is at a logically high level (VDDL), the second signal (V(OUT)) represents the first high power supply voltage (VDDH). Thus, the purpose of voltage level conversion is achieved.

The high-speed potentiometer circuit proposed in this work, as verified by Spice transient analysis simulation results, can not only quickly and accurately convert a first signal into a second signal, but also effectively reduce power loss.

While this invention specifically discloses and describes the chosen best embodiments, it will be apparent to anyone skilled in the art that any possible variations in form or detail do not depart from the spirit and scope of this invention. Therefore, all modifications within the relevant art scope are included within the scope of this patent application.

1: Input Circuit

2: Lockout Circuit

3: Clock input transistor

4: Clock Input Transistor

5: Clock input transistor

N1: First node

N2: Second node

N3: Third node

MP1: First PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

I1: First inverter

MN1: First NMOS transistor

MN2: Second NMOS transistor

MN3: Third NMOS transistor

MN4: Fourth NMOS transistor

MN5: Fifth NMOS transistor

CK: Clock Input

GND: Earth

IN: First input terminal

V(IN): First signal

OUT: Output terminal

V(OUT): Second signal

OUTB: Inverting output terminal

V(OUTB): Inverted second signal

INB: Second Input Terminal

VDDL: Second highest power supply voltage

VDDH: Highest power supply voltage

Claims (8)

A high-speed potentiometer circuit for converting a first signal (V(IN)) into a second signal (V(OUT)) includes: a first node (N1) for connecting the drains of a first PMOS transistor (MP1), a third PMOS transistor (MP3), and a third NMOS transistor (MN3) together; a second node (N2) for connecting the drains of a second PMOS transistor (MP2), a fourth PMOS transistor (MP4), and a fourth NMOS transistor (MN4) together; and a third node (N3) for connecting the sources of a first NMOS transistor (MN1) and a second NMOS transistor (MN2) together. The drains of a fifth NMOS transistor (MN5) are connected together; a first input terminal (IN) is coupled to the gate of the first NMOS transistor (MN1) and the input terminal of a first inverter (I1) to provide a first signal (V(IN)); a second input terminal (INB) is coupled to the gate of the second NMOS transistor (MN2) and the output terminal of the first inverter (I1) to provide the inverted signal (V(INB)) of the first signal (V(IN)); an output terminal (OUT) is coupled to the second node (N2) to output the second signal (V(OUT)); an inverted output terminal (OUTB) is coupled to the first node (N1) to output the second signal (V(OUT)). The inverse signal of two signals (V(OUT)); a first high power supply voltage (VDDH), coupled to the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4), to provide the first high power supply voltage required by the potential converter circuit; a second high power supply voltage (VDDL), coupled to the source of the first inverter (I1), to provide the second high power supply voltage required by the potential converter circuit, the potential of the second high power supply voltage (VDDL) being less than the potential of the first high power supply voltage (VDDH); an input circuit (1), coupled to the first An input terminal (IN) is provided to provide a differential input signal; a latching circuit (2), coupled to the first high power supply voltage (VDDH) and the input circuit (1), is used as an output potential for storage conversion; a clock input transistor (3), coupled to the first high power supply voltage (VDDH) and the first node (N1), is used to raise the potential of the first node (N1); a clock input transistor (4), coupled to the first high power supply voltage (VDDH) and the second node (N2), is used to raise the potential of the second node (N2); and a clock input terminal (CK), coupled to the gate of the clock input transistors, is used to receive a clock signal generated by an external clock generating circuit. The high-speed potentiometer circuit as described in claim 1, wherein the input circuit (1) comprises: a first NMOS transistor (MN1) with its source connected to the third node (N3), its gate connected to the first input terminal (IN), and its drain connected to the source of the third NMOS transistor (MN3); a second NMOS transistor (MN2) with its source connected to the third node (N3), its gate connected to the second input terminal (INB), and its drain connected to the source of the fourth NMOS transistor (MN4); and a first inverter (I1) coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal inverted from the first signal (V(IN)). As described in claim 2, the high-speed potentiometer circuit, wherein the latching circuit (2) comprises: a first PMOS transistor (MP1) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the second node (N2), and whose drain is connected to the first node (N1); and a second PMOS transistor (MP2) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the first node (N1), and whose drain is connected to the first node (N1). The first NMOS transistor (MN1) is connected to the second node (N2); a third NMOS transistor (MN3) has its source connected to the drain of the first NMOS transistor (MN1), its gate connected to the second node (N2), and its drain connected to the first node (N1); and a fourth NMOS transistor (MN4) has its source connected to the drain of the second NMOS transistor (MN2), its gate connected to the first node (N1), and its drain connected to the second node (N2). The second NMOS transistor (MN3) is connected to the second node (N2). As described in claim 3, the high-speed potentiometer circuit comprises a third PMOS transistor (MP3) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the clock input terminal (CK), and whose drain is connected to the first node (N1). As described in claim 4, the high-speed potentiometer circuit, wherein the clock input transistor (4) is composed of a fourth PMOS transistor (MP4), the source of which is connected to the first high power supply voltage (VDDH), the gate of which is connected to the clock input terminal (CK), and the drain of which is connected to the second node (N2). As described in claim 1, the high-speed potentiometer circuit wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). As described in claim 6, the high-speed potentiometer circuit wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). As described in claim 2, the high-speed potentiometer circuit, wherein the voltage source of the first inverter (I1) is the second high-power supply voltage (VDDL).