TWM673160U - Voltage level shifter with leakage current suppression - Google Patents

Abstract

This invention proposes a potential converter with leakage current suppression, comprising an input circuit, a latch circuit, a level shift circuit, a first current suppression circuit, and a second current suppression circuit. The input circuit is used to provide a differential input signal; the latch circuit is used to store and output the differential input signal; the level shift circuit is used to change the level of the signal output from the latch circuit to output the second signal; the first current suppression circuit is used to suppress current flowing into the level shift circuit; and the second current suppression circuit is used to suppress current flowing into the latch circuit.

The potential converter with leakage current suppression proposed in this invention not only accurately converts a first signal into a second signal, but also boasts multiple benefits, including a simple circuit structure and favorable device miniaturization. It also effectively suppresses competition between the pull-up and pull-down paths, thereby reducing power loss.

Description

Potential converter with leakage current suppression

This invention proposes a potential converter with leakage current suppression, specifically an electronic circuit composed of an input circuit (1), a latch circuit (2), a potential shift circuit (3), a first current suppression circuit (4) and a second current suppression circuit (5), in order to obtain accurate voltage level conversion while effectively reducing power loss.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (ICs). In many applications, when the application system needs to transmit signals from the lower-voltage core logic to the higher-voltage peripheral devices, the potential converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

FIG. 1 shows a mirror-type potential converter circuit of another prior art. The potential converter forms a current mirror circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and connected to the drain of the first PMOS transistor (MP1). The first PMOS transistor (MP1) is in a saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1). The currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Because the performance of a mirror-type potential converter is determined by the currents flowing through the first PMOS transistor (MP1) and the first NMOS transistor (MN1), the performance of the potential converter remains largely unchanged even if the output first high power supply voltage (VDDH) changes. Therefore, the mirror-type potential converter is applicable to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, causing both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) to be turned on. Thus, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

FIG2 shows a prior art latch-type potential converter circuit, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) to form a potential converter circuit. The inverter (INV) is biased between the second high power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. Therefore, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is turned on at any one time. Furthermore, due to the cross-coupling of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), no static current is generated in the latch-type potential converter when the output (OUT) of the potential converter is in a stable state. In particular, when the first NMOS transistor (MN1) is off (OFF) and the second NMOS transistor (MN2) is on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down, causing the first PMOS transistor (MP1) to conduct, thereby pulling up the gate potential of the second PMOS transistor (MP2) and turning off the second PMOS transistor (MP2); further, when the first NMOS transistor (MN1) is on and the second NMOS transistor (MN2) is off, the gate potential of the second PMOS transistor (MP2) is pulled down, causing the second PMOS transistor (MP2) to conduct, thereby pulling up the gate potential of the first PMOS transistor (MP1) and turning off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the conventional potential converter, when the second PMOS transistor (MP2) approaches turning on (or off) and the second NMOS transistor (MN2) approaches turning off (or on), there is a competition between the raising and lowering of the potential at the output terminal (OUT). As a result, the second signal (V(OUT)) transitions to a low potential at a slower rate. Furthermore, when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) turns on, and the gate of the second PMOS transistor (MP2) becomes low, turning on the second PMOS transistor (MP2). Therefore, the output is a first high power supply voltage (VDDH). However, because 0 volts cannot instantly transition to 1.8 volts, the low first signal (V(IN)) during the transition period may not fully turn on or off the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and the second NMOS transistor (MN2). This causes a static current to flow between the first high power supply voltage (VDDH) and ground (GND), increasing power loss.

Furthermore, the performance of a latch-type potential converter is affected by the first high power supply voltage (VDDH). Since the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is the first high power supply voltage (VDDH), while the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL), the range of the first high power supply voltage (VDDH) within which the latch-type potential converter can operate normally is limited. As the second PMOS transistor (MP2) approaches turning on (or off) and the second NMOS transistor (MN2) approaches turning off (or on), there is competition between the raising and lowering of the potential at the output terminal (OUT). Therefore, the second signal (V(OUT)) transitions to a low potential more slowly.

In light of this, the primary objective of this invention is to propose a potential converter with leakage current suppression. This converter not only accurately and quickly converts a first signal into a second signal, but also effectively reduces competition between the pull-up and pull-down paths, thereby reducing power loss.

This invention proposes a potential converter with leakage current suppression, which is composed of an input circuit (1), a latch circuit (2), a potential shift circuit (3), a first current suppression circuit (4) and a second current suppression circuit (5), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store and output the differential input signal; the potential shift circuit (3) is used to change the signal potential output from the latch circuit (2) to output the second signal (V(OUT)); the first current suppression circuit (4) is used to suppress current from flowing into the potential shift circuit (3); and the second current suppression circuit (5) is used to suppress current from flowing into the latch circuit (2).

Simulation results confirm that the leakage current-suppressing potential converter proposed in this invention not only accurately and quickly converts a first signal into a second signal, but also boasts multiple benefits, including a simple circuit structure and facilitates device miniaturization, while also effectively reducing power consumption.

1: Input circuit

2: Latch circuit

3: Potential shift circuit

4: First current suppression circuit

5: Second current suppression circuit

GND: Ground

N1: First node

N2: Second Node

N3: Third Node

N4: Fourth Node

N5: Fifth Node

N6: Node 6

N7: Seventh Node

MP1: First PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MP6: Sixth PMOS transistor

MN1: First NMOS transistor

MN2: Second NMOS transistor

MN3: Third NMOS transistor

MN4: Fourth NMOS transistor

I1: First inverter

EN: Mode Control Terminal

OUT: Output port

V(OUT): Second signal

IN: First input terminal

INB: Second input terminal

V(IN): First signal

VDDH: First high power supply voltage

VDDL: Second highest power supply voltage

Figure 1 shows a circuit diagram of a potential converter in a first prior art; Figure 2 shows a circuit diagram of a potential converter in a second prior art; and Figure 3 shows a circuit diagram of a potential converter with leakage current suppression in a preferred embodiment of the present invention.

According to the above-mentioned purpose, the present invention proposes a potential converter with leakage current suppression, as shown in FIG3 , which is composed of an input circuit (1), a latch circuit (2), a potential shift circuit (3), a first current suppression circuit (4) and a second current suppression circuit (5), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store and output the differential input signal; the potential shift circuit (3) is used to change the signal potential output from the latch circuit (2) to output the second signal (V(OUT) ); the first current suppression circuit (4) is used to suppress the current from flowing into the potential shift circuit (3); and the second current suppression circuit (5) is used to suppress the current from flowing into the latch circuit (2); the input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the fifth node (N5), the gate thereof is connected to the first input terminal (IN), and the drain thereof is connected to the third node (N3) The source of the second NMOS transistor (MN2) is connected to the fifth node (N5), the gate thereof is connected to the second input terminal (INB), and the drain thereof is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V(IN)) and provide a signal inverted to the first signal (V(IN)); the latch circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4). P3) and a fourth PMOS transistor (MP4), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), the gate thereof is connected to the fourth node (N4), and the drain thereof is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), the gate thereof is connected to the third node (N3), and the drain thereof is connected to the second node (N2); the third PMOS transistor (MP3) is connected to the The source is connected to the first node (N1), the gate is connected to the first input terminal (IN), and the drain is connected to the third node (N3); the source of the fourth PMOS transistor (MP4) is connected to the second node (N2), the gate is connected to the second input terminal (INB), and the drain is connected to the fourth node (N4); the potential shift circuit (3) is composed of a sixth PMOS transistor (MP6) and a third NMOS transistor (MN3), the source of the sixth PMOS transistor (MP6) is connected to the The sixth node (N6) has a gate connected to the third node (N3) and a drain connected to the seventh node (N7); the source of the third NMOS transistor (MN3) is connected to the ground (GND), the gate is connected to the second input terminal (INB), and the drain is connected to the seventh node (N7); the first current suppression circuit (4) is composed of a fifth PMOS transistor (MP5), the source of which is connected to the first high power supply voltage (VDDH), the gate of which is connected to the second input terminal (INB), and the drain of which is connected to the The sixth node (N6) is connected to the second current suppression circuit (5); the second current suppression circuit (5) is composed of a fourth NMOS transistor (MN4), the source of which is connected to the ground (GND), the gate of which is connected to the mode control terminal (EN), and the drain of which is connected to the fifth node (N5); the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the potential converter; the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the potential converter with leakage current suppression; the second high power supply voltage ( The level of the first high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH); the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts. The first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts. The first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again. When the signal of the mode control terminal (EN) is at a logical high level, the fourth NMOS transistor (MN4) is turned on, and the potential converter is in the active state. Now consider the stable operation of the potential converter with leakage current suppression when the first signal (V(IN)) is at a logical low level (0 volts): the logical low level on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the first NMOS transistor (MN1), and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN4) is turned on. The MOS transistor (MN1) is turned off (OFF), the third PMOS transistor (MP3) is turned on (ON), and the first inverter (I1) transmits a logic high level (VDDL) to the gates of the second NMOS transistor (MN2), the third NMOS transistor (MN3) and the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) and the third NMOS transistor (MN3) are turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). At this time, due to the second PMOS transistor (MN2), the third NMOS transistor (MN3) is turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). The first PMOS transistor (MP1) and the fourth PMOS transistor (MP4) are both turned off (OFF), while the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on (ON). The potential of the fourth node (N4) is pulled down to a logical low level (0 volts), and the logical low level on the fourth node (N4) is transmitted to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on (ON). At this time, since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned on ( The first NMOS transistor (MN1) is turned off, and the potential of the third node (N3) is pulled up to a logically high level. The logically high level of the third node (N3) causes the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) to be turned off. Since the third NMOS transistor (MN3) is turned on, the potential of the seventh node (N7) is pulled down to a logically low level (0 volts), and the potential of the output terminal (OUT) is maintained at a stable value of a logically low level (0 volts). In essence, when the first signal (V(IN)) is at a logically low level (0 volts), it is converted into a second signal at a logically low level (0 volts) by a potential converter with leakage current suppression, and then output from the output terminal (OUT).

Considering the stable operation of the potential converter with leakage current suppression when the first signal (V(IN)) is a logical high level (VDDL), the logical high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the first NMOS transistor (MN1) and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned on (ON) and the third PMOS transistor (MP3) is turned off (OFF), and the first inverter (I1) transmits a logical low level to the second NMOS transistor (MN2), the third The gates of the NMOS transistor (MN3), the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are connected, so that the second NMOS transistor (MN2) and the third NMOS transistor (MN3) are turned off (OFF), and the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are turned on (ON). At this time, since the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are turned on (ON), and the third PMOS transistor (MP3) is turned off (OFF), the potential of the third node (N3) is The third node (N3) is pulled down to a logical low level. The logical low level on the third node (N3) is transmitted to the gates of the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6), causing the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) to be turned on. At this time, since the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned on, the potential of the fourth node (N4) is pulled up to a logical high level. The logical high level of the fourth node (N4) causes the first PMOS transistor (MP1) to be turned off. ), at this time, since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned off (OFF), and the first NMOS transistor (MN1) is turned on (ON), the potential of the third node (N3) will be maintained at a logical low level. At this time, since the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both turned on (ON), and the third NMOS transistor (MN3) is turned off (OFF), the potential of the seventh node (N7) will be pulled up to a logical high level, and a logical high level stable value is output from the output terminal (OUT). In essence, when the first signal (V(IN)) is at a logically high level (VDDL), it is converted into a second signal at a first high power supply voltage (VDDH) by a voltage converter with leakage current suppression, and then output from the output terminal (OUT).

Please refer to Figure 3 again. When the signal at the mode control terminal (EN) is at a logical low level, the fourth NMOS transistor (MN4) is turned off, and the potential converter is in standby mode. The operating principle will not be described here.

In summary, when the first signal (V(IN)) is at a logically low level (0 volts), the second signal (V(OUT)) is also at a logically low level (0 volts). Conversely, when the first signal (V(IN)) is at a logically high level (VDDL), the second signal (V(OUT)) is at the first high power supply voltage (VDDH). This achieves the purpose of voltage level conversion.

The potential converter with leakage current suppression proposed in this invention has been verified through Spice transient analysis simulation results. It not only can quickly and accurately convert a first signal into a second signal, but also effectively reduces competition between the pull-up and pull-down paths at the output terminal (OUT), thereby reducing power loss.

While this invention particularly discloses and describes selected preferred embodiments, those skilled in the art will readily appreciate that variations in form and detail are possible without departing from the spirit and scope of this invention. Therefore, all modifications within the relevant technical scope are intended to be included within the scope of the patent application for this invention.

1: Input circuit

2: Latch circuit

3: Potential shift circuit

4: First current suppression circuit

5: Second current suppression circuit

GND: Ground

N1: First node

N2: Second Node

N3: Third Node

N4: Fourth Node

N5: Fifth Node

N6: Node 6

N7: Seventh Node

MP1: First PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MP6: Sixth PMOS transistor

MN1: First NMOS transistor

MN2: Second NMOS transistor

MN3: Third NMOS transistor

MN4: Fourth NMOS transistor

I1: First inverter

EN: Mode Control Terminal

OUT: Output port

V(OUT): Second signal

IN: First input terminal

INB: Second input terminal

V(IN): First signal

VDDH: First high power supply voltage

VDDL: Second highest power supply voltage

Claims (9)

A potential converter with leakage current suppression is used to convert a first signal (V(IN)) into a second signal (V(OUT)), which includes: a first node (N1) for connecting the drain of a first PMOS transistor (MP1) and the source of a third PMOS transistor (MP3); a second node (N2) for connecting the drain of a second PMOS transistor (MP2) and the source of a fourth PMOS transistor (MP3); The sources of the MOS transistors (MP4) are connected together; a third node (N3) is used to connect the gate of the second PMOS transistor (MP2), the drain of the third PMOS transistor (MP3) and the drain of a first NMOS transistor (MN1); a fourth node (N4) is used to connect the gate of the first PMOS transistor (MP1) and the drain of the fourth PMOS transistor (MP4) together. and a drain of a second NMOS transistor (MN2) are connected together; a fifth node (N5) is used to connect the source of the first NMOS transistor (MN1), the source of the second NMOS transistor (MN2) and the drain of a fourth NMOS transistor (MN4) together; a sixth node (N6) is used to connect the drain of a fifth PMOS transistor (MP5) and a sixth PMOS transistor The source of the sixth PMOS transistor (MP6) is connected together; a seventh node (N7) is used to connect the drain of the sixth PMOS transistor (MP6) and the drain of a third NMOS transistor (MN3) together; a first input terminal (IN) is coupled to the gate of the first NMOS transistor (MN1) and the third PMOS transistor (MP3) to provide the first signal (V(IN)); a second input terminal ( INB), coupled to the gates of the second NMOS transistor (MN2) and the third NMOS transistor (MN3), for providing an inverted input signal of the first signal (V(IN)); an output terminal (OUT), coupled to the seventh node (N7), for outputting the second signal (V(OUT)); a mode control terminal (EN), coupled to the gate of the fourth NMOS transistor (MN4), for providing A mode control signal is provided; a first high power supply voltage (VDDH) is coupled to the source of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the fifth PMOS transistor (MP5) to provide the first high power supply voltage required by the potential converter; a second high power supply voltage (VDDL) is coupled to the source of the first inverter (I1) to provide the potential converter The second high power supply voltage (VDDL) is lower than the first high power supply voltage (VDDH); an input circuit (1) coupled to the first input terminal (IN) for providing a differential input signal; a latch circuit (2) coupled to the first high power supply voltage (VDDH) and the input circuit (1) for preserving the output potential of the conversion; a potential shift circuit A circuit (3) coupled to the latch circuit (2) for changing the signal potential output from the latch circuit (2) to output the second signal (V(OUT)); a first current suppression circuit (4) coupled to the potential shift circuit (3) for suppressing current from flowing into the potential shift circuit (3); and a second current suppression circuit (5) coupled to the input circuit (1) for suppressing current from flowing into the latch circuit (2). The potential converter with leakage current suppression as described in item 1 of the patent application, wherein the input circuit (1) includes: a first NMOS transistor (MN1), whose source is connected to the fifth node (N5), whose gate is connected to the first input terminal (IN), and whose drain is connected to the third node (N3); a second NMOS transistor (MN2), whose source is connected to the fifth node (N5), whose gate is connected to the second input terminal (INB), and whose drain is connected to the fourth node (N4); and a first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a signal that is inverted with respect to the first signal (V(IN)). The potential converter with leakage current suppression as described in item 2 of the patent application, wherein the latch circuit (2) includes: a first PMOS transistor (MP1), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the fourth node (N4), and whose drain is connected to the first node (N1); a second PMOS transistor (MP2), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the third node (N3), and its drain is connected to the second node (N2); a third PMOS transistor (MP3), its source is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); and a fourth PMOS transistor (MP4), its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4). As described in item 3 of the patent application scope, the potential converter with leakage current suppression, wherein the potential shift circuit (3) includes: a sixth PMOS transistor (MP6), whose source is connected to the sixth node (N6), whose gate is connected to the third node (N3), and whose drain is connected to the seventh node (N7); and a third NMOS transistor (MN3), whose source is connected to the ground (GND), whose gate is connected to the second input terminal (INB), and whose drain is connected to the seventh node (N7). As described in item 4 of the patent application scope, the potential converter with leakage current suppression, wherein the first current suppression circuit (4) is composed of a fifth PMOS transistor (MP5), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the second input terminal (INB), and whose drain is connected to the sixth node (N6). As described in item 5 of the patent application scope, the potential converter with leakage current suppression, wherein the second current suppression circuit (5) is composed of a fourth NMOS transistor (MN4), whose source is connected to the ground (GND), whose gate is connected to the mode control terminal (EN), and whose drain is connected to the fifth node (N5). The potential converter with leakage current suppression as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). As described in claim 7 of the potential converter with leakage current suppression, the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). As described in claim 2 of the potential converter with leakage current suppression, the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).