五、新型說明： 【新型所屬之技術領域】 本創作係有關於一種半導體封裝裝置，尤指涉及一種直接 以結構中之金屬層作為凸塊下金屬結構層使用而具層數少並 為X/Cu/Sn金屬層之結構者，特別係指具有較佳之電路結構， 並可以於簡化製程而改進生產率之同時達到有效降低成本者。 【先前技術】 近年來，隨著半導體製程技術之不斷成熟與發展，各種 高效能之電子產品不斷推陳出新，而積體電路（Imegrated Circuit, 1C)元件之積集度(Integrati〇n)也不斷提高。在積體 電路元件之封職程巾’賴電賴裝（ICPaekaging)松演 著相當重要之角色，而積體電路封裝型態可大致區分為打線 接合封裝（Wire Bonding Package，WB )、貼帶自動接合封裝 (TapeAutomatic Bonding, TAB)及覆晶接合（Fiip Chip FC) 等型式，且每種封裝形式均具有其特殊性與應用領域。其中， 對於具有尚密度輸出/輸入（1〇)之電路線設計之晶片與基板 而言，當電連線路徑過長時會導致電感（Inductance)增加。 此外，手動操作之打線接合技術所需之製作成本昂貴、製程 品質之可靠度低、且生產率也相對較低。為了改善上述之問 題，另外發展出一種具有縮小封裝面積及縮短訊號傳輸路徑 之覆晶（Flip-CWp)技術或稱之為控制崩潰晶片接合 (Controlled Collapse Chip Connection, C4)。請參閱第 3 圖， 其積體電路封裝結構5 0 0中積體電路晶片5 〇上之凸塊通 常係為錫球6 0，欲將該錫球6 0銲結於該積體電路晶片§ 0時，首先須在該積體電路晶片5 0之金屬銲墊5 41上形 成一具有一至多層金屬層結構之凸塊下金屬層〔Under Bump Metallization，UBM〕7 0 ’由該積體電路晶片5 〇至該錫球 6 0方向包含一形成於該金屬銲墊5 41上之黏著層 (Adhesionlayer) 7 1，例如為鈦金屬層；一具導電性之導 電層（ConductorLayer) 7 2，例如為鋁（A1)、銅（〇〇、 金（Au)或銀（Ag)金屬；一防止該錫球6 〇穿透而與該導 電層7 2反應之阻障層（BarrierLayer) 7 3，例如錄（Ni)、 鉻（Cr)或鉑（Pt)金屬；以及一用以提供該錫球β 〇潤濕 性並保護下方金屬層之濕潤層（WettableLayer) 7 4，例如 金、銀、銅、錫（Sn)或其它有機化合物。其特徵在利用該 凸塊下金屬層7 0提供接置錫球、擴散阻障（Diffusion Barrier)以及適當黏著性等功能於該錫球6 〇與該積體電路 晶片5 0之金屬鮮整5 41間，俾得以將鲜料塗佈至該凸塊 下金屬層7 0上，再經回銲程序（Reflow)以將所施加之銲 料形成所需之錫球6 0。該凸塊下金屬層製程一般採用之方 法係包括濺鍵技術（Sputtering)、蒸链技術（Evaporation)及 電鍵技術（Plating)等。 請參閱第4A〜4F圖，為習知於積體電路晶片上形成 M398194 凸塊下金屬層之製程。如第4A圖所示，首先提供-表面具 數電性接塾5 1之積體電路晶片5 〇 ’該積體電路晶片 5 〇之参面形成有一保護層（Passivation Layer) 5 2，並曝 , _積體電路晶片50上之電性接勢51’該保護層52上 . 另形成有一第一介電層5 3及-第二介電層5 5，且於該第 -介電層5 3及該第二介電層5 5之間係形成有-金屬層 (Trace Metal) 5 4於該電性接墊51上，該第二介電層5 φ 5並曝露該金屬層5 4上之金厲銲塾5 41。如第4 B圓所 不，接著於該第二介電層5 5及該金屬銲墊5 41上利用濺 鍍方式形成一鈦層及一第一銅層7 2a，其中該鈦層係作為黏 著層71。如第4 C及4D圖所示，於該黏著層71上塗佈 一光阻層7 5，經曝光（Expose)與顯影（Devel〇p)後，以 電鍍方式於該第-鋼層7 2a上陸續形成-第二銅層7 2b、 一鎳層及一金層，其中該第一、二銅層7 2a、7 2b係作為 φ 導電層7 2 ;該鎳層係作為阻障層7 3 ;以及該金層係作為 濕潤層74。如第4E及4 F圖所示，最後剝離該光阻層γ 5，並蝕刻於該光阻層75之下顯露之黏著層71與第一銅 層7 2a。至此，完成一具備鈦/銅/鎳/金（Ti/Cu/Ni/Au)四層 結構之凸塊下金屬層7〇。 然而’上述結構在進行覆晶銲塊時，其錫球6 0遇到含 金之銲料時’會產生共晶反應而產生脆性之金錫介金属化合 物（Intermetallic Compound Layer, IMC)，甚而產生孔洞，造 5 成後續於鎮球與該凸塊下金屬層70間發生龜裂，嚴重影響 製程信賴性。 ,有鑑於上述習知於積體電路晶片上形成凸塊下金肩廣技 術而使用夕贿料’且需經過多道程序，不健高製程複雜 又與成本㈣亦伴隨製程中信賴性風險之增加，且該焊錫 材料經高溫迴料雜，導致卿狀焊縣構之品質可靠 度降低it而導致最終產品之電性連接品質降低而有電性短 路之虞’因此將姆地增加抛縣及降低成本效益，且仍 …、法解决產率過低之問題，故，—般習用者係無法符合使用 者於實際使用時之所需◊ 【新型内容】 本創作之主要目的係在於，克服習知技藝所遭遇之上述 問題並提供-種直接以結構中之金屬層作為凸塊下金屬結構 層使用，可省下額外組裝凸塊下金屬結構層之設備費用，且 其結構係她於f知技術可提供，觸化之X/Cu/Sn金屬 層結構’並域額外設置阻障層，不僅得崎數減少而具有 車乂佳之電路結構，並可以於簡化製程而改進生產率之同時達 到有效降低成本者。 為達以上之目的，本創作係一種半導體封裝裝置，主要 包括一半導體裝置、一金屬層（TraceMetal)、一第二介電層 及一銲錫凸塊（SolderBump)。其中該半導體裝置表面係設 M398194 .置有複數個電性接塾，並覆蓋一表面保護層（p^sivation Layer) ’該表面保護層中對應該些電性接墊之位置係具有複 數個開孔以局觸露該些紐接塾，於其巾，絲面保護層 上係設置有一第一介電層，其具有複數個第一開口以至少局 部顯露該些電性接墊；該金屬層係設置於該第—介電層上並 經由該第電性連接至該半導體裝置之電性接塾，該金 屬層主要包含—黏著層（Adhesionlayer)，係設置於該第-介 電層上，可附著基材並可供後續金屬層附著、一導電層 (ConductorLayer)，係設置於該黏著層上、及一保護層，係 -X置於4導電層上’以供可銲錫性（SGider_abiiity)表面並防 止该導電層被氧化；該第二介電層係設置於該第_介電層與 該金屬層之保護層上’其具有複數個第二開口以至少局部顯 路该金屬叙端部；以及該觸凸義設置於該金屬層局部 顯露之端部上’其覆蓋區域係涵蓋該第二介電層之第二開口。 其中，該金屬層之端部係作為凸塊下金屬結構層⑺謝 Bump MetallizatiGn，UBM) ’以在其上接置該銲恥塊且在 該金屬層中與該_凸塊接置之保縣，其係由—第一保護 層及-第二保護層組成’俾供強化與轉錫凸塊之接合力。 【實施方式】 2 F圖』所示，係分別為本 本創作較佳實施例之半導體 請參閱『第1圖及第2A〜 創作之半導體封裝裝置示意圖、 7 2片結構示意圖、本創作製作欽/鋼/錫層於第2 A圖之半導體 晶片上之結構示意圖、本創作塗佈光阻層於第2B圓之鈦/銅 /錫層上之結構示意圖、本創作局部_第2 c圖之欽顧錫 層之結構示意圖、本創作於第2 D圖之局部鈦/銅/錫層上剝離 光阻層之結構示意圖、以及本創作浸㈣層於第2 E圖之局 部欽/銅/騎上之結構示_。如 主要包括_半嶋置二= (TraCeMetal)2 0、一第二介電層3 0及-銲踢凸塊（solderV. New type of description: [New technical field] The present invention relates to a semiconductor packaging device, in particular to a metal layer directly in the structure as a metal structure layer under the bump and having a small number of layers and being X/ The structure of the Cu/Sn metal layer, in particular, means that it has a better circuit structure and can be used to simplify the process and improve productivity while achieving an effective cost reduction. [Prior Art] In recent years, with the continuous maturity and development of semiconductor process technology, various high-performance electronic products are constantly being introduced, and the integration of integrated circuits (Imegrated Circuits, 1C) components (Integrati〇n) is also constantly improving. . In the ICAGE of the integrated circuit components, ICPAK plays a very important role, and the integrated circuit package type can be roughly divided into Wire Bonding Package (WB) and tape. Types of Tape Automatic Bonding (TAB) and Flip Chip FC, each with its specificity and application. Among them, for wafers and substrates with a circuit line design with a still-density output/input (1〇), when the electrical connection path is too long, the inductance (Inductance) increases. In addition, manual wire bonding techniques require expensive manufacturing costs, low process quality reliability, and relatively low productivity. In order to improve the above problems, a flip-chip (Flip-CWp) technique with a reduced package area and a shortened signal transmission path or a Controlled Collapse Chip Connection (C4) has been developed. Referring to FIG. 3, the bumps on the integrated circuit chip 5 of the integrated circuit package structure 500 are usually solder balls 60, and the solder balls 60 are to be soldered to the integrated circuit chip. At 0 o'clock, first, an under bump metallization (UBM) 70 0' has been formed on the metal pad 5 41 of the integrated circuit wafer 50 from the integrated circuit chip. 5, the solder ball 60 direction includes an adhesive layer 7 1 formed on the metal pad 5 41, for example, a titanium metal layer; a conductive conductive layer (ConductorLayer) 7 2, for example Aluminum (A1), copper (yttrium, gold (Au) or silver (Ag) metal; a barrier layer (Barrier Layer) that prevents the solder ball from penetrating and reacting with the conductive layer 72, for example, recording (Ni), chromium (Cr) or platinum (Pt) metal; and a wet layer (WettableLayer) 7.4 for providing the solder ball β 〇 wettability and protecting the underlying metal layer, such as gold, silver, copper, tin (Sn) or other organic compound characterized by the use of the under bump metal layer 70 to provide a solder ball, a diffusion barrier (Dif Fusion barrier) and appropriate adhesion function between the solder ball 6 and the metal of the integrated circuit wafer 50, and the fresh material is applied to the under-metal layer 70 of the bump, and then Reflow is used to form the solder to be applied to the desired solder ball 60. The general method of the under bump metallization process includes sputtering, evaporation, and electric bonding. Plating, etc. Please refer to Figures 4A to 4F for the process of forming a metal layer under the M398194 bump on a conventional circuit wafer. As shown in Fig. 4A, firstly, the surface is provided with a number of electrical contacts. 5 1 of the integrated circuit chip 5 〇 'the integrated circuit chip 5 〇 formed a protective layer (Passivation Layer) 5 2, and exposed, _ integrated circuit 50 on the electrical potential 51 'this protection A first dielectric layer 53 and a second dielectric layer 55 are formed on the layer 52, and a metal is formed between the first dielectric layer 53 and the second dielectric layer 55. a layer of (Trace Metal) 5 4 on the electrical pad 51, the second dielectric layer 5 φ 5 and exposing the metal layer 5 on the metal layer 5 41. According to the fourth B circle, a titanium layer and a first copper layer 7 2a are formed on the second dielectric layer 55 and the metal pad 541 by sputtering, wherein the titanium layer is As the adhesive layer 71, as shown in FIGS. 4C and 4D, a photoresist layer 75 is coated on the adhesive layer 71, exposed and developed (Devel〇p), and then electroplated. - a second copper layer 7 2b, a nickel layer and a gold layer are formed on the steel layer 7 2a, wherein the first and second copper layers 7 2a, 7 2b are used as the φ conductive layer 7 2 ; a barrier layer 73; and the gold layer serves as a wetting layer 74. As shown in Figs. 4E and 4F, the photoresist layer γ 5 is finally stripped, and the adhesive layer 71 and the first copper layer 7 2a exposed under the photoresist layer 75 are etched. Thus, a metal under bump 7 layer having a four-layer structure of titanium/copper/nickel/gold (Ti/Cu/Ni/Au) was completed. However, when the above-mentioned structure is subjected to a flip chip, when the solder ball 60 encounters a gold-containing solder, a eutectic reaction occurs to generate a brittle intermetallic compound layer (IMC), which even creates pores. 5 is followed by cracking between the ball and the metal layer 70 under the bump, which seriously affects the process reliability. In view of the above-mentioned conventional use of the gold-shouldered technology on the integrated circuit chip, the use of the bribes and the need to go through multiple procedures, the complexity of the process is high and the cost (4) is also accompanied by the reliability risk in the process. Increased, and the solder material is returned to the high temperature by the high temperature, which leads to a decrease in the quality reliability of the Qinglian County, which leads to a decrease in the electrical connection quality of the final product and an electrical short circuit. Reduce cost-effectiveness, and still solve the problem of low yield. Therefore, the general users cannot meet the needs of users in actual use. [New content] The main purpose of this creation is to overcome the habits. The above problems encountered in the know-how and the provision of a metal layer directly in the structure as a metal structure layer under the bump can save the equipment cost of additionally assembling the metal structure layer under the bump, and the structure is known to her. Technology can provide, the X/Cu/Sn metal layer structure of the touch-up is additionally provided with a barrier layer, which not only has a reduced number of turns, but also has a good circuit structure, and can improve the productivity by simplifying the process. At the same time reduce costs by up to. For the above purposes, the present invention is a semiconductor package device comprising a semiconductor device, a metal layer (TraceMetal), a second dielectric layer, and a solder bump (SolderBump). The surface of the semiconductor device is provided with M398194. A plurality of electrical interfaces are disposed and covered with a surface protective layer (p^sivation layer). The position of the surface protective layer corresponding to the electrical pads has a plurality of openings. a hole is formed by the hole, and a first dielectric layer is disposed on the wire surface protection layer, and the plurality of first openings are formed to at least partially expose the electrical pads; the metal layer An electrical interface is disposed on the first dielectric layer and is electrically connected to the semiconductor device. The metal layer mainly includes an adhesive layer disposed on the first dielectric layer. The substrate can be attached and attached to the subsequent metal layer, a conductive layer (Conductor Layer) is disposed on the adhesive layer, and a protective layer is disposed on the 4 conductive layer for solderability (SGider_abiiity) And preventing the conductive layer from being oxidized; the second dielectric layer is disposed on the protective layer of the first dielectric layer and the metal layer, and has a plurality of second openings to at least partially display the metal end portion And the touch is placed on the metal Partially exposed on the end of 'its coverage area based covering the second opening of the second dielectric layer. Wherein, the end of the metal layer is used as a sub-bump metal structure layer (7) Xie Bump MetallizatiGn, UBM) 'Bao County on which the solder joint block is attached and which is connected to the _ bump in the metal layer It consists of a first protective layer and a second protective layer, which are used to strengthen the bonding force with the tin bump. [Embodiment] FIG. 2F is a semiconductor of the preferred embodiment of the present invention. Please refer to FIG. 1 and FIG. 2A for a schematic diagram of a semiconductor package device, and a schematic diagram of a structure of 172 pieces. Schematic diagram of the structure of the steel/tin layer on the semiconductor wafer of FIG. 2A, the structure of the photoresist layer coated on the titanium/copper/tin layer of the 2B circle, and the creation of the part _ 2c The schematic diagram of the structure of the Gu tin layer, the structure diagram of the stripping photoresist layer on the local titanium/copper/tin layer of the 2nd D picture, and the local immersion (4) layer on the local Qin/copper/riding of the 2nd E picture The structure shows _. For example, it mainly includes _half 二2 = (TraCeMetal) 2 0, a second dielectric layer 3 0 and - welding kick bumps (solder
Bump) 4 0 〇 該半導體裝置10係為半導體晶片（Chip)、晶圓 (Wafer)、半導體封裝基板、及電路板之其中一者，其表面 係設置有複數個電性接墊1 1，並覆蓋一表面保護層 (PassivationLayer) 1 2，該表面保護層丄2中對應該些電 性接墊11之位置係具有複數個開孔13以局部顯露該些電 性接墊11，其中，該表面保護層X 2上係設置有一第一介 電層14，其具有複數個第一開口15以至少局部顯露該些 電性接墊11。 該金屬層2 0係設置於該第一介電層14上並經由該第 一開口15電性連接至該半導體裝置丄〇之電性接墊i丄， 該金屬層2 0主要包含一黏著層（Adhesion layer) 2 1，係 設置於該第一介電層14上，可附著基材並可供後續金屬層 附著、一導電層（ConductorLayer) 2 2，係設置於該黏著 層21上、及一保護層2 3，係設置於該導電層2 2上，以 供可鲜踢性（Solder-ability)表面並防止該導電層2 2被氧 化，其中，該保護層2 3係由一第一保護層2 3a及一第二保 °蔓層2 3b組成；該金屬層2 〇係為X/銅/錫（x/Cu/Sn)，且 X為一或多種選自鈦（Ti)、鎢（W)、鉻（Cr)、鎳（Ni)、 鈀（Pd)、鉑（Pt)之金屬元素或其混合物所組成之鈦鎢 (Ti/W)、鉻鎳（Cr/Ni)合金等。 该第二介電層3◦係設置於該第一介電層14與該金屬 層2 〇之第一保護層2 3a上，其具有複數個第二開口 3工以 至少局部顯露該金屬層2〇之端部2〇1。 该銲錫凸塊4 〇係為-錫球，係設置於該金屬層2 〇局 顯露之端部2. 〇 1上’其覆蓋區域係涵蓋該第二介電層3 〇之第二開口31。其中，上述金屬層20之端部20 1係 作為凸塊下金屬結騎（Undei*BumpMetanizati()n，UBM丨， 以在其上接置贿錫凸塊4 0，且在該金屬層2 Q中與該鲜 踢凸塊4 0接置之保護層2 3中，該第二保護層2 3b係為 一可視需求增缚度之無電賴（E1_丨essTin)層或浸鑛 踢（Im_i〇nTin)層’俾供強化與該銲錫凸塊4 0之接合 力。以上所述，係構成-全新之半導體封裝裝置i 〇 〇。 曰當本_於時，上述半導魏置1()係為—半導體 明片（Chip)’其上電性接塾2 ^係為_銘接墊（Aw⑷。於 一較佳實施例中，該半導體封裝裝置10 0之金屬層2 0， 簡化之X/Cu/Sn金屬層結構，並無需額外設置以鎳、鉻或鉑 等昂貴材料之阻障層（BarrierLayer)，不僅得以層數減少而 具有較佳之電路結構，並可以於簡化製程而改進生產率之同 時達到有效降低成本者》 综上所述，本創作係一種半導體封裝裝置，可有效改善 習用之種種缺點，係可省下額外組裝凸塊下金屬結構層之設 備費用，能直接以結構中之金屬層作為凸塊下金屬結構層使 用，且其結構亦相對簡單，係相較於習知技術可提供一較為 簡化之X/Cu/Sn金屬層結構，並無需額外設置阻障層，不僅 得以層數減少而具有較佳之電路結構，並可以於簡化製程而 改進生產率之同時達到有效降低成本者，進而使本創作之産 生月b更進步、更實用、更符合使用者之所須，確已符合創作 專利申請之要件，爰依法提出專利申請。 惟以上所述者，僅為本創作之較佳實施例而已，當不能 以此限林創作實施之$!圍；故，凡依本創作申請專利範圍 及新型說明書崎所作之簡單的粒變化與修飾，皆應仍屬 本創作專利涵蓋之範圍内。 【圖式簡單說明】 第1圖，係本創作之半導體封裝裝置示意圖。 第2 A圖’係本創作較佳實施例之半導體晶片結構示意圖。 第2 B圖，係本創作製作欽/銅/錫層於第2 A圖之半導艘晶 M3981.94 片上之結構示意圖。 第2 C圖，係本創作塗佈光阻層於第2β圖之卿錫層上 之結構不意圖。 第2〇圖，縣編部刪_之__之_ 示意圖。 第2E圖，係本創作於第2_之局㈣鋼/锡層上剝離光 阻層之結構示意圖。 第2 F圖，係本創作浸鑛錫層於第2 E圓之局部欽_層 上之結構不意圖。 第3圖’係f知之積體電路封裝結構示意圖。 第4 A圖，係習知之半導體晶片結構示意圖。 第4 B圖’係f知濺舰/銅層於第4 A圖之半導體晶片上 之結構示意圖。 第4 C圖，係f知塗佈光阻層於第4 B圖之鈦/銅層上之結 構示意圖。 第4DS1，係1知電軸/獻金層於第4C®之顯露鈦/銅 層上之結構示意圖。 第4 E圖’係習知於第❹圖之鈦/銅層上剝離光阻層之結 構示意圖。 圖’係習知局部蝕刻第4E圖之剥離光阻層下之鈦/ 銅層之結構示意圖。 M398194 【主要元件符號說明】 (本創作部分） 半導體封裝裝置1 〇 〇 半導體裝置1 0 電性接墊1 1 表面保護層1 2 開孔1 3 第一介電層1 4 第一開口 1 5 金屬層2 0 端部2 0 1 黏著層2 1 導電層2 2 保護層2 3、 第一保護層2 3a 第二保護層2 3b 光阻層2 4 第二介電層3 0 第二開口 3 1 銲錫凸塊4 0 (習用部分） 積體電路封裝結構5◦0 13The semiconductor device 10 is one of a semiconductor chip, a wafer, a semiconductor package substrate, and a circuit board, and a plurality of electrical pads 1 1 are disposed on the surface thereof. Covering a surface protection layer (1), the position of the surface protection layer 对2 corresponding to the electrical pads 11 has a plurality of openings 13 for partially revealing the electrical pads 11, wherein the surface A first dielectric layer 14 is disposed on the protective layer X 2 , and has a plurality of first openings 15 to at least partially expose the electrical pads 11 . The metal layer 20 is disposed on the first dielectric layer 14 and electrically connected to the electrical pad of the semiconductor device via the first opening 15 . The metal layer 20 mainly includes an adhesive layer. (Adhesion layer) 2 1, is disposed on the first dielectric layer 14, can adhere to the substrate and can be attached to the subsequent metal layer, and a conductive layer (Conductor Layer 2) is disposed on the adhesive layer 21, and A protective layer 2 3 is disposed on the conductive layer 22 for a fresher-like surface and preventing the conductive layer 22 from being oxidized, wherein the protective layer 23 is first The protective layer 2 3a and the second protective layer 2 3b are composed; the metal layer 2 is X/copper/tin (x/Cu/Sn), and X is one or more selected from the group consisting of titanium (Ti) and tungsten. Titanium tungsten (Ti/W), chromium nickel (Cr/Ni) alloy, etc. composed of (W), chromium (Cr), nickel (Ni), palladium (Pd), platinum (Pt) metal elements or a mixture thereof. The second dielectric layer 3 is disposed on the first dielectric layer 14 and the first protective layer 23a of the metal layer 2, and has a plurality of second openings 3 to at least partially expose the metal layer 2 The end of the 〇 is 2〇1. The solder bump 4 is a tin ball which is disposed on the end portion of the metal layer 2 where the metal layer 2 is exposed. The upper portion of the second dielectric layer 3 is covered by the second opening 31 of the second dielectric layer 3 . Wherein, the end portion 20 1 of the metal layer 20 is used as a bump under metal tie (Undei*BumpMetanizati()n, UBM丨 to attach the brim bump 40 on the metal layer 2 Q In the protective layer 2 3 which is connected to the fresh kicking block 40, the second protective layer 2 3b is an electroless (E1_丨essTin) layer or a immersion kick (Im_i〇). The nTin) layer is used to strengthen the bonding force with the solder bumps 40. As described above, the new semiconductor package device i 〇〇 曰 , , , , , , , , , , , 上述 , 上述 上述 上述 上述 上述 上述 上述For the semiconductor chip, the power-on interface is a _ ing pad (Aw (4). In a preferred embodiment, the metal layer 20 of the semiconductor package device 10, simplified X/ The Cu/Sn metal layer structure does not require an additional barrier layer of expensive materials such as nickel, chromium or platinum, which not only has a reduced number of layers but also has a better circuit structure, and can simplify the process and improve productivity. To achieve effective cost reduction" In summary, this creation is a semiconductor packaging device that can effectively improve the species used. The disadvantage is that the equipment cost of additionally assembling the metal structure layer under the bump can be saved, and the metal layer in the structure can be directly used as the metal structure layer under the bump, and the structure thereof is relatively simple, and the system can be compared with the prior art. Providing a relatively simplified X/Cu/Sn metal layer structure, without requiring an additional barrier layer, not only having a reduced number of layers but also having a better circuit structure, and simplifying the process to improve productivity while achieving an effective cost reduction. In turn, the creation of this creation is more progressive, more practical, and more in line with the needs of the user. It has indeed met the requirements for the creation of a patent application, and has filed a patent application according to law. However, the above is only the best of the creation. In the case of the example, it is not possible to create a $! fence for this limitation; therefore, the simple grain changes and modifications made by the patent application scope and the new specification of the creation should remain within the scope of this creation patent. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a semiconductor package device of the present invention. Fig. 2A is a schematic diagram of a semiconductor wafer structure of a preferred embodiment of the present invention. Fig. 2B is a schematic diagram showing the structure of the semi-guided crystal M3981.94 on the 2nd A picture of the Qin/Copper/tin layer. The 2nd C picture shows the application of the photoresist layer. 2β 图 图 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的Schematic diagram of the structure of the resist layer. Fig. 2 F is a schematic diagram of the structure of the immersion tin layer on the local layer of the 2nd E circle. Fig. 3 is a schematic diagram of the package structure of the integrated circuit. A is a schematic diagram of a conventional semiconductor wafer structure. Fig. 4B is a schematic view showing the structure of a sputtering ship/copper layer on a semiconductor wafer of Fig. 4A. Fig. 4C is a schematic view showing the structure of the photoresist layer coated on the titanium/copper layer of Fig. 4B. The fourth DS1 is a schematic diagram showing the structure of the electric/core layer on the exposed titanium/copper layer of the 4C®. Fig. 4E is a schematic view showing the structure of the stripping photoresist layer on the titanium/copper layer of the second embodiment. Fig. ' is a schematic view showing the structure of a conventional titanium/copper layer under the stripping photoresist layer of Fig. 4E. M398194 [Description of main component symbols] (This creation part) Semiconductor package device 1 〇〇Semiconductor device 1 0 Electrical pad 1 1 Surface protection layer 1 2 Opening hole 1 3 First dielectric layer 1 4 First opening 1 5 Metal Layer 2 0 End 2 0 1 Adhesive layer 2 1 Conductive layer 2 2 Protective layer 2 3, First protective layer 2 3a Second protective layer 2 3b Photoresist layer 2 4 Second dielectric layer 3 0 Second opening 3 1 Solder bump 4 0 (conventional part) Integrated circuit package structure 5◦0 13