TW202539001A - Electronic device - Google Patents

Abstract

An electronic device is provided. The electronic device includes a package structure, a redistribution structure, a first conductive pad, a second conductive pad and an electronic unit. The redistribution structure is disposed on the package structure. The first conductive pad is disposed on the redistribution structure. The second conductive pad is disposed on the first conductive pad. The package structure is electrically connected to the electronic unit through the redistribution structure, the first conductive pad and the second conductive pad. In addition, in a direction perpendicular to a normal direction of the electronic device, there is a distance between a center line of the first conductive pad and a center line of the second conductive pad.

Description

Electronic devices

This disclosure relates to electronic devices, and more particularly to conductive pad structures for electronic devices.

Fan-out packaging, such as fan-out panel level package (FOPLP) or fan-out wafer level package (FOWLP) technologies, can increase the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) in a given area, and has been widely used in the production and manufacturing of electronic devices in recent years.

However, fan-out packaging structures often involve the integration of heterogeneous material interfaces (e.g., the interface between the redistribution layer (RDL) and the conductive pad, the under bump metallurgy (UBM) region, etc.). The interfaces of heterogeneous materials are often prone to delamination or peeling due to the presence of large stresses.

As mentioned above, developing solutions to improve the reliability of electronic device packaging structures (e.g., reducing stress in heterogeneous interface structures) remains one of the key research topics in the industry.

According to embodiments of this disclosure, the electronic device includes a conductive pad with specific material properties, which can effectively reduce the stress of the heterogeneous interface structure, thereby improving the structural reliability of the electronic device. According to some embodiments of this disclosure, an electronic device is provided, including a packaging structure, a reflow wiring structure, a first conductive pad, a second conductive pad, and an electronic unit. The reflow wiring structure is disposed on the packaging structure. The first conductive pad is disposed on the reflow wiring structure. The second conductive pad is disposed on the first conductive pad. The packaging structure electrically connects the electronic unit through the reflow wiring structure, the first conductive pad, and the second conductive pad. Furthermore, in a direction perpendicular to the normal direction of the electronic device, there is a distance between the centerline of the first conductive pad and the centerline of the second conductive pad.

To make the features or advantages disclosed herein clearer and easier to understand, some embodiments are provided below, along with accompanying diagrams, for detailed explanation.

The following provides a detailed description of the electronic device according to embodiments of this disclosure. It should be understood that the following description provides many different embodiments to implement various forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for the simple and clear description of some embodiments of this disclosure. Of course, these are only illustrative and not limiting of this disclosure. Furthermore, similar and/or corresponding reference numerals may be used in different embodiments to identify similar and/or corresponding elements for the clear description of this disclosure. However, the use of these similar and/or corresponding reference numerals is only for the simple and clear description of some embodiments of this disclosure and does not imply any relationship between the different embodiments and/or structures discussed.

It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in the embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the device depicted in the diagram is flipped upside down, the element described as being on the "lower" side will become the element on the "higher" side. This disclosure embodiment should be understood in conjunction with the diagrams, which are also considered part of the disclosure description. It should be understood that the diagrams in this disclosure are not drawn to scale; in fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of this disclosure.

Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

The directional terms used in this document, such as "up," "down," "forward," "backward," "left," and "right," are for reference only in the accompanying diagrams. Therefore, the directional terms used are for illustrative purposes and not for limiting this disclosure.

Furthermore, it should be understood that the use of ordinal numbers such as "first" and "second" in the specification and the scope of the patent application to modify components does not imply or represent any prior ordinal number of that component (or those components), nor does it represent the order of one component with another, or the order of manufacturing methods. The use of these ordinal numbers is solely to clearly distinguish one component with a given name from another component with the same name. The scope of the patent application and the specification may not use the same terminology; for example, the first component in the specification may be the second component in the scope of the patent application.

In some embodiments disclosed herein, terms such as “connection” and “interconnection”, unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with another structure situated between them. Furthermore, these terms may also encompass situations where both structures are movable or both are fixed. Additionally, the terms “electrical connection” or “electrical coupling” include any direct or indirect electrical connection means.

In this text, the terms "about" and "substantially" generally refer to a range within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value. The phrase "the range between the first and second values" means that the range includes the first value, the second value, and other values in between.

It should be understood that the following embodiments can be used to substitute, recombine, and combine features from several different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, for example, as defined in a commonly used dictionary, should be interpreted in a manner consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

According to some embodiments disclosed herein, an electronic device is provided that includes a conductive pad with specific material properties, which can effectively reduce the stress of a heterogeneous interface structure and thereby improve the structural reliability of the electronic device.

According to embodiments disclosed herein, the electronic device includes a semiconductor package structure. The electronic device may include, but is not limited to, a display device, a backlight device, an antenna device, a touch device, a sensing device, a wearable device, an automotive device, a battery device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-emissive display device or a self-emissive display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited to these. Furthermore, the electronic device may, for example, include liquid crystal, quantum dot (QD), fluorescence, phosphorescence, other suitable materials, or combinations thereof. Electronic devices may include electronic components, which may include passive and active components, such as capacitors, resistors, inductors, diodes, and transistors. Diodes may include light-emitting diodes or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. According to some embodiments, electronic devices may include panels and/or backlight modules. Panels may include, for example, liquid crystal panels or other self-emissive panels, but are not limited thereto. Splicing devices may be, for example, display splicing devices or antenna splicing devices, but are not limited thereto. It should be understood that electronic devices may be any combination of the foregoing, but are not limited thereto.

Please refer to Figures 1 and 2. Figure 1 shows a partial cross-sectional schematic diagram of the electronic device 10 according to some embodiments of this disclosure. Figure 2 shows a partially enlarged schematic diagram of region R1 in Figure 1 according to some embodiments of this disclosure (region R1 shows an inverted structure). It should be understood that, for clarity, some components of the electronic device 10 may be omitted in the figures, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10 described below.

As shown in Figures 1 and 2, the electronic device 10 may include an electronic unit 100, a rewiring structure 120, and a conductive pad 110. The conductive pad 110 may be disposed between the rewiring structure 120 and the electronic unit 100, and the electronic unit 100 may be electrically connected to the rewiring structure 120 through the conductive pad 110.

According to some embodiments, electronic unit 100 may include integrated circuits (ICs), capacitors, sensors, resistors, printed circuit boards (PCBs), diodes, other suitable electronic components, or combinations thereof, but is not limited thereto. Furthermore, the number of electronic units is not limited to those shown in the figures; depending on different embodiments, the electronic device may have any suitable number of electronic units.

According to some embodiments, the redistribution structure 120 includes at least one conductive layer 120a and at least one insulating layer 120b, which may be arranged in an alternating manner. A conductive pad 110 may be disposed on the conductive layer 120a and the insulating layer 120b. According to some embodiments, the conductive layer 120a can be a single-layer or multi-layer structure. The conductive layer 120a may contain conductive materials, such as copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), any of the aforementioned metal alloys, other suitable materials, or combinations thereof, but not limited thereto. According to some embodiments, the conductive material can be formed by physical vapor deposition, electroplating, electroless electroplating, other suitable methods, or combinations thereof. Furthermore, the conductive material can be patterned using one or more photolithography and/or etching processes to form a patterned conductive layer 120a.

According to some embodiments, the insulating layer 120b may comprise a polymer insulating material, such as ABF build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), other suitable insulating materials, or combinations thereof, but not limited thereto. According to some embodiments, the insulating layer 120b may be formed by a coating process, a spin coating process, a chemical vapor deposition (CVD) process, other suitable methods, or combinations thereof.

It should be understood that, depending on the different embodiments, the redistribution structure 120 may include any suitable number of conductive layers 120a and insulating layers 120b, such as one or more conductive layers 120a and insulating layers 120b.

Furthermore, according to some embodiments, the electronic device 10 may further include an insulating layer 102 and a conductive pad 112. The insulating layer 102 may be disposed adjacent to the conductive pads 110 and 112. The conductive pad 112 may be disposed between the conductive pad 110 and the electronic unit 100, and the conductive pad 110 may be electrically connected to the electronic unit 100 through the conductive pad 112. According to some embodiments, the conductive pad 110 may be in contact with the insulating layer 102 and the conductive pad 112.

According to some embodiments, insulating layer 120b and insulating layer 102 may have the same material. According to some embodiments, insulating layer 102 may be an encapsulation material or underfill, which can reduce the influence of water and oxygen in the external environment on conductive pad 110 and/or conductive layer 120a, but is not limited thereto. According to some embodiments, insulating layer 102 may contain molding compound, epoxy resin, other suitable encapsulation materials, or combinations thereof, but is not limited thereto. Insulating layer 102 may contain filler particles, such as silicon oxide, aluminum oxide, titanium oxide, combinations thereof, or other suitable materials, but is not limited thereto. According to some embodiments, the insulating layer 102 can be formed by compression molding, transfer molding, or other suitable methods. According to some embodiments, the insulating layer 102 can be molded in a liquid or semi-liquid state and then cured. According to some embodiments, the insulating layer 102 can fill the space between the rearranged wire structure 120 and the electronic unit 100, but is not limited thereto.

According to some embodiments, conductive pad 112 may be a contact bump, and conductive pad 110 may serve as an under bump metallurgy (UBM) layer, electrically connected to conductive pad 112, thereby electrically connecting the redistribution structure 120 to the electronic unit 100. Conductive pad 112 may have a single-layer or multi-layer structure. According to some embodiments, the material of conductive pad 112 may include tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead-free solder, copper (Cu), other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the conductive pad 112 can be bonded to the conductive pad 110 by a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, other suitable methods, or a combination thereof.

It is worth noting that, according to some embodiments, the conductive pad 110 is a contact pad that is externally bonded to the electronic unit 100 by the package structure or the redistribution structure 120. The conductive pad 110 is located near multiple heterogeneous interfaces, such as the interface position between the conductive layer 120a and the conductive pad 110 (position P1), the interface position between the conductive layer 120a and the insulating layer 120b (position P2), and the interface position between the conductive pad 110 and the conductive pad 112 (position P3), etc. Locations near heterogeneous interfaces are prone to problems such as delamination or peeling. To address this, the embodiments disclosed herein provide a conductive pad 110 with specific material properties, which can effectively reduce the stress of heterogeneous interface structures and thereby improve the structural reliability of electronic devices.

Specifically, the conductive pad 110 has a first coefficient of thermal expansion (CTE) and a first Young's coefficient, and the first coefficient of thermal expansion and the first Young's coefficient conform to the following relationship: In the relationship, CTE is the first coefficient of thermal expansion, and E is the first Young's coefficient. According to some embodiments, the first coefficient of thermal expansion and the first Young's coefficient of the conductive pad 110 conform to the following relationship: According to some embodiments, the first thermal expansion coefficient and the first Young's coefficient of the conductive pad 110 conform to the following relationship: .

Furthermore, according to some embodiments, the first coefficient of thermal expansion of the conductive pad 110 can be greater than or equal to 10 ppm/℃ and less than or equal to 43.6 ppm/℃ (i.e., 10 ppm/℃ ≤ first coefficient of thermal expansion ≤ 43.6 ppm/℃). According to some embodiments, the first Young's coefficient of the conductive pad 110 can be greater than or equal to 17 GPa and less than or equal to 89 GPa (i.e., 89 GPa ≤ first Young's coefficient ≤ 43.6 ppm/℃). It is worth noting that the conductive pad 110 with the aforementioned specific material properties can effectively reduce the stress of the heterogeneous interface structure and reduce the risk of failure of the electronic device.

According to some embodiments, the conductive pad 112 has a second coefficient of thermal expansion, and the second coefficient of thermal expansion of the conductive pad 112 is greater than the first coefficient of thermal expansion of the conductive pad 110. Specifically, according to some embodiments, the second coefficient of thermal expansion of the conductive pad 112 may be greater than or equal to 15 ppm/℃ and less than or equal to 30 ppm/℃ (i.e., 15 ppm/℃ ≦ second coefficient of thermal expansion ≦ 30 ppm/℃).

According to some embodiments, the aforementioned insulating layer 102 has a fourth coefficient of thermal expansion, and the fourth coefficient of thermal expansion of the insulating layer 102 is less than the first coefficient of thermal expansion of the conductive pad 110. Specifically, according to some embodiments, the fourth coefficient of thermal expansion of the insulating layer 102 may be greater than or equal to 5 ppm/℃ and less than or equal to 12 ppm/℃ (that is, 5 ppm/℃ ≤ fourth coefficient of thermal expansion ≤ 12 ppm/℃).

Furthermore, according to some embodiments, the aforementioned insulation layer 120b has a fifth coefficient of thermal expansion, and the fifth coefficient of thermal expansion of the insulation layer 120b is less than the first coefficient of thermal expansion of the conductive pad 110. Specifically, according to some embodiments, the fifth coefficient of thermal expansion of the insulation layer 120b may be greater than or equal to 5 ppm/℃ and less than or equal to 25 ppm/℃ (that is, 5 ppm/℃ ≤ fifth coefficient of thermal expansion ≤ 25 ppm/℃).

According to the embodiments disclosed herein, the coefficient of thermal expansion can be determined by looking up a table, using a thermal expansion analyzer, or by other conventional directional measuring elements (e.g., the aforementioned conductive pad 110). Alternatively, the Young's coefficient can be determined by looking up a table, using the ASTM D638 standard method, or by other conventional directional measuring elements (e.g., the aforementioned conductive pad 110). For example, the Young's coefficient of the conductive pad 110 can be greater than or equal to 15 GPa and less than or equal to 25 GPa (i.e., 15 GPa ≤ Young's coefficient of the conductive pad 110 ≤ 25 GPa).

Furthermore, according to some embodiments, the material properties of the aforementioned conductive pad 110 can be obtained by stress simulation analysis of the heterogeneous interface structure of the electronic device. For example, it can be simulated using the response surface methodology (RSM), but this disclosure is not limited to this. In detail, according to some embodiments, the response surface methodology can be used to obtain the response surface (with thermal expansion coefficient, Young's coefficient, and stress as parameters) formed by different materials in a specific heterogeneous interface structure of the electronic device.

Please refer to Figures 3A to 3C. Figure 3A shows the results of stress simulation analysis performed at position P1 (the interface between conductive layer 120a and conductive pad 110, as shown in Figure 2) of electronic device 10 according to some embodiments of this disclosure. Figure 3B shows the results of stress simulation analysis performed at position P2 (the interface between conductive layer 120a and insulating layer 120b, as shown in Figure 2) of electronic device 10 according to some embodiments of this disclosure. Figure 3C shows the results of stress simulation analysis performed at positions P1 and P2 (as shown in Figure 2) of electronic device 10 according to some embodiments of this disclosure. Figure 3C presents an overlay of the results from Figures 3A and 3B.

From Figures 3A and 3B, the coefficients of thermal expansion, Young's coefficients, and stresses of different materials at positions P1 and P2 in the electronic device 10 can be obtained, thereby yielding the response surfaces at positions P1 and P2. Furthermore, the response surfaces from Figures 3A and 3B can be superimposed to obtain Figure 3C. Based on the results of Figure 3C, the range of low-stress surfaces of the conductive pad 110 can be determined, and the corresponding relationship between the coefficient of thermal expansion and the Young's coefficient that achieves low interfacial stress can be derived. Specifically, the relationship is as follows: The conductive pad 110, with its material properties, will have low interfacial stress.

According to the embodiments disclosed herein, the material of the conductive pad 110 may contain components conforming to the foregoing relationship: Any conductive material. For example, the conductive material may include copper alloys, magnesium alloys, zinc alloys, titanium alloys, or other conductive materials conforming to the formula, but this disclosure is not limited thereto. Furthermore, the conductive pad 110 may have a single-layer or multi-layer structure. According to some embodiments, the conductive material can be formed by physical vapor deposition, electroplating, electroless electroplating, other suitable methods, or combinations thereof. Moreover, the conductive material can be patterned to form the conductive pad 110 by one or more photolithography and/or etching processes.

As mentioned above, the conductive pad 110 can be used as a contact pad for the external bonding of the package structure to the electronic unit 100. The conductive pad 110 is located near the multi-dimensional heterogeneous interface. The following will further explain the application of the conductive pad 110 in electronic devices with different structures.

As shown in Figure 1, the electronic device 10 may further include a package structure 200 electrically connected to the redistribution structure 120. According to some embodiments, the package structure 200 may include a chip 202 and a protective layer 204, the protective layer 204 being disposed around the chip 202. Specifically, the protective layer 204 surrounding the chip 202 means that, in cross-sectional view, the protective layer 204 contacts at least two sides of the chip 202. According to some embodiments, the protective layer 204 may surround at least one chip 202. According to some embodiments, the protective layer 204 may simultaneously surround at least one chip 202, a resistor, capacitor, inductor, antenna element, or other suitable electronic element, but is not limited thereto. In other words, chips, resistors, capacitors, inductors, antenna elements or other suitable electronic components may be electrically connected to or electrically connected to each other through a rewiring structure, but are not limited thereto.

According to some embodiments, the electronic device 10 can be packaged as a system-on-chip (SoP), a system-in-package (SiP), or other suitable methods. Furthermore, according to some embodiments, the manufacturing method of the electronic device 10 can be applied to wafer-level package (WLP) or panel-level package (PLP), but this disclosure is not limited thereto.

According to some embodiments, the chip 202 may be, for example, a known-good die (KGD), an integrated circuit chip (IC), a diode, etc.

According to some embodiments, the protective layer 204 may be a packaging material that reduces the impact of water and oxygen in the external environment on the chip 202, but is not limited thereto. According to some embodiments, the protective layer 204 may comprise molding compounds, epoxy resins, other suitable packaging materials, or combinations thereof, but is not limited thereto. According to some embodiments, the protective layer 204 may be formed by compression molding, transfer molding, or other suitable methods. According to some embodiments, the protective layer 204 may be molded in a liquid or semi-liquid state and then cured. The protective layer 204 may contain filler particles, such as silicon oxide, aluminum oxide, titanium oxide, combinations thereof, or other suitable materials, but is not limited thereto. According to some embodiments, the particle size of the filler particles in the protective layer 204 is greater than or equal to the particle size of the filler particles in the insulating layer 102, so that the protective layer 204 can have excellent rigidity, preventing the packaging device from being scratched or reducing the impact of water and oxygen in the external environment on the wafer 202, but not limited thereto.

According to some embodiments, the protective layer 204 has a third coefficient of thermal expansion, and the third coefficient of thermal expansion of the protective layer 204 is less than the first coefficient of thermal expansion of the conductive pad 110. Specifically, according to some embodiments, the third coefficient of thermal expansion of the protective layer 204 may be greater than or equal to 6 ppm/℃ and less than or equal to 24 ppm/℃ (that is, 6 ppm/℃ ≦ third coefficient of thermal expansion ≦ 24 ppm/℃).

Furthermore, in this embodiment, the electronic device 10 employs a chip-first packaging method, that is, first forming a package structure 200 containing the chip 202, and then forming a redistribution structure 120 on the package structure 200, but this disclosure is not limited thereto. The chip-first method may further include face-up and face-down.

As shown in Figure 1, according to some embodiments, the package structure 200 may further include a conductive pad 206, a connector 208, a passivation layer 210, and an insulating layer 212. The conductive pad 206 and the connector 208 may be disposed between the chip 202 and the redistribution structure 120 to provide electrical connection between the chip 202 and the redistribution structure 120. Furthermore, the passivation layer 210 and the insulating layer 212 may be disposed around the conductive pad 206 and the connector 208.

According to some embodiments, the conductive pad 206 may be made of conductive materials, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), any of the aforementioned metal alloys, transparent conductive materials, or other suitable conductive materials, but is not limited thereto. According to some embodiments, the conductive material may be formed by physical vapor deposition, electroplating, electroless electroplating, other suitable methods, or combinations thereof. Furthermore, the conductive material may be patterned using one or more photolithography and/or etching processes to form the conductive pad 206.

According to some embodiments, the material of connector 208 may include conductive materials, such as copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), any of the aforementioned metal alloys, other suitable materials, or combinations thereof, but not limited thereto. According to some embodiments, the conductive material can be formed by physical vapor deposition, electroplating, electroless electroplating, other suitable methods, or combinations thereof. Furthermore, the conductive material can be patterned to form connector 208 by one or more photolithography and/or etching processes.

According to some embodiments, the material of the passivation layer 210 may include inorganic materials, organic materials, or combinations thereof, but is not limited thereto. For example, inorganic materials may include silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof, but are not limited thereto. For example, organic materials may include polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), polymethyl methacrylate (PMMA), polyimide (PI), photosensitive polyimide (PSPI), other suitable materials, or combinations thereof, but are not limited thereto. Furthermore, the passivation layer 210 may have a single-layer or multi-layer structure. According to some embodiments, the passivation layer 210 can be formed by a spin coating process, a chemical vapor deposition (CVD) process, other suitable methods, or a combination thereof.

According to some embodiments, the insulating layer 212 may comprise a polymer insulating material, such as ABF build-up film, polybenzobis(oxo)azole (PBO), polyimide, photosensitive polyimide, phenylcyclobutene (BCB), other suitable insulating materials, or combinations thereof, but not limited thereto. According to some embodiments, the insulating layer 212 may be formed by a coating process, a spin coating process, a chemical vapor deposition (CVD) process, other suitable methods, or combinations thereof.

Furthermore, as shown in Figure 1, according to some embodiments, the conductive pad 110 has a substantially flat top surface, which is substantially flush with the top surface of the insulating layer 102. Moreover, the conductive pad 112 may have a first width W1, and the conductive pad 110 may have a second width W2. According to some embodiments, the first width W1 of the conductive pad 112 may be greater than the second width W2 of the conductive pad 110. Furthermore, according to some embodiments, the center line 110L of conductive pad 110 and the center line 112L of conductive pad 112 do not overlap; there is a distance between the center lines 110L and 112L. That is, an offset occurs when conductive pads 110 and 112 are joined. According to some embodiments, the distance between the center lines 110L and 112L does not exceed W²/6 of the width of conductive pad 110, and can be between 0 and W²/6. It is worth noting that a slight offset between conductive pads 110 and 112 can reduce the stress after the joining reaction; however, the offset distance should not be too large to affect the electrical connection. According to some embodiments, the conductive pad 112 does not overlap with the side 202S of the chip 202. This design can reduce stress during the manufacturing process and thus improve reliability.

According to the embodiments disclosed herein, the first width W1 refers to the maximum width of the conductive pad 110 in a direction perpendicular to the normal direction of the electronic device (e.g., the normal direction of the conductive pad 110) (e.g., the X direction in the figure), and the second distance W2 refers to the maximum width of the conductive pad 112 in a direction perpendicular to the normal direction of the electronic device (e.g., the normal direction of the conductive pad 110) (e.g., the X direction in the figure).

It should be understood that, according to the embodiments disclosed herein, the width, thickness, or height of each element, and the spacing or distance between elements, can be measured using a scanning electron microscope (SEM), an optical microscope (OM), an α-step thickness profiler, an elliptical thickness gauge, or other suitable methods. More specifically, according to some embodiments, a scanning electron microscope can be used to acquire a cross-sectional image containing the elements to be measured, and the width, thickness, or height of each element, and the spacing or distance between elements, can be measured.

Next, please refer to Figure 4, which shows a partial cross-sectional schematic diagram of the electronic device 20 according to some other embodiments of this disclosure. It should be understood that, for clarity, some components of the electronic device 20 may be omitted from the drawing, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 20 described below. Furthermore, it should be understood that components or elements that are the same or similar to those described above will be indicated by the same or similar reference numerals, and their materials, manufacturing methods, and functions are the same or similar to those described above; therefore, this part will not be repeated hereafter.

As shown in Figure 4, according to some embodiments, the redistribution structure 120 may further include a thin-film transistor (TFT) unit 120T. The TFT unit 120T may be electrically connected to the conductive layer 120a in the redistribution structure 120, and then electrically connected to the conductive pad 110 and the electronic unit 100 for driving. According to some embodiments, the TFT unit 120T may be further electrically connected to the signal lines of the electronic device. The signal lines may include, for example, current signal lines, voltage signal lines, high-frequency signal lines, and low-frequency signal lines, and the signal lines may transmit the device operating voltage (VDD), the common ground voltage (VSS), or the driving device terminal voltage. This disclosure is not limited thereto. According to some embodiments, the conductive layer 120a in the redistribution line structure 120 may be a dummy pattern, but is not limited thereto.

It should be understood that the number and type of thin-film transistor units 120T are not limited to those shown in the figures. Depending on the embodiment, the electronic device may have other suitable numbers or types of thin-film transistors. The types of thin-film transistor units 120T may include top-gate thin-film transistors, bottom-gate thin-film transistors, dual-gate or double-gate thin-film transistors, or combinations thereof. According to some embodiments, the thin-film transistor units 120T may be further electrically connected to capacitive elements, but this is not a limitation. Furthermore, the thin-film transistor unit 120T may include at least one semiconductor layer, a gate dielectric layer, and a gate electrode layer, wherein the semiconductor layer may include single-crystal silicon, polycrystalline silicon, cryogenic silicon, oxide semiconductor, or a combination thereof, but is not limited thereto. In addition, the materials of the source electrode and drain electrode of the thin-film transistor unit 120T may be the same as or different from those of the conductive layer 120a. The thin-film transistor unit 120T may exist in various forms well known to those skilled in the art, and its detailed structure will not be described here.

Furthermore, as shown in Figure 4, according to some embodiments, the top surface of the conductive pad 110 may be recessed, that is, it has a concave surface. This design, for example, can prevent the conductive pad 112 from shifting.

Next, please refer to Figure 5, which shows a partial cross-sectional schematic diagram of the electronic device 30 according to some other embodiments of this disclosure. It should be understood that, for clarity, some components of the electronic device 30 may be omitted from the drawing, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 30 described below.

As shown in Figure 5, the connector 208 of the package structure 200 has a first thickness T1, and the conductive pad 110 has a second thickness T2. According to some embodiments, the second thickness T2 of the conductive pad 110 may be greater than the first thickness T1 of the connector 208. Specifically, according to some embodiments, the first thickness T1 may be between 1 micrometer (μm) and 5 micrometers (μm) (i.e., 1 μm ≤ first thickness T1 ≤ 5 μm). According to some embodiments, the second thickness T2 may be between 5 micrometers (μm) and 20 micrometers (μm) (i.e., 5 μm ≤ second thickness T2 ≤ 20 μm). It is worth noting that, with the aforementioned configuration, the stability after the conductive pads 110 and 112 are connected can be improved, the heat dissipation effect can be enhanced, and thus the electrical connection or reliability can be improved.

According to the embodiments disclosed herein, the first thickness T1 refers to the maximum thickness of the conductive pad 110 in the normal direction of the electronic device (e.g., the Z direction in the diagram), and the second thickness T2 refers to the maximum thickness of the connector 208 in the normal direction of the electronic device (e.g., the Z direction in the diagram).

Furthermore, as shown in Figure 5, according to some embodiments, the top surface of the conductive pad 110 may be raised, i.e., have a convex surface. The conductive pad 110 may protrude beyond the top surface of the insulation layer 102. According to some embodiments, the top surface of the conductive pad 110 may be planar, and the planar surface is higher than the top surface of the insulation layer 102. According to some embodiments, the top surface of the conductive pad 110 may be concave, and the concave surface is higher than the top surface of the insulation layer 102, but this is not a limitation.

Next, please refer to Figure 6, which shows a partial cross-sectional schematic diagram of the electronic device 40 according to some other embodiments of this disclosure. It should be understood that, for clarity, some components of the electronic device 40 may be omitted from the drawing, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 40 described below.

As shown in Figure 6, according to some embodiments, the electronic device 40 may adopt a redistribution-first (RDL first) packaging method, that is, the redistribution structure 120 is formed first, and then a package structure 200 including the chip 202 is formed on the redistribution structure 120. In this embodiment, the conductive layer 120a of the redistribution structure 120 may be further electrically connected to conductive pads 110' and 112', which are respectively disposed on opposite sides of the redistribution structure 120. The materials and forming methods of conductive pads 110' and 112' are the same as or similar to those of the aforementioned conductive pads 110 and 112, and will not be repeated here. According to some embodiments, the conductive layer 120a in the redistribution structure 120 may be a dummy pattern or electrically connected to the grounding signal line, but is not limited thereto. According to some embodiments, the surface of conductive pad 110' may be substantially flush with the surface of the insulating layer 102b. For example, along the Z-direction, the difference between the surface of conductive pad 110' and the surface of the insulating layer 102b may be greater than or equal to 0 micrometers and less than or equal to 5 micrometers. According to some embodiments, the surface of conductive pad 110' may protrude along the Z-direction from the surface of the insulating layer 102b. According to some embodiments, the surface of the conductive pad 110' may be recessed along the Z direction into the surface of the insulating layer 102b.

Furthermore, the electronic device 40 may further include a protective layer 214, which may be disposed between the redistribution structure 120 and the packaging structure 200 and surround the conductive pad 112.

According to some embodiments, the protective layer 214 may be an encapsulation material that can reduce the influence of water and oxygen in the external environment on the conductive pads 110 and 112, but is not limited thereto. According to some embodiments, the protective layer 214 may comprise molding compounds, epoxy resins, other suitable encapsulation materials, or combinations thereof, but is not limited thereto. According to some embodiments, the protective layer 214 may be formed by compression molding, transfer molding, or other suitable methods. According to some embodiments, the protective layer 214 may be molded in a liquid or semi-liquid form and then cured.

In summary, according to the embodiments disclosed herein, the electronic device includes a conductive pad with specific material properties, which can effectively reduce the stress of the heterogeneous interface structure and thereby improve the structural reliability of the electronic device.

Although the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone with ordinary skill in the art can combine, modify, substitute, and refine them without departing from the spirit and scope of this disclosure. Features among the embodiments disclosed may be freely mixed and matched as long as they do not violate the spirit of the invention or conflict with it. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Any processes, machines, manufacturing, material composition, apparatus, methods, and steps that can be understood by those skilled in the art from the content of this disclosure, whether currently developed or in the future, may be used in accordance with this disclosure, as long as substantially the same function can be performed or substantially the same result can be obtained in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. The scope of protection of this disclosure shall be determined by the appended patent application scope. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and features disclosed in this disclosure.

10, 20, 30, 40: Electronic device; 100: Electronic unit; 102: Insulation layer; 110, 110’: Conductive pad; 110L: Center line; 112, 112’: Conductive pad; 112L: Center line; 120: Relayed wiring structure; 120a: Conductive layer; 120b: Insulation layer; 120T: Thin film transistor unit. 200: Package structure; 202: Chip; 202S: Side; 204: Protective layer; 206: Conductive pad; 208: Connector; 210: Passivation layer; 212: Insulating layer; 214: Protective layer; P1, P2, P3: Location; R1: Area; T1: First thickness; T2: Second thickness; W1: First width; W2: Second width.

Figure 1 shows a partial cross-sectional structural schematic diagram of the electronic device according to some embodiments of the present disclosure; Figure 2 shows a partially enlarged schematic diagram of region R1 in Figure 1 according to some embodiments of the present disclosure; Figure 3A shows the results of stress simulation analysis performed at position P1 of the electronic device according to some embodiments of the present disclosure; Figure 3B shows the results of stress simulation analysis performed at position P2 of the electronic device according to some embodiments of the present disclosure. Figure 3C shows the results of stress simulation analysis performed at positions P1 and P2 of the electronic device according to some embodiments of the present disclosure; Figure 4 shows a partial cross-sectional schematic diagram of the electronic device according to some embodiments of the present disclosure; Figure 5 shows a partial cross-sectional schematic diagram of the electronic device according to some embodiments of the present disclosure; Figure 6 shows a partial cross-sectional schematic diagram of the electronic device according to some embodiments of the present disclosure.

10: Electronic Devices

100: Electronic Unit

102: The Insulation Layer

110: Conductive Pad

110L: Centerline

112: Conductive Pad

112L: Centerline

120: Relay Line Structure

120a: Conductive layer

120b: Insulation layer

200: Packaging Structure

202: Chip

202S: Side

204: Protective Layer

206: Conductive Pad

208: Connector

210: Passivation layer

212: Insulation Layer

R1: Region

W1: First width

W2: Second width

Claims (10)

An electronic device includes: a packaging structure; a rewiring structure disposed on the packaging structure; a first conductive pad disposed on the rewiring structure; a second conductive pad disposed on the first conductive pad; and an electronic unit, wherein the packaging structure is electrically connected to the electronic unit through the rewiring structure, the first conductive pad, and the second conductive pad, wherein a distance exists between a center line of the first conductive pad and a center line of the second conductive pad in a direction perpendicular to a normal direction of the electronic device. The electronic device as described in claim 1, wherein the distance is greater than 0 and less than or equal to two-sixths of the width of the first conductive pad. The electronic device as described in claim 1, wherein the package structure includes a chip and a protective layer surrounding the chip. The electronic device as described in claim 3, wherein the redistribution structure includes at least one conductive layer and at least one insulating layer, the at least one conductive layer and the at least one insulating layer being disposed in an alternating stacked manner, and the coefficient of thermal expansion of the at least one insulating layer being greater than the coefficient of thermal expansion of the protective layer. The electronic device as described in claim 4, wherein at least one of the at least one conductive layer is a dummy pattern. The electronic device as described in claim 4 further includes an insulating layer disposed on the redistribution structure, wherein the insulating layer contacts the first conductive pad, and the coefficient of thermal expansion of the at least one insulating layer of the redistribution structure is greater than the coefficient of thermal expansion of the insulating layer. The electronic device as claimed in claim 1, wherein the first conductive pad has a first coefficient of thermal expansion, the second conductive pad has a second coefficient of thermal expansion, and the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion. The electronic device as described in claim 1, wherein the top surface of the first conductive pad is recessed. The electronic device as described in claim 1 further includes an insulating layer disposed on the redistribution structure, wherein the first conductive pad protrudes from the top surface of the insulating layer. The electronic device as described in claim 1, wherein the redistribution structure includes a thin-film transistor.