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TWI816561B - Test device, test method and test system - Google Patents

Test device, test method and test system Download PDF

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Publication number
TWI816561B
TWI816561B TW111136660A TW111136660A TWI816561B TW I816561 B TWI816561 B TW I816561B TW 111136660 A TW111136660 A TW 111136660A TW 111136660 A TW111136660 A TW 111136660A TW I816561 B TWI816561 B TW I816561B
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target chip
detection
pin
processor
standby mode
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TW111136660A
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TW202414213A (en
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許詠慶
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新唐科技股份有限公司
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Priority to CN202310750687.XA priority patent/CN117783811A/en
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Abstract

A test device for testing a target chip and providing a test result is provided. The test device includes a transmission interface, a memory, and a processor. The transmission interface is coupled to the target chip. The memory stores a test program code. The processor performs the test program code to obtain the state information of the target chip and generate the test result.

Description

檢測裝置、檢測方法及檢測系統Detection device, detection method and detection system

本發明是關於一種檢測裝置,特別是關於一種檢測一目標晶片的狀態資訊的檢測裝置。The present invention relates to a detection device, and in particular to a detection device for detecting status information of a target wafer.

一般而言,使用者在開發晶片的應用程式的過程中,需要隨時注意晶片的功耗。當晶片的實際功耗與規格參考值有落差時,使用者通常會認為晶片故障或發生異常。然而,大多數的原因只是出自晶片的系統的錯誤設定,或是晶片所連接的外部實體電路具有缺陷。因此,使用者需要花費很長的測試時間,才能找出真正的問題所在。Generally speaking, users need to pay attention to the power consumption of the chip at all times during the process of developing chip applications. When the actual power consumption of the chip is different from the specification reference value, users usually think that the chip is faulty or abnormal. However, most of the causes are simply incorrect system settings of the chip, or defects in the external physical circuitry to which the chip is connected. Therefore, users need to spend a long time testing to find out the real problem.

本發明之一實施例提供一種檢測裝置,用以檢測一目標晶片,並提供一檢測結果。檢測裝置包括一傳輸介面、一記憶體以及一處理器。傳輸介面耦接目標晶片。記憶體儲存一檢測程式碼。處理器執行檢測程式碼,用以讀取目標晶片的狀態資訊,並產生檢測結果。An embodiment of the present invention provides a detection device for detecting a target wafer and providing a detection result. The detection device includes a transmission interface, a memory and a processor. The transmission interface is coupled to the target chip. The memory stores a detection program code. The processor executes the detection program code to read the status information of the target chip and generate detection results.

本發明之另一實施例提供一種檢測系統,包括一目標晶片、一轉換器以及一檢測裝置。目標晶片具有複數接腳及一暫存電路。轉換器耦接目標晶片。檢測裝置透過轉換器,檢測目標晶片,用以產生一檢測結果,並包括一傳輸介面、一記憶體以及一處理器。傳輸介面耦接轉換器。記憶體儲存一檢測程式碼。處理器執行檢測程式碼,用以讀取目標晶片的狀態資訊,並產生結果。Another embodiment of the present invention provides a detection system, including a target wafer, a converter and a detection device. The target chip has a plurality of pins and a temporary storage circuit. The converter is coupled to the target chip. The detection device detects the target chip through the converter to generate a detection result, and includes a transmission interface, a memory and a processor. The transmission interface is coupled to the converter. The memory stores a detection program code. The processor executes the detection program code to read the status information of the target chip and generate results.

本發明之另一實施例提供一種檢測方法,包括重置一目標晶片;判斷目標晶片是否進入一待機模式;當目標晶片進入待機模式時,檢測目標晶片,用以產生檢測結果;輸出檢測結果。Another embodiment of the present invention provides a detection method, which includes resetting a target chip; determining whether the target chip enters a standby mode; when the target chip enters the standby mode, detecting the target chip to generate a detection result; and outputting the detection result.

本發明之檢測方法可經由本發明之檢測系統來實作,其為可執行特定功能之硬體或韌體,亦可以透過程式碼方式收錄於一紀錄媒體中,並結合特定硬體來實作。當程式碼被電子裝置、處理器、電腦或機器載入且執行時,電子裝置、處理器、電腦或機器變成用以實行本發明之檢測裝置或檢測系統。The detection method of the present invention can be implemented through the detection system of the present invention, which is hardware or firmware that can perform specific functions. It can also be recorded in a recording medium through program code and implemented in conjunction with specific hardware. . When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a detection device or detection system for implementing the present invention.

為讓本發明之目的、特徵和優點能更明顯易懂,下文特舉出實施例,並配合所附圖式,做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本發明。另外,實施例中圖式標號之部分重覆,係為了簡化說明,並非意指不同實施例之間的關聯性。In order to make the purpose, features and advantages of the present invention more clearly understandable, embodiments are given below and explained in detail with reference to the accompanying drawings. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. The configuration of each component in the embodiment is for illustration only and is not intended to limit the present invention. In addition, the partial repetition of reference numbers in the figures in the embodiments is for simplifying the description and does not imply the correlation between different embodiments.

第1圖為本發明之檢測系統的示意圖。如圖所示,檢測系統100包括一檢測裝置110、一轉換器120以及一待測電路180。檢測裝置110藉由轉換器120,連接待測電路180,用以週期讀取待測電路180裡的一目標晶片130的狀態資訊,並產生一檢測結果ST。因此,使用者藉由觀察檢測結果ST,便可快速地得知待測電路180的設定是否錯誤。Figure 1 is a schematic diagram of the detection system of the present invention. As shown in the figure, the detection system 100 includes a detection device 110, a converter 120 and a circuit to be tested 180. The detection device 110 is connected to the circuit under test 180 through the converter 120, and is used to periodically read the status information of a target chip 130 in the circuit under test 180, and generate a detection result ST. Therefore, by observing the test result ST, the user can quickly know whether the setting of the circuit under test 180 is wrong.

在一可能實施例中,檢測裝置110更具有電流檢測功能。在此例中,檢測裝置110將所有可能影響目標晶片130功耗的因素都標註在檢測結果ST中。舉例而言,當目標晶片130的某一接腳處於一浮動位準、或是某一接腳的電位狀態不同於該接腳所連接的外部實體電路的電位狀態或是目標晶片130的某項功能被開啟時,目標晶片130的功耗都會受到影響。因此,檢測裝置110在檢測結果ST中,凸顯可能影響目標晶片130功耗的因素。使用者根據檢測結果ST,調整目標晶片130的內部設定(關閉造成功耗的功能)或是調整目標晶片130所連接的外部實體電路的架構。在本實施例中,待測電路180包括目標晶片130及目標晶片130所連接的外部實體電路。在完成調整後,便可排除所有可能影響目標晶片130功耗的原因。接著,使用者重新啟動目標晶片130。此時,目標晶片130的功耗應該小於或等於一預設值。當目標晶片130的功耗未小於或等於一預設值時,表示目標晶片130運作異常。因此,使用者可快速地找出異常目標晶片。In a possible embodiment, the detection device 110 further has a current detection function. In this example, the detection device 110 marks all factors that may affect the power consumption of the target wafer 130 in the detection result ST. For example, when a certain pin of the target chip 130 is at a floating level, or the potential state of a certain pin is different from the potential state of the external physical circuit to which the pin is connected, or when a certain item of the target chip 130 When the function is enabled, the power consumption of the target chip 130 will be affected. Therefore, the detection device 110 highlights factors that may affect the power consumption of the target wafer 130 in the detection result ST. According to the detection result ST, the user adjusts the internal settings of the target chip 130 (turn off functions that cause power consumption) or adjusts the structure of the external physical circuit connected to the target chip 130 . In this embodiment, the circuit to be tested 180 includes a target chip 130 and an external physical circuit connected to the target chip 130 . After completing the adjustment, all possible causes that may affect the power consumption of the target chip 130 can be eliminated. Then, the user restarts the target chip 130 . At this time, the power consumption of the target chip 130 should be less than or equal to a preset value. When the power consumption of the target chip 130 is not less than or equal to a preset value, it indicates that the target chip 130 is operating abnormally. Therefore, the user can quickly find the abnormal target chip.

在一些實施例中,檢測裝置110可能先令目標晶片130進入一待機模式(power-down mode),再找出可能造成目標晶片130耗電的原因,並將耗電原因標註於檢測結果ST中。在此例中,使用者根據檢測結果ST,進行一調整操作,如調整目標晶片130的內部設定或是目標晶片130所連接的外部實體電路的架構。在完成調整後,使用者可能令目標晶片130進入一待機模式(power-down mode),並測量目標晶片130的功耗。由於使用者已事先排除所有影響目標晶片130功耗的因素,故在測量目標晶片130的功耗時,使用者可得到較準確的測量結果。In some embodiments, the detection device 110 may first put the target chip 130 into a standby mode (power-down mode), then find out the possible cause of power consumption of the target chip 130, and mark the power consumption cause in the detection result ST. . In this example, the user performs an adjustment operation based on the detection result ST, such as adjusting the internal settings of the target chip 130 or the structure of the external physical circuit connected to the target chip 130 . After completing the adjustment, the user may put the target chip 130 into a power-down mode and measure the power consumption of the target chip 130 . Since the user has eliminated all factors affecting the power consumption of the target chip 130 in advance, the user can obtain a more accurate measurement result when measuring the power consumption of the target chip 130 .

在一可能實施例中,檢測裝置110包括一記憶體111以及一處理器112。記憶體111儲存一檢測程式碼113。本發明並不限定記憶體111的種類。在一可能實施例中,記憶體111係為一非揮發記憶體。處理器112讀取記憶體111,用以執行檢測程式碼113,並產生一檢測結果ST。在一可能實施例中,處理器112根據檢測程式碼113,產生一命令訊息SCM,用以讀取目標晶片130的狀態資訊。In a possible embodiment, the detection device 110 includes a memory 111 and a processor 112 . The memory 111 stores a detection program code 113 . The present invention is not limited to the type of memory 111. In a possible embodiment, the memory 111 is a non-volatile memory. The processor 112 reads the memory 111 to execute the detection program code 113 and generates a detection result ST. In a possible embodiment, the processor 112 generates a command message SCM according to the detection program code 113 to read the status information of the target chip 130 .

在其它實施例中,處理器112透過命令訊息SCM,命令目標晶片130進入一待機模式。當目標晶片130未進入待機模式時,處理器112週期性地偵測目標晶片130是否進入待機模式。在目標晶片130進入待機模式後,處理器112讀取目標晶片130的內部暫存電路,用以得知目標晶片130的所有接腳的定義,並根據目標晶片130的接腳定義,檢測部分特定接腳的位準,用以產生檢測結果ST。在另一可能實施例中,處理器112根據目標晶片130的內部暫存電路所儲存的資訊,找到可能影響目標晶片130功耗的接腳編號,並得知目標晶片130的某些影響功耗的功能是否關閉。處理器112藉由檢測結果ST,提醒使用者注意目標晶片130的部分接腳以及目標晶片130的內部設定。在一些實施例中,檢測結果ST呈現目標晶片130的每一接腳的腳位資訊及目標晶片130的編號。In other embodiments, the processor 112 commands the target chip 130 to enter a standby mode through the command message SCM. When the target chip 130 does not enter the standby mode, the processor 112 periodically detects whether the target chip 130 enters the standby mode. After the target chip 130 enters the standby mode, the processor 112 reads the internal temporary storage circuit of the target chip 130 to learn the definitions of all pins of the target chip 130, and detects some specific pins according to the pin definitions of the target chip 130. The level of the pin is used to generate the detection result ST. In another possible embodiment, the processor 112 finds the pin numbers that may affect the power consumption of the target chip 130 based on the information stored in the internal temporary storage circuit of the target chip 130, and learns some of the factors that affect the power consumption of the target chip 130. function is turned off. The processor 112 reminds the user to pay attention to some pins of the target chip 130 and the internal settings of the target chip 130 through the detection result ST. In some embodiments, the detection result ST presents the pin information of each pin of the target chip 130 and the number of the target chip 130 .

在一些實施例中,檢測裝置110更包括一顯示裝置114,用以呈現檢測結果ST。本發明並不限定顯示裝置114如何呈現檢測結果ST。在一可能實施例中,顯示裝置114係以一文字方式呈現檢測結果ST。在另一可能實施例中,顯示裝置114係以一視覺化方式呈現檢測結果ST。舉例而言,顯示裝置114可能呈現目標晶片130的外觀。In some embodiments, the detection device 110 further includes a display device 114 for presenting the detection result ST. The present invention does not limit how the display device 114 presents the detection result ST. In a possible embodiment, the display device 114 presents the detection result ST in a text format. In another possible embodiment, the display device 114 presents the detection result ST in a visual manner. For example, display device 114 may present the appearance of target wafer 130 .

在本實施例中,顯示裝置114整合於檢測裝置110中,但並非用以限制本發明。在其它實施例中,顯示裝置114可能獨立於檢測裝置110之外。在一些實施例中,處理器112更耦接一列印裝置(未顯示),如印表機。在此例中,處理器112可能將檢測結果ST作為一報表,並透過列印裝置,列印檢測結果ST。In this embodiment, the display device 114 is integrated into the detection device 110, but this is not intended to limit the invention. In other embodiments, the display device 114 may be independent of the detection device 110 . In some embodiments, the processor 112 is further coupled to a printing device (not shown), such as a printer. In this example, the processor 112 may use the detection result ST as a report, and print the detection result ST through the printing device.

在其它實施例中,檢測裝置110更包括一傳輸介面115。傳輸介面115耦接轉換器120,用以輸出處理器112所產生的命令訊息SCM或是接收轉換器120產生的轉換訊息ST2。本發明並不限定傳輸介面115的種類。在一可能實施例中,傳輸介面115係為一串列介面,如USB介面。In other embodiments, the detection device 110 further includes a transmission interface 115 . The transmission interface 115 is coupled to the converter 120 and is used for outputting the command message SCM generated by the processor 112 or receiving the conversion message ST2 generated by the converter 120 . The present invention does not limit the type of transmission interface 115. In a possible embodiment, the transmission interface 115 is a serial interface, such as a USB interface.

本發明並不限定檢測裝置110的種類。在一可能實施例中,檢測裝置110係為一個人電腦(PC)或是一筆記型電腦(NB)。在此例中,檢測程式碼113係為運行在個人電腦或筆記型電腦上的檢測應用程式。當檢測應用程式被開啟時,檢測裝置110便透過轉換器120,檢測目標晶片130。The present invention is not limited to the type of detection device 110. In a possible embodiment, the detection device 110 is a personal computer (PC) or a notebook computer (NB). In this example, the detection code 113 is a detection application running on a personal computer or laptop. When the detection application is opened, the detection device 110 detects the target chip 130 through the converter 120 .

轉換器120耦接於檢測裝置110與待測電路180之間,用以將檢測裝置110發出的命令訊息SCM轉換成目標晶片130能辨識的訊息,如轉換訊息ST1,再將目標晶片130發出的回覆訊息SRO轉換成檢測裝置110能辨識的訊息,如轉換訊息ST2。本發明並不限定轉換器120的種類。在一可能實施例中,轉換器120係為一在線模擬器(in circuit emulator;ICE)。The converter 120 is coupled between the detection device 110 and the circuit under test 180, and is used to convert the command message SCM sent by the detection device 110 into a message that can be recognized by the target chip 130, such as the conversion message ST1, and then convert the command message SCM sent by the target chip 130. The reply message SRO is converted into a message that can be recognized by the detection device 110, such as the converted message ST2. The present invention does not limit the type of converter 120. In a possible embodiment, the converter 120 is an in circuit emulator (ICE).

在一些實施例中,轉換器120具有傳輸介面121及122。傳輸介面121用以接收來自檢測裝置110的命令訊息SCM,或是輸出轉換訊息ST2予檢測裝置110。在此例中,傳輸介面121的種類相同於傳輸介面151的種類,如均為USB介面。另外,傳輸介面122用以接收來自目標晶片130的回覆訊息SRO,或是輸出轉換訊息ST1予目標晶片130。在一可能實施例中,傳輸介面122係為一除錯介面,如一串行線除錯(Serial Wire Debug;SWD)介面或是一聯合檢測工作群組(Joint Test Action Group;JTAG)標準介面。In some embodiments, the converter 120 has transmission interfaces 121 and 122. The transmission interface 121 is used to receive the command message SCM from the detection device 110 or to output the conversion message ST2 to the detection device 110 . In this example, the type of the transmission interface 121 is the same as the type of the transmission interface 151 , for example, both are USB interfaces. In addition, the transmission interface 122 is used to receive the reply message SRO from the target chip 130 or to output the conversion message ST1 to the target chip 130 . In a possible embodiment, the transmission interface 122 is a debugging interface, such as a Serial Wire Debug (SWD) interface or a Joint Test Action Group (Joint Test Action Group; JTAG) standard interface.

目標晶片130具有接腳131~162以及一暫存電路170。本發明並不限定目標晶片130的接腳數量。在其它實施例中,目標晶片130具有更多或更少的接腳。暫存電路170用以儲存接腳131~162的腳位資訊。在一可能實施例中,目標晶片130更包括一中央處理器(未顯示)。中央處理器根據暫存電路170所儲存的資訊,對接腳131~162的功能進行定義。The target chip 130 has pins 131 to 162 and a temporary storage circuit 170 . The present invention does not limit the number of pins of the target chip 130 . In other embodiments, target wafer 130 has more or fewer pins. The temporary storage circuit 170 is used to store the pin information of the pins 131~162. In a possible embodiment, the target chip 130 further includes a central processing unit (not shown). The central processing unit defines the functions of the pins 131 to 162 based on the information stored in the temporary storage circuit 170 .

舉例而言,接腳131~162之第一部分接腳被配置成通用輸入輸出(General Purpose Input Output;GPIO)的輸入模式(input mode),接腳131~162之第二部分接腳被配置成開汲輸出模式(open-drain output mode),接腳131~162之第三部分接腳被配置成推輓輸出模式(push-pull output mode)的接腳,接腳131~162之第四部分接腳被配置成近似雙向模式(quasi-bidirectional mode)的接腳。因此,檢測裝置110根據暫存電路170所儲存的資訊,便可得知接腳131~162的功能。For example, the first part of pins 131~162 is configured as the input mode of General Purpose Input Output (GPIO), and the second part of pins 131~162 is configured as In open-drain output mode, the third part of pins 131~162 is configured as a pin in push-pull output mode, and the fourth part of pins 131~162 The pins are configured as quasi-bidirectional mode pins. Therefore, the detection device 110 can learn the functions of the pins 131 to 162 based on the information stored in the temporary storage circuit 170 .

在另一可能實施例中,目標晶片130的特定功能(如一上電復位 (power-on reset;POR)功能、或是一低壓偵測(brown-out detector;BOD)功能)是否被開啟的資訊也儲存於暫存電路170中。在其它實施例中,目標晶片130具有類比相關功能,如類比數位轉換器(ADC)、類比比較器(ACMP)、類比放大器(OPA)。在此例中,暫存電路170所儲存的資訊也可表示相對應的類比功能是否開啟。In another possible embodiment, information on whether a specific function of the target chip 130 (such as a power-on reset (POR) function or a brown-out detector (BOD) function) is enabled Also stored in the temporary storage circuit 170. In other embodiments, the target chip 130 has analog-related functions, such as an analog-to-digital converter (ADC), an analog comparator (ACMP), and an analog amplifier (OPA). In this example, the information stored in the temporary storage circuit 170 may also indicate whether the corresponding analog function is enabled.

在一可能實施例中,暫存電路170包括資訊171~173。資訊171用以表示目標晶片130是否已進入待機模式。舉例而言,當目標晶片130未進入待機模式時,資訊171可能具有一第一數值。當目標晶片130進入待機模式後,資訊171具有一第二數值。因此,檢測裝置110根據資訊171,便可得知目標晶片130是否已進入待機模式。In a possible embodiment, the temporary storage circuit 170 includes information 171~173. Information 171 is used to indicate whether the target chip 130 has entered the standby mode. For example, when the target chip 130 does not enter the standby mode, the information 171 may have a first value. When the target chip 130 enters the standby mode, the information 171 has a second value. Therefore, the detection device 110 can know whether the target chip 130 has entered the standby mode according to the information 171 .

資訊172記錄接腳131~162的腳位資訊。當檢測裝置110讀取資訊172後,便可得知接腳131~162的操作模式。處理器112偵測操作於特定模式的接腳的位準。在一些實施例中,特定模式係指GPIO的輸入模式、開汲輸出模式、推輓輸出模式或是近似雙向模式。Information 172 records the pin information of pins 131~162. After the detection device 110 reads the information 172, it can know the operation modes of the pins 131~162. The processor 112 detects the level of the pin operating in a specific mode. In some embodiments, the specific mode refers to the GPIO input mode, open-drain output mode, push-pull output mode or approximate bidirectional mode.

以接腳131為例,假設接腳131操作於GPIO的輸入模式或是開汲輸出模式。在此例中,處理器112判斷接腳131的位準是否為一浮動位準(floating level)。在一可能實施例中,當接腳131所連接的外部實體電路未提供電壓予接腳131時,接腳131的位準為一浮動位準。當接腳131的位準為浮動位準時,表示接腳131的電位異常。由於接腳131的位準異常時,易造成目標晶片130的電流異常,故處理器112在檢測結果ST中,凸顯接腳131的接腳編號。在另一可能實施例中,當接腳131操作於GPIO的推輓輸出模式或是近似雙向模式時,處理器112判斷接腳131的位準是否符合一預設位準。當接腳131的位準不符合一預設位準,表示接腳131的輸入(或輸出)位準(如高位準)不同於相對應的外部實體電路的輸出(或輸入)位準(如低位準)。因此,處理器112在檢測結果ST中,凸顯接腳131的接腳編號。Taking pin 131 as an example, assume that pin 131 operates in the GPIO input mode or the open-drain output mode. In this example, the processor 112 determines whether the level of the pin 131 is a floating level. In a possible embodiment, when the external physical circuit connected to the pin 131 does not provide voltage to the pin 131, the level of the pin 131 is a floating level. When the level of the pin 131 is a floating level, it means that the potential of the pin 131 is abnormal. Since the abnormal level of the pin 131 may easily cause abnormal current in the target chip 130 , the processor 112 highlights the pin number of the pin 131 in the detection result ST. In another possible embodiment, when the pin 131 operates in the push-pull output mode or the approximate bidirectional mode of the GPIO, the processor 112 determines whether the level of the pin 131 meets a preset level. When the level of pin 131 does not meet a preset level, it means that the input (or output) level of pin 131 (such as high level) is different from the output (or input) level of the corresponding external physical circuit (such as low level). Therefore, the processor 112 highlights the pin number of the pin 131 in the detection result ST.

資訊173用以表示目標晶片130的特定功能(如POR功能及BOD功能)是否開啟。處理器112根據資訊173,便可得知目標晶片130的一特定功能是否開啟。在其它實施例中,資訊173更表示目標晶片130的一類比功能是否開啟,如類比數位轉換器、類比比較器、類比放大器。The information 173 is used to indicate whether specific functions of the target chip 130 (such as the POR function and the BOD function) are enabled. Based on the information 173, the processor 112 can know whether a specific function of the target chip 130 is enabled. In other embodiments, the information 173 further indicates whether an analog function of the target chip 130 is enabled, such as an analog-to-digital converter, an analog comparator, and an analog amplifier.

第2圖為本發明之檢測結果的示意圖。在一可能實施例中,檢測結果200可能呈現於第1圖的顯示裝置114中。在此例中,檢測結果200包括目標晶片130的外觀以及每一接腳的狀態資訊。如圖所示,接腳1~4操作於GPIO的輸入模式,故以朝向目標晶片130的箭頭表示接腳1~4的操作模式。接腳5、6、11、12、29-32操作於GPIO的近似雙向模式,故以雙向箭頭表示接腳5、6、11、12、29-32的操作模式。接腳13-16操作於GPIO的開汲輸出模式,故以一水平線段再加一圓點表示接腳13-16的操作模式。接腳17-22操作於GPIO的推輓輸出模式,故接腳17-22的箭頭方向朝外。由於目標晶片130的每一接腳的操作模式係以圖案方式(如箭頭)表示,故使用者立即得知目標晶片130的每一接腳的操作模式。在一些實施例中,檢測結果200更呈現目標晶片130的編號MCU1234。Figure 2 is a schematic diagram of the detection results of the present invention. In a possible embodiment, the detection result 200 may be presented on the display device 114 in FIG. 1 . In this example, the detection result 200 includes the appearance of the target chip 130 and the status information of each pin. As shown in the figure, pins 1 to 4 operate in the GPIO input mode, so the arrows pointing toward the target chip 130 indicate the operation modes of pins 1 to 4. Pins 5, 6, 11, 12, and 29-32 operate in the approximate bidirectional mode of GPIO, so the operating modes of pins 5, 6, 11, 12, and 29-32 are represented by bidirectional arrows. Pins 13-16 operate in the open-sink output mode of GPIO, so a horizontal line segment plus a dot indicates the operating mode of pins 13-16. Pins 17-22 operate in the push-pull output mode of GPIO, so the arrows on pins 17-22 point outward. Since the operation mode of each pin of the target chip 130 is represented by a pattern (such as an arrow), the user immediately knows the operation mode of each pin of the target chip 130 . In some embodiments, the detection result 200 further presents the serial number MCU 1234 of the target wafer 130 .

在一可能實施例中,當處理器112執行檢測程式碼113時,處理器112產生命令訊息SCM。轉換器120轉換命令訊息SCM,用以產生轉換訊息ST1,並將轉換訊息ST1提供予目標晶片130。目標晶片130根據轉換訊息ST1,讀取暫存電路170,用以產生回覆訊息SRO。轉換器120轉換回覆訊息SRO,用以產生轉換訊息ST2,並將轉換訊息ST2提供予處理器112。處理器112根據轉換訊息ST2,產生檢測結果200,並將檢測結果200呈現於顯示裝置114中。In a possible embodiment, when the processor 112 executes the detection program code 113, the processor 112 generates the command message SCM. The converter 120 converts the command message SCM to generate the conversion message ST1, and provides the conversion message ST1 to the target chip 130. The target chip 130 reads the temporary storage circuit 170 according to the conversion message ST1 to generate the reply message SRO. The converter 120 converts the reply message SRO to generate the conversion message ST2, and provides the conversion message ST2 to the processor 112. The processor 112 generates a detection result 200 according to the conversion message ST2, and presents the detection result 200 on the display device 114.

在本實施例中,透過圖形化檢測結果200,使用者可立即判斷出目標晶片130的各接腳的狀態資訊。在其它實施例中,沒有標示箭頭的接腳可能作為電源接腳,用以接收外部電壓,或是輸出電壓予外部裝置。In this embodiment, through the graphical detection results 200, the user can immediately determine the status information of each pin of the target chip 130. In other embodiments, the pins without arrows may serve as power pins for receiving external voltage or outputting voltage to external devices.

另外,檢測結果200除了標示出各接腳的狀態資訊,在一些實施例中,檢測結果200更凸顯(highlight)可能造成目標晶片130耗電的接腳的接腳編號。舉例而言,接腳1~4的操作模式均為GPIO的輸入模式,但接腳1及2的字型不同於接腳3及4的字型,這表示接腳1及2的位準為一浮動位準。由於操作於GPIO的輸入模式的接腳(如接腳1及2)若為浮動位準,則很容易造成目標晶片130耗電。因此,使用者根據檢測結果200所凸顯的接腳1及2,特別注意對應接腳1及2的外部實體電路的設計。舉例而言,使用者可能判斷接腳1是否連接到一上拉電阻或一下拉電阻。In addition, the detection result 200 not only indicates the status information of each pin, but in some embodiments, the detection result 200 further highlights the pin number of the pin that may cause the target chip 130 to consume power. For example, the operation modes of pins 1 to 4 are all GPIO input modes, but the fonts of pins 1 and 2 are different from the fonts of pins 3 and 4, which means that the levels of pins 1 and 2 are A floating level. If the pins operating in the GPIO input mode (such as pins 1 and 2) are at a floating level, it will easily cause the target chip 130 to consume power. Therefore, the user pays special attention to the design of the external physical circuit corresponding to pins 1 and 2 based on the pins 1 and 2 highlighted in the test result 200 . For example, the user may determine whether pin 1 is connected to a pull-up resistor or a pull-down resistor.

在另一可能實施例中,接腳13~16的操作模式均為GPIO的開汲輸出模式,但接腳15及16的字型不同於接腳13及14的字型,這表示接腳15及16的位準為一浮動位準。因此,使用者根據檢測結果200所凸顯的接腳15及16,特別注意相對應的外部實體電路的設計。舉例而言,使用者可能判斷外部實體電路是否具有一上接電阻耦接至接腳15。In another possible embodiment, the operation modes of pins 13 to 16 are all GPIO open-drain output modes, but the fonts of pins 15 and 16 are different from the fonts of pins 13 and 14, which means that pin 15 The level of 16 is a floating level. Therefore, the user pays special attention to the design of the corresponding external physical circuit based on the pins 15 and 16 highlighted in the test result 200 . For example, the user may determine whether the external physical circuit has an upper resistor coupled to pin 15 .

在其它實施例中,接腳17~22的操作模式均為GPIO的推輓輸出模式,但接腳17及18的字型不同於接腳19-22的字型,這表示接腳17及18的位準不同於外部實體電路的位準。舉例而言,接腳17及18可能輸出一高位準,但相對應的外部實體電路卻下拉接腳17及18的位準,使得接腳17及18的位準不等於高位準。由於接腳17及18的輸出位準不同於外部實體電路的輸入位準時,很容易造成漏電(leakage)問題。因此,使用者根據檢測結果200所凸顯的接腳編號(如接腳17及18),特別注意相對應外部實體電路的設計。In other embodiments, the operation mode of pins 17 to 22 is the push-pull output mode of GPIO, but the font of pins 17 and 18 is different from the font of pins 19-22, which means that pins 17 and 18 The level is different from the level of the external physical circuit. For example, pins 17 and 18 may output a high level, but the corresponding external physical circuit pulls down the levels of pins 17 and 18, so that the levels of pins 17 and 18 are not equal to the high level. Since the output levels of pins 17 and 18 are different from the input levels of the external physical circuit, it is easy to cause leakage problems. Therefore, the user pays special attention to the design of the corresponding external physical circuit based on the pin numbers highlighted in the test result 200 (such as pins 17 and 18).

在另一實施例中,接腳29~32的操作模式均為GPIO的近似雙向模式,但接腳29及30的字型不同於接腳31及32的字型,這表示接腳29及30的位準不同於外部實體電路的位準。舉例而言,接腳29及30可能輸出一高位準,但在相對應的外部實體電路上卻量測到低位準。由於接腳29及30的位準狀態不同於外部實體電路的位準狀態時,很容易造成漏電問題。因此,使用者根據檢測結果200所凸顯的接腳編號(如接腳29及30),特別注意相對應外部實體電路的設計。In another embodiment, the operation modes of pins 29 to 32 are all approximate bidirectional modes of GPIO, but the fonts of pins 29 and 30 are different from the fonts of pins 31 and 32, which means that pins 29 and 30 The level is different from the level of the external physical circuit. For example, pins 29 and 30 may output a high level, but measure a low level on the corresponding external physical circuit. Since the level status of pins 29 and 30 is different from the level status of the external physical circuit, it is easy to cause leakage problems. Therefore, the user pays special attention to the design of the corresponding external physical circuit based on the pin numbers highlighted in the test result 200 (such as pins 29 and 30).

在一些實施例中,檢測結果200可能以不同顏色的接腳編號,凸顯可能發生電流異常的接腳編號。舉例而言,由於接腳1、2、15、16、17、18、29及30可能造成異常電流,故接腳1、2、15、16、17、18、29及30的編號以第一顏色(如橘色)呈現。在此例中,由於接腳3-14、19-28、31及32並不會造成目標晶片130的電流異常,故以第二顏色(如黑色)呈現。In some embodiments, the detection result 200 may use pin numbers of different colors to highlight the pin numbers where current abnormality may occur. For example, because pins 1, 2, 15, 16, 17, 18, 29 and 30 may cause abnormal current, the numbers of pins 1, 2, 15, 16, 17, 18, 29 and 30 are numbered with the first Color (such as orange) appears. In this example, since the pins 3-14, 19-28, 31 and 32 will not cause abnormal current in the target chip 130, they are presented in a second color (such as black).

在一些實施例中,當使用者移動游標,令游標指向一特定接腳時,顯示裝置可能呈現一提醒視窗,告知使用者該特定接腳的特性。第3圖為本發明之提醒視窗的示意圖。當使用者將游標指向接腳2時,顯示裝置呈現一提醒視窗300。提醒視窗300可能顯示接腳2的名稱、相關的暫存器的設定值以及對應的時脈頻率與來源等等。In some embodiments, when the user moves the cursor so that the cursor points to a specific pin, the display device may display a reminder window to inform the user of the characteristics of the specific pin. Figure 3 is a schematic diagram of the reminder window of the present invention. When the user points the cursor to pin 2, the display device displays a reminder window 300. The reminder window 300 may display the name of pin 2, the related register setting value, the corresponding clock frequency and source, and so on.

在本實施例中,提醒視窗300提供資訊310、320及330。資訊310可能表示接腳2的相對應功能模組暫存器的設定。資訊320可能表示GPIO設定暫存器的設定。資訊330可能表示接腳2的狀態。在其它實施例中,資訊330的顏色可能不同於資訊310及320,讓使用者更容易注意到接腳2與外部電路的連接關係。In this embodiment, the reminder window 300 provides information 310, 320 and 330. Information 310 may represent the setting of the corresponding function module register of pin 2. Information 320 may represent the settings of the GPIO configuration register. Information 330 may indicate the status of pin 2. In other embodiments, the color of the information 330 may be different from the information 310 and 320 so that the user can more easily notice the connection relationship between the pin 2 and the external circuit.

第4圖為本發明之提醒視窗的另一示意圖。在本實施例中,提醒視窗400與檢測結果200同時呈現。提醒視窗400列出目標晶片130的操作狀態,目前的輸出電壓為3.3V、目前所檢測的目標晶片130的編號(如MCU1234)、以及目標晶片130的操作狀態,如是否進入待機模式。在其它實施例中,提醒視窗400可能列出特定接腳的編號(即可能影響目標晶片130功耗的接腳),如具有浮動位準的接腳1、2、15、16,以及可能發生漏電問題的接腳17、18、29、30。Figure 4 is another schematic diagram of the reminder window of the present invention. In this embodiment, the reminder window 400 and the detection result 200 are presented simultaneously. The reminder window 400 lists the operating status of the target chip 130, the current output voltage is 3.3V, the number of the currently detected target chip 130 (such as MCU 1234), and the operating status of the target chip 130, such as whether to enter standby mode. In other embodiments, the reminder window 400 may list the numbers of specific pins (ie, pins that may affect the power consumption of the target chip 130), such as pins 1, 2, 15, and 16 with floating levels, and may occur Pins 17, 18, 29, and 30 for leakage problems.

第5圖為本發明之提醒視窗的另一示意圖。當使用者將游標指向目標晶片130的編號MCU1234時,顯示裝置呈現一提醒視窗500。在此例中,使用者根據提醒視窗500提供的訊息,得知目標晶片130所開啟的功能。在其它實施例中,提醒視窗500僅呈現可能造成目標晶片130額外耗電的功能,如POR功能。Figure 5 is another schematic diagram of the reminder window of the present invention. When the user points the cursor to the number MCU 1234 of the target chip 130, the display device displays a reminder window 500. In this example, the user learns the functions enabled by the target chip 130 based on the information provided by the reminder window 500 . In other embodiments, the reminder window 500 only displays functions that may cause extra power consumption of the target chip 130, such as the POR function.

在一些實施例中,當一檢測裝置(如第1圖的110)發現目標晶片130的一特定功能(造成目標晶片130額外耗電的功能)被開啟時,檢測裝置在檢測結果200中凸顯目標晶片130的編號MCU1234,如令編號MCU1234的字型(或顏色)不同於接腳編號5~8的字型(或顏色)。因此,使用者根據目標晶片130的字型(或顏色),便可得知影響目標晶片130功耗的功能是否未關閉。在此例中,如果使用者將游標指向目標晶片130的編號MCU1234時,顯示裝置呈現提醒視窗500,用以通知使用者目標晶片130的哪項功能未關閉。In some embodiments, when a detection device (such as 110 in FIG. 1 ) finds that a specific function of the target chip 130 (a function that causes extra power consumption of the target chip 130 ) is turned on, the detection device highlights the target in the detection result 200 The chip 130 is numbered MCU1234. For example, the font (or color) of the number MCU1234 is different from the font (or color) of the pin numbers 5 to 8. Therefore, the user can know whether the function that affects the power consumption of the target chip 130 is not turned off according to the font (or color) of the target chip 130 . In this example, if the user points the cursor to the number MCU 1234 of the target chip 130, the display device displays the reminder window 500 to inform the user which function of the target chip 130 is not closed.

本發明並不限定提醒視窗500所呈現的訊息。在一可能實施例中,提醒視窗500至少呈現目標晶片130所開啟的功能。使用者根據提醒視窗500的訊息,關閉可能造成目標晶片130耗電的特定功能,如POR功能或BOD功能。在另一可能實施例中,提醒視窗500更呈現目標晶片130的部分接腳編號。在此例中,提醒視窗500所呈現的接腳編號係對應可能造成目標晶片130額外耗電的接腳(如1、2、15-18、29、30)。因此,使用者根據提醒視窗500所呈現的接腳編號,檢測相對應的外部實體電路是否設置有上拉或下拉電阻,以避免相對應的接腳的位準為一浮動位準,或是檢測外部實體電路是否影響目標晶片130輸出的電位。The present invention does not limit the message presented in the reminder window 500. In a possible embodiment, the reminder window 500 at least presents the functions enabled by the target chip 130 . According to the message in the reminder window 500, the user closes specific functions that may cause power consumption of the target chip 130, such as the POR function or the BOD function. In another possible embodiment, the reminder window 500 further displays partial pin numbers of the target chip 130 . In this example, the pin numbers displayed in the reminder window 500 correspond to pins (eg, 1, 2, 15-18, 29, 30) that may cause extra power consumption of the target chip 130 . Therefore, the user detects whether the corresponding external physical circuit is equipped with a pull-up or pull-down resistor according to the pin number presented in the reminder window 500, so as to prevent the level of the corresponding pin from being a floating level, or to detect Whether the external physical circuit affects the potential output by the target chip 130 .

由於提醒視窗500呈現了所有可能增加目標晶片130額外耗電的功能及接腳編號,故使用者可根據提醒視窗500,關掉所有影響目標晶片130功耗的功能,並檢查目標晶片130所耦接的外部實體電路,確保目標晶片130的功耗不會受到外部影響。Since the reminder window 500 displays all functions and pin numbers that may increase the extra power consumption of the target chip 130, the user can turn off all functions that affect the power consumption of the target chip 130 according to the reminder window 500, and check the coupling of the target chip 130. The connected external physical circuit ensures that the power consumption of the target chip 130 will not be affected by external influences.

在一些實施例中,檢測裝置可能先命令目標晶片130進入一待機模式。在目標晶片130進入待機模式後,檢測裝置再偵測目標晶片130內部的暫存電路,用以判斷目標晶片130的各接腳的定義,再標示出特定接腳編號(如1、2、15-18、29、30)於檢測結果200中。檢測裝置也透過檢測結果200,告知目標晶片130的部分功能已開啟。使用者可能關閉目標晶片130的部分功能,再重新連接目標晶片130與外部實體電路,並測量目標晶片130的功耗。在此例中,由於目標晶片130的特定功能已關閉,並且外部實體電路已被檢查(是否具有上拉或下拉電阻、是否具有漏電流問題),故當目標晶片130操作於待機模式時,目標晶片130的功耗應低於一預設值。當目標晶片130的功耗不符合預設值時,表示目標晶片130確實異常。然而,當目標晶片130的功耗符合預設值時,表示目標晶片130正常。因此,藉由提醒視窗500可加快使用者檢測目標晶片130的時間,並提高檢測的準確度,降低誤判的機率。In some embodiments, the detection device may first command the target chip 130 to enter a standby mode. After the target chip 130 enters the standby mode, the detection device detects the temporary storage circuit inside the target chip 130 to determine the definition of each pin of the target chip 130, and then marks the specific pin number (such as 1, 2, 15 -18, 29, 30) in the test result 200. The detection device also informs the target chip 130 that some functions of the target chip 130 have been enabled through the detection result 200 . The user may turn off some functions of the target chip 130, then reconnect the target chip 130 with the external physical circuit, and measure the power consumption of the target chip 130. In this example, since the specific function of the target chip 130 has been turned off, and the external physical circuit has been checked (whether it has a pull-up or pull-down resistor, whether it has a leakage current problem), when the target chip 130 operates in the standby mode, the target chip 130 operates in the standby mode. The power consumption of the chip 130 should be lower than a preset value. When the power consumption of the target chip 130 does not meet the preset value, it means that the target chip 130 is indeed abnormal. However, when the power consumption of the target chip 130 meets the preset value, it means that the target chip 130 is normal. Therefore, the reminder window 500 can speed up the time for the user to detect the target chip 130, improve the accuracy of detection, and reduce the probability of misjudgment.

第6圖為本發明之檢測方法的流程示意圖。本發明之檢測方法係用以檢測一目標晶片,得知目標晶片的每一接腳的定義以及目標晶片所開啟的功能。在一可能實施例中,檢測方法所產生的檢測結果標註出目標晶片的特定接腳及目標晶片所開啟的特定功能。被標註出的特定接腳係指在位準異常時,易造成耗電的接腳。舉例而言,易造成耗電的接腳係指操作於GPIO的輸入模式以及操作於GPIO的開汲輸出模式,且位準等於一浮動位準的接腳。另外,操作於GPIO的推輓輸出模式以及操作於GPIO的近似雙向模式,且位準不同於相對應的外部實體電路的位準的接腳也會造成目標晶片的電流異常。在其它實施例中,檢測結果所標註的特定功能係指,目標晶片於待機模式時,易造成額外耗電的功能,如POR功能、BOD功能、類比功能…等。Figure 6 is a schematic flow chart of the detection method of the present invention. The detection method of the present invention is used to detect a target chip and learn the definition of each pin of the target chip and the functions enabled by the target chip. In a possible embodiment, the detection results generated by the detection method mark the specific pins of the target chip and the specific functions enabled by the target chip. The specific pins marked refer to the pins that may easily cause power consumption when the position is abnormal. For example, pins that are prone to power consumption refer to pins that operate in the GPIO input mode and the GPIO open-drain output mode, and the level is equal to a floating level. In addition, pins operating in the push-pull output mode of the GPIO and operating in the approximate bidirectional mode of the GPIO, and whose levels are different from those of the corresponding external physical circuits, will also cause current anomalies in the target chip. In other embodiments, the specific functions marked in the test results refer to functions that easily cause extra power consumption when the target chip is in standby mode, such as POR function, BOD function, analog function, etc.

本發明之檢測方法可以透過程式碼存在。當程式碼被機器載入且執行時,機器變成用以實行本發明之檢測裝置。首先,將檢測裝置與一轉換器連接在一起,並開啟檢測裝置的檢測程式碼(步驟S611)。在一可能實施例中,轉換器可能是一在線模擬器(ICE)。The detection method of the present invention can exist through program code. When the program code is loaded and executed by the machine, the machine becomes a detection device for implementing the invention. First, the detection device is connected to a converter, and the detection program code of the detection device is turned on (step S611). In one possible embodiment, the converter may be an in-circuit emulator (ICE).

接著,藉由轉換器連接一待測電路(步驟S612)。在一可能實施例中,轉換器負責檢測裝置與待測電路之間的通訊。在另一可能實施例中,在連接待測電路後,檢測裝置執行檢測程式碼,用以讀取待測電路上的一目標晶片的狀態資訊。在其它實施例中,在讀取目標晶片的狀態資訊前,檢測裝置先命令目標晶片執行一重置操作。Then, connect a circuit to be tested through a converter (step S612). In a possible embodiment, the converter is responsible for communication between the detection device and the circuit under test. In another possible embodiment, after connecting to the circuit under test, the detection device executes the detection program code to read the status information of a target chip on the circuit under test. In other embodiments, before reading the status information of the target chip, the detection device first commands the target chip to perform a reset operation.

判斷目標晶片是否進入一待機模式(步驟S613)。在一可能實施例中,檢測裝置確認目標晶片裡的一中央處理器是否進入一睡眠模式。在中央處理器進入睡眠模式後,檢測裝置確認目標晶片是否開啟一待機功能。在一可能實施例中,檢測裝置可能讀取目標晶片內部的一暫存電路所儲存的第一資訊,得知目標晶片是否開啟待機功能。當目標晶片未開啟待機功能時,表示目標晶片尚未進入一待機模式,故回到步驟步驟S613,週期讀取目標晶片的狀態。Determine whether the target chip enters a standby mode (step S613). In a possible embodiment, the detection device determines whether a CPU in the target chip enters a sleep mode. After the central processor enters the sleep mode, the detection device confirms whether the target chip has enabled a standby function. In a possible embodiment, the detection device may read the first information stored in a temporary storage circuit inside the target chip to learn whether the target chip has enabled the standby function. When the target chip does not turn on the standby function, it means that the target chip has not yet entered a standby mode, so it returns to step S613 to periodically read the status of the target chip.

當目標晶片開啟待機功能時,表示目標晶片進入待機模式,故開始進行設定檢測(步驟S614)。在一可能實施例中,步驟S614係檢測目標晶片的每一接腳的定義,用以產生一檢測結果。在此例中,步驟S614可能讀取目標晶片內部的一暫存電路所儲存的第二資訊,用以得知目標晶片的每一接腳的定義。在另一可能實施例中,步驟S614更偵測目標晶片的特定功能是否開啟。在此例中,步驟S614根據目標晶片內部的一暫存電路所儲存的第二資訊,得知目標晶片的哪些功能被開啟。When the target chip turns on the standby function, it means that the target chip enters the standby mode, so the setting detection is started (step S614). In a possible embodiment, step S614 is to detect the definition of each pin of the target chip to generate a detection result. In this example, step S614 may read the second information stored in a temporary storage circuit inside the target chip to obtain the definition of each pin of the target chip. In another possible embodiment, step S614 further detects whether a specific function of the target chip is enabled. In this example, step S614 learns which functions of the target chip are enabled based on the second information stored in a temporary storage circuit inside the target chip.

輸出檢測結果(步驟S615)。在一可能實施例中,檢測結果係輸出予一顯示裝置。在此例中,檢測結果可能以圖形化或是文字化方式呈現在顯示裝置上。在另一可能實施例中,藉由一列印工具(如印表機),列印出檢測結果。同樣地,檢測結果可能以圖形化或是文字化方式呈現於一報表中。The detection result is output (step S615). In a possible embodiment, the detection result is output to a display device. In this example, the detection results may be presented on the display device in a graphical or textual manner. In another possible embodiment, the detection results are printed out through a printing tool (such as a printer). Likewise, test results may be presented graphically or textually in a report.

在一些實施例中,檢測結果凸顯至少一特定接腳的接腳編號。在此例中,被凸顯的接腳編號係指該特定接腳的操作狀態屬於GPIO的一輸入模式或是一開汲輸出模式,且該特定接腳的位準為一浮動位準。在另一可能實施例中,被凸顯的接腳編號係指該特定接腳的操作狀態屬於GPIO的一推輓輸出模式或是一近似雙向模式,且該特定接腳的位準不同於相對應的外部實體電路的位準。在此例中,當顯示裝置呈現檢測結果時,如果使用者將一游標指向特定接腳的接腳編號時,顯示裝置更呈現一第一提醒視窗,提醒使用者特定接腳可能造成耗電。使用者根據第一提醒視窗所標註的特定接腳的接腳編號,檢測相對應的外部實體電路(外部實體電路將會連接目標晶片),如檢測外部實體電路是否具有上拉或下拉電阻或是檢測外部實體電路是否具有漏電問題。當外部實體電路具有上拉或下拉電阻時,便可避免外部實體電路連接目標晶片時,造成目標晶片的特定接腳的位準為一浮動位準。In some embodiments, the detection result highlights the pin number of at least one specific pin. In this example, the highlighted pin number means that the operating state of the specific pin belongs to an input mode or an open-drain output mode of the GPIO, and the level of the specific pin is a floating level. In another possible embodiment, the highlighted pin number means that the operating state of the specific pin belongs to a push-pull output mode or an approximate bidirectional mode of GPIO, and the level of the specific pin is different from the corresponding level of the external physical circuit. In this example, when the display device displays the detection result, if the user points a cursor to the pin number of a specific pin, the display device further displays a first reminder window to remind the user that the specific pin may cause power consumption. The user detects the corresponding external physical circuit (the external physical circuit will be connected to the target chip) according to the pin number of the specific pin marked in the first reminder window, such as detecting whether the external physical circuit has a pull-up or pull-down resistor or whether Detect whether the external physical circuit has leakage problems. When the external physical circuit has a pull-up or pull-down resistor, it can avoid causing the level of a specific pin of the target chip to be a floating level when the external physical circuit is connected to the target chip.

在另一可能實施例中,當目標晶片的POR功能及BOD功能之至少一者被開啟時,在檢測結果中,凸顯目標晶片的編號。在此例中,當顯示裝置呈現檢測結果時,如果使用者將游標指向目標晶片的編號時,顯示裝置更呈現一第二提醒視窗,提醒使用者關閉目標晶片的部分功能,以避免額外的耗電。當使用者關閉目標晶片的部分功能後,使用者可能將目標晶片連接一外部實體電路,並操作目標晶片於一待機模式。由於目標晶片的耗電功能已關閉,故目標晶片的功耗應符合一預設值。當目標晶片的功耗不符合一預設值時,表示目標晶片異常。因此,使用者可藉由量測目標晶片的功耗,準確地得知目標晶片是否異常。In another possible embodiment, when at least one of the POR function and the BOD function of the target chip is turned on, the number of the target chip is highlighted in the detection result. In this example, when the display device displays the detection result, if the user points the cursor to the number of the target chip, the display device further displays a second reminder window to remind the user to turn off some functions of the target chip to avoid additional consumption. Electricity. After the user turns off some functions of the target chip, the user may connect the target chip to an external physical circuit and operate the target chip in a standby mode. Since the power consumption function of the target chip has been turned off, the power consumption of the target chip should comply with a preset value. When the power consumption of the target chip does not meet a preset value, it indicates that the target chip is abnormal. Therefore, the user can accurately know whether the target chip is abnormal by measuring the power consumption of the target chip.

本發明之檢測方法,或特定型態或其部份,可以以程式碼的型態存在。程式碼可儲存於實體媒體,如軟碟、光碟片、硬碟、或是任何其他機器可讀取(如電腦可讀取)儲存媒體,亦或不限於外在形式之電腦程式產品,其中,當程式碼被機器,如電腦載入且執行時,此機器變成用以參與本發明之檢測裝置。程式碼也可透過一些傳送媒體,如電線或電纜、光纖、或是任何傳輸型態進行傳送,其中,當程式碼被機器,如電腦接收、載入且執行時,此機器變成用以參與本發明之檢測裝置。當在一般用途處理單元實作時,程式碼結合處理單元提供一操作類似於應用特定邏輯電路之獨特裝置。The detection method of the present invention, or a specific type or part thereof, may exist in the form of program code. Program code can be stored in physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (such as computer-readable) storage media, or computer program products that are not limited to external forms, among which, When the program code is loaded and executed by a machine, such as a computer, the machine becomes a detection device for participating in the present invention. The program code can also be transmitted through some transmission media, such as wires or cables, optical fiber, or any transmission type. When the program code is received, loaded and executed by a machine, such as a computer, the machine becomes a party to participate in the process. Invented detection device. When implemented in a general purpose processing unit, the program code combined with the processing unit provides a unique device that operates similarly to application specific logic circuits.

除非另作定義,在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外,除非明白表示,詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致,而不應解釋為理想狀態或過分正式之語態。雖然“第一”、“第二”等術語可用於描述各種元件,但這些元件不應受這些術語的限制。這些術語只是用以區分一個元件和另一個元件。Unless otherwise defined, all terms (including technical and scientific terms) used herein belong to the common understanding of a person with ordinary knowledge in the technical field to which this invention belongs. In addition, unless explicitly stated, the definition of a word in a general dictionary should be interpreted as consistent with its meaning in articles in the relevant technical field, and should not be interpreted as an ideal state or an overly formal tone. Although terms such as "first," "second," and the like may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾。舉例來說,本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above in terms of preferred embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. . For example, the systems, devices or methods described in the embodiments of the present invention may be implemented as physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

100:檢測系統 110:檢測裝置 120:轉換器 130:目標晶片 111:記憶體 112:處理器 113:檢測程式碼 114:顯示裝置 115、121、122:傳輸介面 131~162:接腳 170:暫存電路 171~173、310、320、330:資訊 180:待測電路 ST、200:檢測結果 SCM:命令訊息 ST1、ST2:轉換訊息 SRO:回覆訊息 300、400、500:提醒視窗 S611~S615:步驟 100:Detection system 110:Detection device 120:Converter 130:Target chip 111:Memory 112: Processor 113: Detection code 114:Display device 115, 121, 122: Transmission interface 131~162: Pin 170: Temporary circuit 171~173, 310, 320, 330: Information 180: Circuit to be tested ST, 200: test results SCM: command message ST1, ST2: Conversion message SRO: Reply message 300, 400, 500: reminder window S611~S615: steps

第1圖為本發明之檢測系統的示意圖。 第2圖為本發明之檢測結果的示意圖。 第3圖為本發明之提醒視窗的示意圖。 第4圖為本發明之提醒視窗的另一示意圖。 第5圖為本發明之提醒視窗的另一示意圖。 第6圖為本發明之檢測方法的流程示意圖。 Figure 1 is a schematic diagram of the detection system of the present invention. Figure 2 is a schematic diagram of the detection results of the present invention. Figure 3 is a schematic diagram of the reminder window of the present invention. Figure 4 is another schematic diagram of the reminder window of the present invention. Figure 5 is another schematic diagram of the reminder window of the present invention. Figure 6 is a schematic flow chart of the detection method of the present invention.

100:檢測系統 100:Detection system

110:檢測裝置 110:Detection device

120:轉換器 120:Converter

130:目標晶片 130:Target chip

111:記憶體 111:Memory

112:處理器 112: Processor

113:檢測程式碼 113: Detection code

114:顯示裝置 114:Display device

115、121、122:傳輸介面 115, 121, 122: Transmission interface

131~162:接腳 131~162: Pin

170:暫存電路 170: Temporary circuit

171~173:資訊 171~173:Information

180:待測電路 180: Circuit to be tested

ST:檢測結果 ST: test results

SCM:命令訊息 SCM: command message

ST1、ST2:轉換訊息 ST1, ST2: Conversion message

SRO:回覆訊息 SRO: Reply message

Claims (10)

一種檢測裝置,用以檢測一目標晶片,並提供一檢測結果,該檢測裝置包括:一傳輸介面,耦接該目標晶片;一記憶體,儲存一檢測程式碼;以及一處理器,執行該檢測程式碼,用以讀取該目標晶片的狀態資訊,並產生該檢測結果;其中該處理器命令該目標晶片進入一待機模式,在該目標晶片進入該待機模式後,該處理器讀取該目標晶片的狀態資訊。 A detection device is used to detect a target chip and provide a detection result. The detection device includes: a transmission interface coupled to the target chip; a memory to store a detection program code; and a processor to execute the detection Program code for reading status information of the target chip and generating the detection result; wherein the processor commands the target chip to enter a standby mode, and after the target chip enters the standby mode, the processor reads the target Chip status information. 如請求項1之檢測裝置,其中該處理器讀取該目標晶片的一暫存電路所儲存的一第一資訊,用以判斷該目標晶片是否進入該待機模式,當該目標晶片進入該待機模式時,該處理器讀取該暫存電路所儲存的一第二資訊,用以讀取該目標晶片的每一接腳的腳位資訊。 The detection device of claim 1, wherein the processor reads a first information stored in a temporary storage circuit of the target chip to determine whether the target chip enters the standby mode. When the target chip enters the standby mode, At this time, the processor reads a second information stored in the temporary storage circuit to read the pin information of each pin of the target chip. 如請求項2之檢測裝置,其中當該目標晶片未進入該待機模式時,該處理器週期性讀取該暫存電路所儲存的該第一資訊,直到該目標晶片進入該待機模式。 Such as the detection device of claim 2, wherein when the target chip does not enter the standby mode, the processor periodically reads the first information stored in the temporary storage circuit until the target chip enters the standby mode. 如請求項2之檢測裝置,更包括:一顯示裝置,呈現該檢測結果,其中該檢測結果呈現該目標晶片的每一接腳的腳位資訊及該目標晶片的編號。 The detection device of claim 2 further includes: a display device to present the detection result, wherein the detection result presents the pin information of each pin of the target chip and the number of the target chip. 如請求項4之檢測裝置,其中該處理器根據該暫存電路所儲存的該第二資訊,判斷該目標晶片的每一接腳是否操作於一特定模式,當該目標晶片的一特定接腳操作於一特定模式時,該 處理器根據該特定接腳的位準,決定是否在該檢測結果中,凸顯該特定接腳。 The detection device of claim 4, wherein the processor determines whether each pin of the target chip operates in a specific mode based on the second information stored in the temporary storage circuit. When a specific pin of the target chip When operating in a specific mode, the The processor determines whether to highlight the specific pin in the detection result based on the level of the specific pin. 如請求項5之檢測裝置,其中:當該特定接腳操作於一通用輸入輸出的一輸入模式或是一開汲輸出模式,且該特定接腳為一浮動位準時,該處理器在該檢測結果中,凸顯該特定接腳;以及當該特定接腳操作於該通用輸入輸出的一推輓輸出模式或是一近似雙向模式,且該特定接腳的位準不符合一預設值時,該處理器在該檢測結果中,凸顯該特定接腳。 The detection device of claim 5, wherein: when the specific pin operates in an input mode of a general-purpose input and output or an open-drain output mode, and the specific pin is a floating level, the processor detects In the results, the specific pin is highlighted; and when the specific pin operates in a push-pull output mode or an approximate bidirectional mode of the general-purpose input and output, and the level of the specific pin does not meet a preset value, The processor highlights the specific pin in the detection result. 一種檢測方法,包括:重置一目標晶片;命令該目標晶片進入一待機模式;判斷該目標晶片是否進入一待機模式;當該目標晶片進入該待機模式時,檢測該目標晶片,用以產生一檢測結果;以及輸出該檢測結果。 A detection method includes: resetting a target chip; commanding the target chip to enter a standby mode; determining whether the target chip enters a standby mode; when the target chip enters the standby mode, detecting the target chip to generate a Test results; and output the test results. 如請求項7之檢測方法,其中當一顯示裝置的一游標指向該特定接腳的接腳編號時,該顯示裝置更呈現一提醒視窗。 For example, the detection method of claim 7, wherein when a cursor of a display device points to the pin number of the specific pin, the display device further displays a reminder window. 如請求項7之檢測方法,其中檢測該目標晶片的步驟更包括:判斷該目標晶片的一上電復位功能及一低壓偵測功能之至少一者是否開啟;以及當該上電復位功能及該低壓偵測功能之至少一者開啟時,在該檢測結果中,凸顯該目標晶片的編號。 As claimed in claim 7, the step of detecting the target chip further includes: determining whether at least one of a power-on reset function and a low-voltage detection function of the target chip is turned on; and when the power-on reset function and the low-voltage detection function are turned on; When at least one of the low-voltage detection functions is turned on, the number of the target chip is highlighted in the detection result. 一種檢測系統,包括:一目標晶片,具有複數接腳及一暫存電路;一轉換器,耦接該目標晶片;以及一檢測裝置,透過該轉換器,檢測該目標晶片,用以產生一檢測結果,並包括:一傳輸介面,耦接該轉換器;一記憶體,儲存一檢測程式碼;以及一處理器,執行該檢測程式碼,用以讀取該目標晶片的狀態資訊,並產生該檢測結果;其中該處理器命令該目標晶片進入一待機模式,在該目標晶片進入該待機模式後,該處理器讀取該目標晶片的狀態資訊。 A detection system includes: a target chip having a plurality of pins and a temporary storage circuit; a converter coupled to the target chip; and a detection device that detects the target chip through the converter to generate a detection The result includes: a transmission interface coupled to the converter; a memory storing a detection program code; and a processor executing the detection program code to read the status information of the target chip and generate the Detection result; wherein the processor commands the target chip to enter a standby mode, and after the target chip enters the standby mode, the processor reads status information of the target chip.
TW111136660A 2022-09-28 2022-09-28 Test device, test method and test system TWI816561B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105589762A (en) * 2014-08-19 2016-05-18 三星电子株式会社 Memory Devices, Memory Modules And Method For Correction
US20170168910A1 (en) * 2015-12-14 2017-06-15 Samsung Electronics Co., Ltd. Multichip debugging method and multichip system adopting the same
US20190205244A1 (en) * 2011-04-06 2019-07-04 P4tents1, LLC Memory system, method and computer program products
TW202018509A (en) * 2018-11-05 2020-05-16 英業達股份有限公司 Sas connector conduction detection system and method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190205244A1 (en) * 2011-04-06 2019-07-04 P4tents1, LLC Memory system, method and computer program products
CN105589762A (en) * 2014-08-19 2016-05-18 三星电子株式会社 Memory Devices, Memory Modules And Method For Correction
US20170168910A1 (en) * 2015-12-14 2017-06-15 Samsung Electronics Co., Ltd. Multichip debugging method and multichip system adopting the same
TW202018509A (en) * 2018-11-05 2020-05-16 英業達股份有限公司 Sas connector conduction detection system and method thereof

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