TWI895865B - Method for packaging chip, chip packaging structure, and terminal device - Google Patents

Abstract

A method for packaging chip that utilizes a principle of thermal expansion and contraction. First, a chip assembly is placed at a first temperature to cause a deformation piece of the chip assembly to shrink. Then the chip component is placed in a groove of a circuit board, and a position of the chip component in the groove is adjusted at a second temperature, so that pins of the chip correspond to a circuit layer of the circuit board, and the position of the chip component in the groove is relatively fixed. Reflow soldering is performed at a third temperature to connect the conductive paste to the circuit board and the chip, and the deformation piece expands and squeezes the chip in a high temperature environment to increase the reliability of the connection between the chip and the circuit board. A chip packaging structure and a terminal device are further provided.

Description

Chip packaging method, chip packaging structure and terminal device

This application relates to the field of chip packaging, and more particularly to a chip packaging method, a chip packaging structure, and a terminal device.

Chips are often embedded within circuit boards to minimize the size of the chip package. The thickness of the chip typically aligns with the stacking direction of the circuit board. During the chip packaging process, vias are drilled into the circuit board to electrically connect the board and chip. If the chip has dense solder pins, high precision is required for both drilling and plating the vias, otherwise soldering problems can easily occur.

Therefore, it is necessary to provide a chip packaging method with good soldering to solve the above problems.

A chip packaging method comprises the following steps: forming a recess in a circuit board, the recess comprising a first sidewall and a second sidewall disposed opposite each other; the circuit board comprising a circuit layer, the circuit layer exposed to the first sidewall; providing a chip assembly, the chip assembly comprising a chip, a conductive paste, and a deformable sheet, the deformable sheet and the conductive paste being located on opposite surfaces of the chip; exposing the chip assembly to a first temperature to shrink the deformable sheet; placing the chip assembly with the shrunk deformable sheet in the recess, with the deformable sheet spaced apart from the second sidewall; at a second temperature, the conductive paste contacts the circuit layer, and the deformable sheet contacts the second sidewall; and exposing the circuit board and chip assembly to a third temperature for reflow soldering to electrically connect the conductive paste and the circuit layer, wherein the third temperature is greater than the second temperature, and the second temperature is greater than the first temperature.

In some embodiments of the present application, the chip packaging method further includes: filling the groove with a packaging layer; forming a through hole in the circuit board and removing the deforming sheet, exposing the surface of the chip facing away from the conductive paste to the through hole; and forming a conductive layer in the through hole.

In some embodiments of the present application, the thermal expansion coefficient of the deformable sheet is greater than the thermal expansion coefficient of the circuit board.

In some embodiments of the present application, the material of the deformable sheet is selected from one of zinc, copper, lead and aluminum.

In some embodiments of the present application, the groove is recessed along a first direction, and the conductive paste, chip, and deformable sheet are stacked along a second direction, with the first direction and the second direction being perpendicular to each other.

In some embodiments of this application, after the chip assembly with the deformable plate contracted is placed in the groove, the distance between the deformable plate and the second sidewall is greater than or equal to 0.56 μm.

In some embodiments of the present application, the first temperature is less than or equal to 0°C, and/or the third temperature is greater than or equal to 220°C.

A chip package structure includes a circuit board, a chip, a conductive paste, and a conductive layer. The circuit board includes a circuit layer and a dielectric layer stacked along a first direction; the chip includes a body and solder pins, which are arranged on the surface of the body along a second direction; the conductive paste is arranged between the circuit layer and the solder pins along the second direction to electrically connect the solder pins and the circuit layer; and the conductive layer penetrates the circuit board along the first direction and connects to the surface of the body facing away from the solder pins.

In some embodiments of the present application, the first direction and the second direction are perpendicular to each other.

A terminal device includes a chip package structure.

A chip packaging method employs the principle of thermal expansion and contraction. The chip assembly is first placed in a low-temperature environment (i.e., a first temperature) to contract the deformable tabs within the chip assembly. The chip assembly is then placed in a circuit board with a recess. At room temperature (i.e., a second temperature), the position of the chip assembly within the recess is adjusted so that the chip's solder pins align with the circuit board's wiring layer, securing the chip assembly relative to the recess. Reflow soldering is then performed at a high-temperature environment (i.e., a third temperature) to connect the conductive paste to the circuit board and chip. The deformable tabs expand in the high-temperature environment, compressing the chip to enhance the reliability of the connection between the chip and the circuit board.

200: Terminal device

100: Chip packaging structure

10: Circuit board

11: Dielectric layer

13: Line layer

15: Groove

152: First side wall

154: Second side wall

156:Bottom wall

20: Chipset

21: Chip

212: Body

214: Soldering pins

23: Transformer

25: Conductive paste

252: The First Gap

254: The Second Gap

30: Packaging layer

40: Copper clad plate

41:Circuit substrate

50: Through hole

51: conductive layer

T1: First temperature

T2: Second temperature

T3: The third temperature

L1: First Direction

L2: Second Direction

Figure 1 is a schematic cross-sectional view of a circuit board after a groove is formed according to an embodiment of this application.

Figure 2 is a schematic diagram of the process of placing the chip assembly at a first temperature to shrink the deformable sheet in this embodiment of the application.

Figure 3 is a schematic cross-sectional view of the shrunken chip assembly shown in Figure 2 after it is placed in the groove of Figure 1.

Figure 4 is a schematic cross-sectional view of the circuit board and chip assembly shown in Figure 3 after being placed at a second temperature to allow the deformable piece to recover its size.

Figure 5 is a schematic cross-sectional view of the circuit board and chip assembly shown in Figure 4 after being subjected to reflow soldering at a third temperature.

FIG6 is a schematic cross-sectional view of the reflow-processed circuit board and chip assembly shown in FIG5 after being exposed to a second temperature.

Figure 7 is a schematic cross-sectional view of the groove shown in Figure 6 and the surface of the circuit board after a packaging layer is formed.

Figure 8 is a schematic cross-sectional view of the package layer and circuit board shown in Figure 7 after a copper clad plate is provided on their surfaces.

Figure 9 is a schematic cross-sectional view of the circuit board shown in Figure 8 after a through hole is formed.

Figure 10 is a schematic cross-sectional view of the chip package structure obtained after forming a conductive layer in the through-hole of Figure 9 and fabricating circuits on the copper-clad substrate.

Figure 11 is a schematic diagram of a portion of the chip package structure shown in Figure 10.

Figure 12 is a schematic diagram of the structure of the terminal device provided in an embodiment of this application.

To facilitate a clearer understanding of the aforementioned objectives, features, and advantages of this application, the following detailed description is provided with reference to the accompanying drawings and specific embodiments. It should be noted that, where non-conflicting, the embodiments of this application and the features therein may be combined. The following description provides numerous specific details to facilitate a full understanding of this application. The embodiments described represent only a portion of the embodiments of this application, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of this application without inventive effort are also protected by this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application relates. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and/or" used herein includes all and any combinations of one or more of the related listed items.

In the various embodiments of this application, for the purpose of description and not limitation, the term "connected" used in this patent specification and scope is not limited to physical or mechanical connections, whether direct or indirect. Terms such as "upper," "lower," "above," "below," "left," and "right" are used solely to indicate relative positional relationships. When the absolute position of the described objects changes, the relative positional relationship also changes accordingly.

Referring to Figures 1 to 11, this embodiment of the present application provides a chip packaging method, which may include the following steps:

Step S1: Referring to Figure 1 , a groove 15 is formed on the circuit board 10. The groove 15 includes a first sidewall 152 and a second sidewall 154 disposed opposite each other. The circuit board 10 includes a circuit layer 13, which is exposed at the first sidewall 152.

The circuit board 10 can be a flexible board, a rigid board, or a rigid-flexible board. The circuit board 10 can also include a dielectric layer 11. A circuit layer 13 and the dielectric layer 11 are stacked along a first direction L1. The circuit layer 13 and the dielectric layer 11 can have one or more layers. In this embodiment, the circuit layer 13 has multiple layers.

The groove 15 is recessed along the first direction L1 and includes a bottom wall 156. The bottom wall 156 connects the first sidewall 152 and the second sidewall 154. The first sidewall 152, the second sidewall 154, and the bottom wall 156 enclose the groove 15. In this embodiment, the first sidewall 152 and the second direction L2 are both parallel to the first direction L1, and the bottom wall 156 is parallel to the second direction L2. The second direction L2 may be perpendicular to the first direction L1.

The groove 15 can be formed by laser cutting or mechanical drilling.

Step S2: Referring to Figure 2, a chip assembly 20 is provided. The chip assembly 20 includes a chip 21, a conductive paste 25, and a deformable sheet 23. The deformable sheet 23 and the conductive paste 25 are located on opposite surfaces of the chip 21. The chip assembly 20 is placed at a first temperature T1 to cause the deformable sheet 23 to contract.

Chip 21 includes a body 212 and multiple solder pins 214. Solder pins 214 are located on the surface of body 212. Deformable tabs 23 are located on the surface of body 212 facing away from solder pins 214. Conductive paste 25 is located on the surface of each solder pin 214. The position of the circuit layer 13 exposed in recess 15 corresponds to the position of the multiple conductive pastes 25. This is equivalent to recess 15 being recessed along a first direction L1. The conductive paste 25, chip 21, and deformable tabs 23 are stacked along a second direction L2, with the first and second directions L1 and L2 being perpendicular to each other.

The material of the conductive paste 25 can be solder paste, silver paste, etc.

The thermal expansion coefficient of deformable plate 23 is greater than that of circuit board 10 to ensure that the plate expands more than the circuit board 10 in subsequent high-temperature environments. Deformable plate 23 can be made of materials such as zinc, copper, lead, and aluminum. In this embodiment, deformable plate 23 is made of zinc, which has a thermal expansion coefficient of 3.6× ^{10-5K -1} .

In this embodiment, the chip assembly 20 is cooled from a second temperature T2 to a first temperature T1, where the second temperature T2 is greater than the first temperature T1. The second temperature T2 can be room temperature, such as 15°C-35°C, i.e., a temperature that does not change due to external influences. When the chip assembly 20 is at the first temperature T1, the deformable piece 23 contracts relative to the state at the second temperature T2, and the volume of the deformable piece 23 decreases. The first temperature T1 can be less than or equal to 0°C, such as -25°C, -40°C, or -50°C. In this embodiment, the chip assembly 20 is placed in a low temperature environment of -50°C to cause the deformable piece 23 to contract. The chip 21 is typically made of silicon, which has a thermal expansion coefficient of 2.4×10 ^-6 K ^-1 , which is smaller than the thermal expansion coefficient of the deformable plate 23 . Therefore, the shrinkage of the chip 21 at the first temperature T1 can be ignored.

Step S3: Referring to Figure 3 , the chip assembly 20 with the deformable sheet 23 retracted is placed in the recess 15 . The deformable sheet 23 can be spaced apart from the second sidewall 154 , i.e., a first gap 252 is defined between the deformable sheet 23 and the second sidewall 154 .

After the chip assembly 20 has been at the first temperature T1 for a period of time, it is placed in the groove 15, with the conductive paste 25 facing the first sidewall 152 and the deformable sheet 23 facing the second sidewall 154. Along the second direction L2, the width of the chip assembly 20 is smaller than the width of the groove 15. After the deformable sheet 23 is retracted and placed in the groove 15, a certain distance can be maintained between the deformable sheet 23 and the second sidewall 154. The chip assembly 20 can be adjusted in the groove 15 so that the conductive paste 25 aligns with the circuit layer 13.

In some embodiments, the distance between the deformable piece 23 and the second sidewall 154 is greater than or equal to 0.56 μm, so as to facilitate adjustment of the position of the chip assembly 20 in the groove 15.

Step S4: Referring to Figure 4, at the second temperature T2, the conductive paste 25 contacts the circuit layer 13, and the deformable sheet 23 contacts the second sidewall 154.

In this embodiment, after chip assembly 20 is placed in recess 15, chip assembly 20 and circuit board 10 are placed in a second temperature environment (T2) of 24°C. The deformable tabs 23 return to their original dimensions. At this point, both sides of chip assembly 20 are connected to circuit board 10. Specifically, the conductive paste 25 contacts the circuit layer 13, and the deformable tabs 23 contact the second sidewall 154. This facilitates alignment of the conductive paste 25 with the circuit layer 13, minimizing or preventing displacement of chip assembly 20 within recess 15.

If the chip assembly 20 is placed directly into the groove 15 without being exposed to the first temperature T1, it will be difficult to adjust the position of the chip assembly 20 within the groove 15, making it difficult to ensure that the conductive paste 25 aligns with the circuit layer 13. This can easily lead to poor soldering, such as bridging and cracking, during the subsequent soldering process. If the width of the groove 15 along the second direction L2 is increased, the chip assembly 20 will easily shift within the groove 15. Even if the conductive paste 25 is pre-aligned with the circuit layer 13, the chip assembly 20 will easily shift within the groove 15 during subsequent steps, causing the positions of the conductive paste 25 and the circuit layer 13 to deviate, resulting in poor soldering.

Step S5: Referring to Figure 5, the circuit board 10 and chip assembly 20 are placed in a third temperature T3 for reflow soldering to electrically connect the conductive paste 25 and the circuit layer 13. The third temperature T3 is greater than the second temperature T2.

The third temperature T3 can be adjusted according to the type of conductive paste 25. For example, in some embodiments, the third temperature T3 can be greater than 220°C. For example, in this embodiment, the third temperature T3 is 250°C.

At the third temperature T3, the deformable sheet 23 and the circuit board 10 expand due to heat. Since the thermal expansion coefficient of the deformable sheet 23 is greater than that of the circuit board 10, the expansion amplitude of the deformable sheet 23 is greater than that of the circuit board 10. That is, along the second direction L2, the width of the groove 15 is smaller than the width of the chip assembly 20. After the deformable sheet 23 expands, it squeezes the deformable sheet 23. The forces acting on both sides of the chip 23, namely the deformable plate 23, compress the chip 21, causing it to move toward the first sidewall 152. Simultaneously, the conductive paste 25 melts at the third temperature T3 and connects to the circuit layer 13. The deformable plate 23 compresses the chip 21, creating a tighter connection between the conductive paste 25 and the circuit layer 13. Using conductive paste 25 to directly connect the solder pins 214 and the circuit layer 13 eliminates the drilling and plating required to achieve conductivity in related technologies.

Referring again to Figures 4 and 5 , when the chip assembly 20 is exposed to a second temperature T2, the width of the deformable sheet 23 along the first direction L1 is smaller than the width of the body 212, and the projection of the deformable sheet 23 lies within the projection of the body 212. This allows the deformable sheet 23 to expand when the chip assembly 20 is exposed to a third temperature T3. This prevents the deformable sheet 23 from excessively deforming along the first direction L1, potentially causing the chip assembly 20 to move along the first direction L1 and misalignment between the conductive paste 25 and the circuit layer 13.

Referring to Figure 6 , when the temperature drops, for example, to the second temperature T2, the conductive paste 25 solidifies and electrically connects the chip 21 and the circuit board 10. The chip assembly 20 moves a certain distance toward the first sidewall 152 relative to its pre-reflow position. The deformable tab 23 contracts and is spaced from the second sidewall 154, creating a second gap 254 between the deformable tab 23 and the second sidewall 154. Because the chip assembly 20 moves a certain distance toward the first sidewall 152 after the reflow process, the width of the second gap 254 along the second direction L2 is greater than the width of the first gap 253.

Step S6: Please refer to Figure 7 and fill the encapsulation layer 30 in the groove 15.

The packaging layer 30 can be filled between the conductive paste 25 and the first sidewall 152, and between the deformable sheet 23 and the second sidewall 154. The packaging layer 30 can also be located on the surface of the circuit board 10 where the groove 15 is formed.

Step S7: Referring to Figure 8, a copper clad plate 40 is provided on the surface of the packaging layer 30 facing away from the circuit board 10.

In some embodiments, additional layers can be added based on the number of circuit layers 13 required. The copper-clad substrate 40 is subsequently used to fabricate the circuit substrate 41 to achieve the addition of circuit layers 13. In some embodiments, step S7 can also be omitted.

Step S8: Referring to Figures 9, 10, and 11, a through hole 50 is formed through the copper clad plate 40 and the circuit board 10. The deformed sheet 23 is removed, and the surface of the chip 21 facing away from the conductive paste 25 is exposed to the through hole 50. A conductive layer 51 is formed in the through hole 50.

A conductive layer 51 can be formed in the through-hole 50 by electroplating to obtain the chip package structure 100. The conductive layer 51 is connected to the surface of the chip 21 to achieve heat dissipation. The conductive layer 51 can also be connected to the circuit board 10 and the circuit layer 13 in the circuit substrate 41 to achieve electrical conductivity.

The entire surface of the body 212 facing away from the solder pins 214 can be connected to the conductive layer 51, increasing the heat dissipation area and thus improving the heat dissipation effect.

By packaging the chip 21 in the circuit board 10 with the solder pins 214 facing the second direction L2, the width of the chip package structure 100 along the second direction L2 can be reduced, making the chip package structure 100 suitable for environments with a smaller installation space along the second direction L2.

During the process of forming the conductive layer 51, circuits are also fabricated on the copper-clad substrate 40 to form the circuit substrate 41.

Referring to FIG. 10 , this embodiment of the present application further provides a chip package structure 100 . The chip package structure 100 may include a circuit board 10 , a chip 21 , a conductive paste 25 , and a packaging layer 30 . The conductive paste 25 connects the chip 21 and the circuit board 10 , and the packaging layer 30 packages the chip 21 within the circuit board 10 .

The circuit board 10 includes a dielectric layer 11 and a circuit layer 13, which are stacked along a first direction L1. A chip 21 includes a body 212 and solder pins 214. The solder pins 214 and body 212 are arranged along a second direction L2 and disposed on the surface of the body 212. Conductive paste 25 is disposed between the circuit layer 13 and the solder pins 214 to electrically connect the solder pins 214 to the circuit layer 13. The circuit layer 13, conductive paste 25, and chip 21 are arranged along the second direction L2. The first direction L1 and the second direction L2 may be perpendicular to each other. A packaging layer 30 is placed between the chip 21 and the circuit board 10.

The circuit board 10 also includes a conductive layer 51. A through hole 50 extends through the circuit board 10 along a first direction L1. The conductive layer 51 is connected to the surface of the body 212 facing away from the solder pins 214. The conductive layer 51 can be used to quickly transfer heat generated by the chip 21 during operation.

Referring to FIG. 12 , this embodiment of the present application further provides a terminal device 200 , which includes a chip package structure 100 . The terminal device 200 may be a mobile phone, a camera, a drone, a computer, a video camera, or the like. In this embodiment, the terminal device 200 is a mobile phone.

The chip packaging method provided by the embodiment of the present application adopts the principle of thermal expansion and contraction. First, the chip assembly 20 is placed in a low temperature environment (i.e., a first temperature T1) to shrink the deformable piece 23 in the chip assembly 20. Then, the chip assembly 20 is placed in a circuit board 10 with a groove 15, and the position of the chip assembly 20 in the groove 15 is adjusted in a normal temperature environment (i.e., a second temperature T2) so that the chip assembly 20 shrinks. The solder pins 214 of the sheet 21 correspond to the wiring layer 13 of the circuit board 10, thereby fixing the chip assembly 20 in the groove 15. Reflow soldering is performed in a high-temperature environment (i.e., the third temperature T3) to connect the conductive paste 25 to the circuit board 10 and the chip 21. The deformable sheet 23 expands in the high-temperature environment, squeezing the chip 21 and increasing the reliability of the connection between the chip 21 and the circuit board 10.

The above embodiments are intended only to illustrate the technical solutions of this application and are not intended to be limiting. Although this application is described in detail with reference to the above preferred embodiments, persons skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application may be made without departing from the spirit and scope of the technical solutions of this application.

10: Circuit board 11: Dielectric layer 13: Circuit layer 15: Groove 152: First sidewall 154: Second sidewall 156: Bottom wall 20: Chip assembly 21: Chip 212: Body 214: Solder pins 23: Deformable sheet 25: Conductive paste T3: Third temperature L1: First direction L2: Second direction

Claims (8)

A chip packaging method comprises: forming a groove in a circuit board, the groove being recessed along a first direction and comprising a first sidewall and a second sidewall disposed opposite each other; the circuit board comprising a circuit layer, the circuit layer being exposed at the first sidewall; providing a chip assembly, the chip assembly comprising a chip, a conductive paste, and a deformable sheet, the deformable sheet and the conductive paste being positioned on opposite surfaces of the chip, the conductive paste, the chip, and the deformable sheet being stacked in a second direction, the first direction and the second direction being perpendicular to each other; exposing the chip assembly to a first temperature to cause the deformable sheet to contract; placing the chip assembly with the deformable sheet contracted in the groove, the deformable sheet being spaced apart from the second sidewall; at the second temperature, the conductive paste contacts the circuit layer, and the deformable sheet contacts the second sidewall; and The circuit board and the chip assembly are placed at a third temperature for reflow soldering to electrically connect the conductive paste and the circuit layer, wherein the third temperature is greater than the second temperature, and the second temperature is greater than the first temperature. The chip packaging method of claim 1, further comprising: filling the recess with a packaging layer; forming a through hole in the circuit board and removing the deformable sheet, exposing a surface of the chip facing away from the conductive paste to the through hole; and forming a conductive layer in the through hole. A chip packaging method as described in claim 1 or 2, wherein the thermal expansion coefficient of the deformable sheet is greater than the thermal expansion coefficient of the circuit board. A chip packaging method as described in claim 3, wherein the material of the deformable sheet is selected from one of zinc, copper, lead and aluminum. A chip packaging method as described in claim 1 or 2, wherein after the chip assembly with the deformable plate contracted is placed in the groove, the distance between the deformable plate and the second side wall is greater than or equal to 0.56 μm. A chip packaging method as described in claim 1 or 2, wherein the first temperature is less than or equal to 0°C, and/or the third temperature is greater than or equal to 220°C. A chip package structure comprises: a circuit board comprising a circuit layer and a dielectric layer stacked along a first direction; a chip comprising a body and solder pins, the solder pins and the body being arranged along a second direction and disposed on a surface of the body; a conductive paste disposed between the circuit layer and the solder pins to electrically connect the solder pins and the circuit layer, the circuit layer, the conductive paste, and the chip being arranged along the second direction, the first and second directions being perpendicular to each other; and a conductive layer extending through the circuit board along the first direction and connected to a surface of the body facing away from the solder pins. A terminal device, wherein the terminal device includes the chip package structure as described in claim 7.