TWI892900B - Memory and memory test method - Google Patents

Abstract

A memory test system includes a memory and a test equipment. The test equipment is coupled to the memory, and is configured to generate a first test signal to test a minimum input high voltage level of the memory. The test equipment is configured to generate a second test signal to test a maximum input low voltage level of the memory. The test equipment is configured to generate a voltage compliance mask range of the memory according to the minimum input high voltage level and the maximum input low voltage level. The test equipment is configured to generate an input signal into the memory according to the voltage mask range of the memory.

Description

Memory and memory testing methods

This case involves an electronic system and chip testing method. More specifically, it involves a memory testing system and memory testing method.

Existing test equipment inputs data signals or commands to the memory's receiver, which then performs operations based on the data signals or commands. When the data signals or commands reach the receiver's data voltage mask range, the receiver generates an error signal, preventing the receiver from performing operations based on the data signals or commands.

Therefore, the above technology still has many defects, and it is necessary for practitioners in this field to develop other suitable memory testing systems and memory testing methods.

One aspect of this invention relates to a memory. The memory includes a receiver coupled to an external system. The receiver performs the following operations: receives a plurality of test signals from the external system. The memory further performs the following operations: generates a plurality of test results corresponding to each of the plurality of test signals; and outputs the plurality of test results to the external system, so that the external system determines a voltage mask range of the memory based on the plurality of test results.

Another aspect of this case involves a memory testing method. The memory testing method includes the following steps: receiving a plurality of test signals through a memory; generating a plurality of corresponding test results through the memory in response to each of the plurality of test signals; and outputting the plurality of test results through the memory to an external system connected to the memory, so that the external system determines a voltage mask range of the memory based on the plurality of test results.

In view of the aforementioned shortcomings and deficiencies of the existing technology, this case provides a memory test system and memory test method. The memory test system and memory test method of this case analyze the voltage mask range of the memory to ensure that the input signal is within the normal operating voltage range of the memory based on the voltage mask range.

The following diagrams and detailed descriptions clearly illustrate the spirit of this invention. After understanding the embodiments of this invention, anyone with ordinary skill in the art can make changes and modifications based on the techniques taught in this invention without departing from the spirit and scope of this invention.

The terms used herein are for describing specific embodiments only and are not intended to be limiting of the present invention. Singular forms such as "a," "the," "this," and "the" as used herein also include plural forms.

The terms "include", "including", "have", "contain", etc. used in this document are open terms, meaning including but not limited to.

Unless otherwise noted, the terms used in this document generally have the ordinary meanings they possess in the art, within the context of this application, and in the specific context. Certain terms used to describe this application are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art regarding the description of this application.

FIG1 is a circuit block diagram of a memory test system 100 according to some embodiments of the present invention. In some embodiments, as shown in FIG1 , the memory test system 100 includes a memory 110 and a test machine 120. The test machine 120 is coupled to the memory 110.

In some embodiments, the test machine 120 is configured to generate a first test signal to test the minimum input high voltage level of the memory 110. The test machine 120 is configured to generate a second test signal to test the maximum input low voltage level of the memory 110. The test machine 120 is configured to generate a voltage mask range (not shown) for the memory 110 based on the minimum input high voltage level and the maximum input low voltage level. The voltage mask range will be illustrated and described in the following description and figures. The test machine 120 is configured to generate an input signal to the memory 110 based on the voltage mask range of the memory 110.

In some embodiments, the memory 110 includes dynamic random access memory (DRAM).

In some embodiments, the memory 110 includes a receiver 111. The receiver 111 is coupled to the test apparatus 120 and configured to receive an input high voltage level of a first test signal. The receiver 111 determines whether the input high voltage level reaches a voltage mask range of the receiver 111, thereby determining whether to generate a first error signal.

In some embodiments, if the input high voltage level contacts the voltage mask range of the receiver 111, the receiver 111 is configured to output a first error signal. If the input high voltage level does not contact the voltage mask range of the receiver 111, the test apparatus 120 is further configured to continue adjusting the input high voltage level.

In some embodiments, the receiver 111 is further configured to receive an input low voltage level of a second test signal and to determine whether the input low voltage level reaches a voltage mask range, thereby determining whether to generate a second error signal.

In some embodiments, referring to FIG. 1 , if the input low voltage level reaches the voltage mask range of the receiver 111, the receiver 111 is further configured to output a second error signal. If the input low voltage level does not reach the voltage mask range of the receiver 111, the tester 120 is configured to continue adjusting the input low voltage level.

In some embodiments, the first test signal, the second test signal, and the input signal are different. In some embodiments, the first error signal and the second error signal are different.

In some embodiments, to facilitate understanding of the operation of memory testing system 100 for testing memory 110 in FIG. 1 , please refer to FIG. 1 through FIG. 4 . FIG. 2 is a schematic flow diagram illustrating the steps of a memory testing method 200 according to some embodiments of the present invention. FIG. 3 and FIG. 4 are schematic diagrams illustrating test signals generated by memory testing system 100 according to some embodiments of the present invention. In some embodiments, memory testing method 200 includes steps 210 through 260. These steps are described in detail in the following paragraphs.

In step 210 , a first test signal is input to the memory by a test machine. In some embodiments, referring to FIG. 1 to FIG. 3 , the first test signal S1 is input to the receiver 111 of the memory 110 by a test machine 120 .

In step 220, the memory is used to test a minimum input high voltage level of the memory according to the first test signal.

In some embodiments, referring to FIG. 1 to FIG. 3 , the memory 110 is used to test the minimum input high voltage level VIH(min) of the receiver 111 of the memory 110 according to the first test signal S1.

It should be noted that the first test signal S1 is a test signal that, when a normal signal is input into receiver 111, can be recognized by receiver 111 as the minimum input high voltage level VIH(min). VIH (High-level input voltage) is defined as the minimum input voltage that can be recognized as a high level by a logic gate. In other words, the high level of a normal signal has a range of values due to circuit errors. To ensure that the high level of a normal signal remains within the high-level voltage range recognized by the logic gate, a preliminary test is usually required.

In some embodiments, the test equipment 120 adjusts the input high voltage level VIH(default) of the first test signal S1 to search for the minimum input high voltage level VIH(min) of the receiver 111 of the memory 110 .

In some embodiments, the receiver 111 determines whether the input high voltage level VIH(default) has reached the voltage mask range R of the compliance mask M. If the input high voltage level VIH(default) has reached the voltage mask range R of the receiver 111, the receiver 111 outputs a first error signal. The first error signal indicates that the first test signal S1 has reached the compliance mask M, thereby determining the upper limit of the compliance mask M of the receiver 111.

Furthermore, if the input high voltage level VIH (default) does not reach the voltage mask range R of the receiver 111, the test equipment 120 continues to adjust the input high voltage level VIH (default).

For example, the input high voltage level VIH(default) has a value of 910 millivolts (mV). By adjusting the voltage shift ΔX using test equipment 120 to bring VIH(default) into the voltage mask range R of receiver 111, receiver 111 will output a first error signal. At this point, the first test signal S1 is adjusted to the first target signal S1'. The voltage shift ΔX is 25 millivolts (mV). The minimum input high voltage level VIH(min) is 885 millivolts (mV).

In step 230, a second test signal is input to the memory via the test machine.

In some embodiments, referring to FIG. 1 , FIG. 2 , and FIG. 4 , the second test signal S2 is input to the receiver 111 of the memory 110 by the test equipment 120 .

In step 240, the memory is used to test the maximum input low voltage level of the memory according to the second test signal.

In some embodiments, referring to FIG. 1 , FIG. 2 , and FIG. 4 , the maximum input low voltage level VIL(max) of the memory 110 is tested according to the second test signal S2 .

It should be noted that the second test signal S2 is a test signal that, when a normal signal is input to receiver 111, receiver 111 will recognize the normal signal as the maximum input low-voltage level VIL(max). VIL (low-level input voltage) is defined as the maximum input voltage that can be recognized as a low-level by a logic gate. In other words, the low-level of a normal signal has a range of values due to circuit errors. To ensure that the low-level of a normal signal remains within the low-level voltage range recognized by the logic gate, a preliminary test is usually required.

In some embodiments, the test equipment 120 adjusts the input low voltage level VIL(default) of the second test signal S2 to search for the maximum input low voltage level VIL(max) of the receiver 111 of the memory 110 .

In some embodiments, referring to Figures 1, 2, and 4, receiver 111 determines whether the input low voltage level VIL(default) touches the voltage mask range R of the compliance mask M of receiver 111 of memory 110. If the input low voltage level VIL(default) touches the voltage mask range R of receiver 111, receiver 111 outputs a second error signal. The second error signal indicates that the second test signal S2 has touched the compliance mask M, thereby indicating the lower limit of the compliance mask M of receiver 111.

Furthermore, if the input low voltage level VIL(default) does not touch the voltage mask range R of the receiver 111, the test equipment 120 continues to adjust the input low voltage level VIL(default).

For example, the voltage value of the input low voltage level VIL(default) is 730 millivolts (mV). By adjusting the voltage shift ΔY by the test machine 120 to adjust the input low voltage level VIL(default) to the voltage mask range R of the receiver 111, the receiver 111 will output a second error signal. At this time, the second test signal S2 is adjusted to the second target signal S2'. The voltage shift ΔY is 25 millivolts (mV). The maximum input low voltage level VIL(max) is 755 millivolts (mV). It should be noted that the voltage shift ΔX and the voltage shift ΔY can be the same or different.

In step 250, a voltage mask range of the memory is generated by a test machine according to the minimum input high voltage level and the maximum input low voltage level.

In some embodiments, referring to FIG. 1 to FIG. 4 , the test equipment 120 generates a voltage mask range R of the memory 110 according to a minimum input high voltage level VIH(min) and a maximum input low voltage level VIL(max).

For example, according to steps 220 and 240 above, the minimum input high voltage level VIH(min) is 885 millivolts (mV). The maximum input low voltage level VIL(max) is 755 millivolts (mV). The test equipment 120 subtracts the minimum input high voltage level VIH(min) from the maximum input low voltage level VIL(max) to obtain a voltage mask range R of 130 millivolts (mV) for the receiver 111 of the memory 110.

In step 260, a test machine generates an input signal to the memory according to the voltage mask range of the memory.

In some embodiments, referring to FIG. 1 to FIG. 4 , the test equipment 120 generates an input signal to the memory 110 according to a voltage mask range R of a receiver 111 of the memory 110 in compliance with a mask M.

In some embodiments, the test equipment 120 generates an input signal according to the voltage mask range R of the compliance mask M, thereby preventing the high level and the low level of the input signal from touching the voltage mask range R of the compliance mask M of the receiver 111.

According to the aforementioned embodiments, this case provides a memory test system and a memory test method. The memory test system and the memory test method of this case analyze the voltage mask range of the memory receiver to ensure that the high and low levels of the input signal or command are within the normal operating voltage range of the memory receiver based on the voltage mask range.

Although this invention is disclosed above with detailed embodiments, it does not exclude other feasible embodiments. Therefore, the scope of protection of this invention shall be determined by the scope of the attached patent application, and shall not be limited by the aforementioned embodiments.

It is clear to those skilled in the art that various modifications and improvements can be made to this application without departing from the spirit and scope of this application. Based on the aforementioned embodiments, all modifications and improvements made to this application are also covered by the scope of protection of this application.

100: Memory test system 110: Memory 111: Receiver 120: Test equipment 200: Method 210-260: Steps VIH (default): Input high voltage level VIH (min): Minimum input high voltage level R: Voltage mask range M: Compliance mask S1: First test signal S1’: First target signal ΔX: Voltage shift VIL (default): Input low voltage level VIL (max): Maximum input low voltage level S2: Second test signal S2’: Second target signal ΔY: Voltage shift

The present invention can be better understood by referring to the embodiments described in the following paragraphs and the following figures: Figure 1 is a schematic circuit block diagram of a memory test system according to some embodiments of the present invention; Figure 2 is a schematic flow diagram of the steps of a memory test method according to some embodiments of the present invention; Figure 3 is a schematic diagram of test signals generated by the memory test system according to some embodiments of the present invention; and Figure 4 is a schematic diagram of test signals generated by the memory test system according to some embodiments of the present invention.

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100:Memory test system

110: Memory

111: Receiver

120: Testing machine

Claims (10)

A memory includes: A receiver coupled to an external system; The receiver performs the following operations: Receives a plurality of test signals from the external system; The memory further performs the following operations: Generates a plurality of test results corresponding to each of the test signals; and Outputs the test results to the external system, so that the external system determines a voltage mask range of a compliance mask of the receiver of the memory based on the test results. The memory device of claim 1, wherein the external system is a test machine. The memory as described in claim 1, wherein the test signals include a first test signal and a second test signal, wherein the first test signal is used to test a minimum input high voltage level of the voltage mask range of the memory, and wherein the second test signal is used to test a maximum input low voltage level of the voltage mask range of the memory. The memory of claim 3, wherein the receiver is configured to: receive a first level of the first test signal during a first period; and determine whether to output a first error signal as one of the test results based on the minimum input high voltage level of the voltage mask range and the first level of the first test signal during the first period. The memory as described in claim 4, wherein if the first level contacts the voltage mask range, the receiver is configured to output the first error signal, and if the first level does not contact the voltage mask range, the external system is further configured to continue to lower the first level. The memory of claim 4, wherein the receiver is configured to: receive a second level of the second test signal during a second period; and determine whether to output a second error signal as one of the test results based on the maximum input low voltage level of the voltage mask range and the second level of the second test signal during the second period. The memory as described in claim 6, wherein if the second level contacts the voltage mask range, the receiver is further configured to output the second error signal, and if the second level does not contact the voltage mask range, the external system is configured to continue to increase the second level. The memory of claim 6, wherein the first period and the second period do not overlap. The memory of claim 1, wherein the external system is further configured to generate an input signal based on the voltage mask range to transmit the input signal to the memory. A memory testing method includes: receiving a plurality of test signals through a memory; generating a plurality of corresponding test results by the memory in response to each of the test signals; and outputting the test results through the memory to an external system connected to the memory, so that the external system determines a voltage mask range of a compliance mask of a receiver of the memory based on the test results.