TW200301487A - Non-volatile memory and method for operating a non-volatile memory - Google Patents

Abstract

A non-volatile memory (10) comprises an array (12) of individual memory cells (14), a read circuit (16) and an identifying circuit (18). The memory cells (14) of the array are individually capable of having a threshold voltage programmed or erased to an intended level within a range, the range being between range boundary levels. The read circuit (16) is reads the range of an actual threshold voltage of memory cells, and the identifying circuit (18) identifies any memory cells (14) having an intended level in at least one predefined range that each has it's actual threshold voltage shifted beyond a predetermined margin level within the range different from the range boundary levels.

Description

200301487

发明 Description of the invention (the description of the invention should state: the technical field to which the invention belongs, the prior art, the content of the present invention is about non-volatile memory and operating methods, especially about a microcontroller single unit; MCU) Memory. In the prior art, independent non-volatile or flash memory is faced with each time a READ operation is performed, a wipeable electric block that loses electric charge during a read operation of its floating gate depends on whether it loses charge. In order to achieve these effects, its technology and actual inspection and repair or repair. In U.S. Patent No. 5,963,473, a non-volatile random computing circuit of an encapsulated non-volatile memory unit generates an output to indicate the cumulative disturbing effect in the array caused by a partially-performed erase operation. U.S. Patent No. 6,3 1 4,027 describes a flash memory device that uses a division algorithm as a state machine to prevent excessive circuits of flash memory cells. First, the threshold voltage of the selected cell is checked in advance. It is higher than the maximum value corresponding to the erased state range. If at least one of the voltages is higher than the pre-verified voltage, a high-voltage production voltage is gradually increased according to a predetermined voltage level. The critical voltage of the element is equal to or less than the pre-verification f, the embodiment, and the schematic description.) Make a non-volatile memory 7G (microcontroller disturbing effect, which causes the removal or programmable block to be loaded. Can be erased or programmed Method. It is possible to include a programmable or erasable memory device with an erasing control circuit that disturbs a first part in the other columns of the array, using a specific erasing. Erasing. Whether the erasing controls A critical generator that reaches a predetermined target threshold voltage selection unit generates a body of electricity. If all selected single voltages are selected, the high-voltage output is 200301487.

(2) The generator generates a continuous mains voltage. U.S. Patent No. 6,049,899 discloses a semiconductor non-volatile memory including a memory cell array, and the memory cells of the array can each have a programmable or erasable to achieve a memory range supported by the memory system. Planned threshold voltage. The monitoring component invoked in at least one of a plurality of predefined events of the memory system identifies one or more cells whose critical voltage offset exceeds a predetermined marginal level of its planned level, and writes The input component writes the shifted critical voltage back to its planned level. Memory cells are individually programmable into two or more states to store more than one bit in each cell. Such a memory system is an independent memory controlled by a memory controller. The plurality of predefined events of the memory system include memory operations on a portion of the memory array, which tend to disrupt cells within that portion of the memory array. The above U.S. Patent No. 5,963,473 / U.S. Patent No. 6,3 1 4,027 / U.S. Patent No. 6,049,8 99 are disclosed to address the major issues during a stylization or erase operation. There is no difference between data or executable code. The access status is unknown, and the memory controller does not know whether an application can be stopped to repair the disturbed unit. U.S. Patent No. 6,21 6,251 describes a microcontroller with a CPU and a memory including a memory array. A large part of the array is used to contain the functional data of the CPU, but the array also contains parity information for one or a few rows of memory content. Once the array is written with persistent data and / or software, a parity controller will generate an initial parity value that is related to the contents of the memory array. After generating the initial parity data, the -6-200301487 (3) Description of the invention In certain parity check events, the parity controller sometimes generates the current parity from the data stored in the array, and the parity part of the array Compared. If errors are detected, corrective actions can be taken to extend the product's reliable life. The microcontroller is able to detect a data error after it has occurred, but it cannot identify memory cells that may experience data errors in the near future. The present invention seeks to provide an MCU that mitigates the aforementioned disadvantages. The MCU needs a non-volatile memory, in which an expected data error in the memory is detected before it actually occurs, so that the planned normal operation of the MCU can continue. SUMMARY OF THE INVENTION According to the present invention, it utilizes a configuration set in a microcontroller, which is different from the configuration in a separate non-volatile memory. The microcontroller has a processor, a memory (EEPROM, FLASH) RAM, I / O timers, PWM, and other peripherals (possibly including a state machine). The processor's main software knows exactly the state of the state machine and the application. The processor can rely on the application program to interrupt the process in order to repair a disturbed memory unit. The state machine can be used and triggered from the processor for a repair cycle of an NVM unit. In the context of a user program, the state machine can use the processor's free cycles to perform memory test procedures. Regarding an NVM read operation, the present invention is mainly directed to a read disturbing effect (charge loss, data retention problem) caused by a read operation in a normal use operation mode. If during the reading operation, the charge is lost due to different effects, the application can be warned, and the user software can determine 200301487

(4) determine what corrective action should be taken. If, during this read operation, the threshold voltage deviation of a floating gate unit exceeds a predetermined marginal level of its planned level, it will endanger an application, making it possible to perform incorrect instruction encoding and fail to operate correctly. An example and definition of a typical two-state NVM unit embedded in a microcontroller will now be described. Programmable or erasable bi-state NVM units tend to become a naturally neutral state over time. Cell charges can drift, causing data retention issues. The definition of the erasable and programmable state of the NVM unit is dependent on the design. For example, the erasable state may be a logical "1" represented by a typical 5 volts to 2.6 volts, and the programmable state of the unit may be a logical "0" represented by a typical 0 to 2.5 volts. The unit's natural neutral state can be 1.5 volts, which in this case corresponds to a logical "0". A typical failure mechanism of the NVM unit will now be described. Under the specified worst-case conditions, a unit has a typical life of 15 years. But charges can be lost more quickly due to certain unpredictable circumstances. For example, electron traps in oxide isolation or defects in oxides will cause a loss of charge, which can accelerate with temperature. The invention realizes the early detection of the critical charge shift of the cell and provides a decision procedure to determine whether the critical voltage of the cell needs to be repaired or repaired. Using a simple comparator technology, early detection of the loss of charge that causes a dangerous offset can prevent incorrect operation of the program or prevent changes in the stored data. The present invention proposes an improved method to detect during reading Out-of-range units (disturbing units) during instruction execution. The present invention proposes different methods and algorithms for monitoring units over time 200301487 ⑸ \ ^ /, on · \ h. In a specific embodiment of the present invention, an individual unit or a group of units can be monitored to check whether the voltage of the unit is shifted to represent a dangerous logic value change (inverted from "1" to "0", or vice versa) ). The early voltage / current is tested to check whether the offset exceeds a number of specified reference levels within a predefined period. Depending on the technology used, this reference level point can be used to determine if a bit-level offset is out of control and if necessary actions such as rewriting or patching are required. The critical unit can only be judged by the NVM test software to avoid a fatal error in a running application. This monitoring can be done on the fly or using a separate memory test. A memory test can be run in the context of an application, or it can be performed during the power-on or power-off phase of a device. Such an NVM test algorithm can use a state machine parallel to a processor. A state machine can use cycles where the processor does not access the memory. In the case of real-time monitoring during the instruction access of the processor by the processor, the state machine can still be selectively activated in parallel with the processor to control the memory. When needed, the state machine can perform a repair procedure. BRIEF DESCRIPTION OF THE DRAWINGS An exemplary embodiment of the present invention will be described below with reference to the drawings, in which: FIG. 1 shows a schematic block diagram of a preferred embodiment of a non-volatile memory according to the present invention; FIG. 2 shows A schematic voltage diagram related to the non-volatile memory of FIG. 1; FIG. 3 shows a schematic block diagram of different preferred embodiments of the non-volatile memory according to the present invention; -9- 200301487

FIG. 4 shows a schematic block diagram of another preferred embodiment of a non-volatile memory according to the present invention; FIG. 5 shows a schematic block diagram of another preferred embodiment of a non-volatile memory according to the present invention Figures; and Figure 6 shows an unintended block diagram of a preferred embodiment of a method according to the present invention. Referring to FIG. 1, an embodiment shows a non-volatile memory (non-volatile memory; NV M) 10, which includes an array 12 of individual memory cells 14, a reading circuit 16 and a Identification circuit 1 8. FIG. 2 shows a schematic diagram of voltage V versus time t. The memory cells 1 4 of the array 12 may each have a threshold voltage Vt that is programmable or erasable to reach a planned level within a range. A range is defined between the range boundary levels and represents a logical value. Here, the boundary level is V. The range 22 to VB represents a logical "0", and the range 24 between the boundary level ¥ 3 and Vi represents a logical "1". The threshold voltage Vt is initially programmed as Vs and shifts with time along the curve 26. If no event is added to the memory cell 14, such as reprogramming, erasing, or a defect, the threshold voltage Vt eventually reaches a natural value, which is denoted here as the natural voltage VN. The threshold voltage Vt passes the boundary voltage VB as it shifts along the curve 26, which constitutes a critical error because it is now interpreted as a different logical value. Such errors must be prevented. The present invention introduces monitoring of the critical voltage Vt at an extra marginal level VM. At this extra marginal level VM, the read circuit 16 (here at time TR) reads the range of the actual threshold voltage, which is correct range -10- 200301487 (7) I turn the description on the next page 2 4 as planned The range that is correctly interpreted when its logical value is "1". However, reaching VM indicates that the boundary voltage VB can be reached quickly. According to the invention, this flag is used to take measures to prevent the boundary voltage VB from being reached. At time TR, the identification circuit 18 identifies the memory cell, its planned level is within a predefined range 2 4, and its actual threshold voltage Vt shifts beyond a predetermined range different from the range boundary levels VB and Vi. Marginal Level VM. An erasable memory cell in a two-level cell usually does not need to be monitored because it does not change its logic ® value when it is shifted to the natural voltage vN. However, in the case of a multilevel cell to which the present invention is also applicable, several ranges can be monitored. Hereinafter, the present invention will be described using specific embodiments, in which the MCU includes a processing unit and an embedded NVM. This application of the invention is particularly advantageous for several reasons. The MCU is integrated into a typical device with a design life of 10 to 15 years. The NVM usually contains MCU software and device data, and requires that the above-mentioned critical errors do not occur during its use. An example is an MCU for automotive engine control, where a Φ boundary error in the MCU software can cause the execution of an incorrect command or interrupt the processor, or where a critical error in the device's data can cause the valve to open at the wrong time or Shut down, resulting in immediate engine danger. FIG. 3 shows a memory in the form of an MCU 30 according to the present invention, which includes a processing unit processor 32 and an embedded NVM 34. The NVM 34 further includes an array 35, a comparator 38, and a control logic 40 of the memory unit 36, which includes an adjustable DC power supply to supply the NVM 34. The memory cells of array 3 5 can each have a programmable or erasable by up to -11-200301487

的 A threshold voltage to a planned level in a range between the range boundary levels. The processor 32 controls the control logic 40, which is adapted to apply an adjustable test read potential to at least one bit line of the memory cells of the array during a read operation. Comparator 3 8 receives the analog signal on line 4 2 (preferably for several units in parallel), compares each signal with an internal voltage, and outputs a digital signal to the bus coupled to processor 3 2 44 〇

The processor 3 2, the comparator 38, and the control logic 40 simultaneously form a reading circuit for reading an actual critical voltage range of the memory unit; and an identification circuit for identifying a planned level at least one preset Any memory cell that defines a range, the actual threshold voltage offset of each memory cell exceeds a predetermined marginal level within the range that is different from the range boundary level. In the array 35, the memory cells 36 are coupled to bit lines (not shown), which allows selection by applying a predefined voltage to the selected bit line for a planned operation (such as a read operation). Address a different memory unit 3 4.

According to the present invention, the adjustable DC power supply within the control logic 40 allows a normal read potential to be applied to the bit line to perform a normal read operation. Referring to Figs. 1 and 2, this configuration operates as a read circuit in which the comparator 38 receives an analog signal representing the actual threshold voltage Vt read by the memory cell 34. The comparator then discriminates at the boundary voltage VB to interpret the logical value "0" or "1". According to the present invention, the adjustable DC power supply within the control logic 40 also allows a test read potential to be applied to the bit line to perform a test read operation. This configuration operates as a recognition circuit where the comparator 3 8 receives a representative -12- 200301487

The analog signal of the modified voltage is lower than the threshold voltage Vt of the memory cell 34. Next, the comparator performs discrimination on a discriminator voltage in the comparator. The voltage is still unchanged, equal to VB but representing a threshold voltage discrimination at the boundary level VM to interpret the logical value "0" or "1" . Thus, by performing a test read operation under a test read condition different from the normal read condition, and by reading the NVM and comparing the results by using the normal read potential and the test read potential at the same time, here In the processor 32, it can be detected whether the actual threshold voltage of the unit under inspection is in a range higher than Vb but lower than VM. FIG. 4 shows another specific embodiment of the memory according to the present invention, which is in the form of an MCU 50 including a processing unit processor 52 and an embedded NVM 54. The NVM 54 further includes an array 55 of a memory unit 56, a comparator 58 and a control logic 60. The memory cells of the array 55 may individually have a threshold voltage that is programmable or erasable to reach a planned level within a range between the range boundary levels. The processor 5 2 controls the control logic 6 0, and the control logic 60 controls the comparator 5 8 via the control line 6 1 to compare the actual threshold voltage of the memory unit with several different voltages, which is a discrimination with normal read operation. The voltage VB is compared with two different test voltages VMi, VM2 which are different from a discrimination voltage VB of a normal read operation. Both the test voltages VMi and VM2 allow similar discrimination of VMs as described above, but this example also illustrates the additional advantages of the two test voltages VM1 and VM2. These analog voltages are applied by the control logic 60 to the comparator 58. Comparator 5 8 receives the analog signal on line 62 (preferably performed in parallel with several units), compares each signal with an internal voltage, and outputs a number -13-200301487

The bit signals are connected to a bus 64 coupled to the processor 52 and a bus 66 coupled to the control logic 60. The processor 5 2, the comparator 58, and the control logic 60 simultaneously form a reading circuit for reading an actual threshold voltage range of the memory unit; and an identification circuit for identifying any of the planned levels at least one For a memory cell of a predefined range, the actual threshold voltage offset of each memory cell exceeds a predetermined marginal level in the range that is different from the range boundary level. In addition, the configuration includes several comparators that compare the signal of a memory cell with different test voltages in parallel to identify any memory cell whose actual threshold voltage offset exceeds one of its predetermined margins. Here, several comparators compare the signals of several memory cells in parallel with each test voltage according to the width of the bus 62. An advantageous application of two different test voltages VM1, VM2 different from a discrimination voltage Vb of a normal read operation will now be explained. The invention allows to assess the reliability of the memory. Assuming that V Μ 1 is greater than V Μ 2 ′ hereinafter, referring to FIG. 2, when the threshold voltage Vt shifts along curve 26, it reaches the V M i margin before reaching the VM 2 margin. Then, the recognition circuit is adjusted to define a recognition event of a recognition memory unit. The time between reaching the marginal event of VM i and reaching the marginal event of VM2 can be measured, and thus an indication of the reliability of the memory can be obtained. This is important because NVM cells can only be re-programmed or erased a limited number of times. If a defective cell is re-programmed each time an error is detected or predicted, the limited number will be reached very quickly. Measuring the time between events reaching two margins allows monitoring of the memory's aging or other characteristics and can decide when to replace the memory chip or the MCU. -14- 200301487 (π) Description of the title page There may be several implementations of the controller 60 and the comparator 58. In one implementation, the controller 60 receives the comparison result in the form of digital data on the bus 66 from the comparator 58. The controller 60 checks the difference between the data read of the VM1 margin and the VM2 margin, and transmits an appropriate signal to the processor 52. In another implementation, the bus 66 is ignored, and the processor 58 receives the comparison result in the form of continuous digital data on the bus 64 from the comparator 58. The processor 52 then checks the difference between the data reads of the VM1 margin and the VM2 margin and takes appropriate action. The description of an alternative embodiment of the present invention is also referred to FIG. 4, which is modified as the controller 60 controls the comparator 58 to perform a read operation on a memory unit, and the test read access time is longer than normal The read duration is short. Its advantage is that it controls the integration time in the comparison process. The effect of changing the read access time is similar to the effect of changing the read potential of the bit line of NV, as explained in conjunction with FIG. FIG. 5 shows another specific embodiment of the memory according to the present invention, which is in the form of an MCU 70 including a processing unit processor 72 and an embedded NVM 74. The NVM 74 further includes an array 75 of a memory unit 76, a comparator 78, and an ADC (analog-to-digital converter) 80. The memory cells of the array 75 may individually have a threshold voltage that is programmable or erasable to reach a planned level within a range between the range boundary levels. Comparator 7 8 receives the analog signal on line 8 2 (preferably performed in parallel on several units), compares each signal with an internal voltage, and outputs a digital signal to a bus coupled to processor 7 2 8 4. According to the width of line 82, 200301487 (12) Invention of continuation :, > — 余 办 吻-. &Quot; V, .. Wv.D-. V:-.:? 〆 · 泛, .. '· The processor 72 controls the ADC 80 to measure an actual threshold voltage of several memory cells. The processor 72 compares the output of A DC with a value representative of the test voltage. In another embodiment, a multiplexer (not shown) can multiplex the actual threshold voltage of several memory cells to a single AD C. All the examples illustrated in Figures 1, 3, 4 and 5 allow the implementation of additional advantageous features. Regardless of the number of test voltages, the configuration includes patching components to patch the identification memory cells. In other words, a mechanism known in the art is used to detect and correct a logical data error. It is best to patch only memory arrays that were previously checked with a cyclic redundancy check (CRC). The non-volatile memory may further include a memory component for memorizing an address of an identification memory unit. This facilitates patching and provides patching that does not require the retention of a portion of memory for error correction of redundant data. The non-volatile memory may further include a counter for counting events of the same memory unit. This provides an assessment of the end of the memory usage period. The identification of the unit can be advantageously performed at the full external time of memory data access, and can be used as part of the non-volatile memory startup mode or power-down mode. In the case where the memory is integrated in MCU, unit identification can be advantageously performed during the processor's idle period and the time slot during normal operation of the non-volatile memory.

The threshold voltage of the identification memory cell can be written to a planning level by using a writing means to favorably correct a detection error. This is best in CRC 200301487

(13) Executed after verification. It is advantageous to perform a write operation of the unit after an event or a defined number of events have occurred. It is also advantageous that when an event or a defined number of events occur, the write protection of the memory can be selectively disabled to repair the identification unit. FIG. 6 is a flowchart schematically illustrating a method of operating a non-volatile memory according to the present invention with reference to the above-mentioned memory and FIGS. 1 to 5. The method starts from step 92, reading an actual threshold voltage range of the memory cell. The method proceeds to step 94, identifying any memory cell with a planned level in at least a predefined range, and the actual threshold voltage offset of each memory cell exceeds a range within the range that is different from the range boundary level. Predetermined marginal levels. The results of steps 92 and 94 can then be compared to check the difference. If differences are detected, appropriate measures can be taken, such as using CRC verification or parity checks or repairs. Those skilled in the art will understand that the steps of the method can be performed in any order. Different specific embodiments of the memory have been used herein and Figures 1 to 5 have been used to illustrate advantageous specific embodiments. Explanation of Symbols of the Drawings 10 Non-volatile memory 1 2, 3 5, 5 5, 7 5 Individual memory cell array 1 4, 3 6, 5 6, 76 Memory unit 16 Read circuit 18 Identification circuit 20 Schematic diagram 22 , 24 range -17- 200301487

26 curve 30, 50, 70 microcontroller 32, 52, 72 processing unit processor 34, 54, 74 input NVM 3 8, 58, 78 comparator 40, 60 control logic 42, 62, 82 line 44 , 64, 66, 84 Bus 6 1 Control line 80 Analog to digital converter 90 Flow chart

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Claims (1)

200301487 Patent application scope 1. A non-volatile memory, comprising: a memory cell array, the memory cells of the array can have a programmable or erasable to achieve a range of one The planned critical voltage, the range is between the range boundary levels; a reading circuit for reading an actual voltage range of the memory cells; and an identification circuit for identifying a planned level at For any memory cell within at least one predefined range, the actual critical pressure offset of each memory cell exceeds a predetermined inter-level within the range that is different from the range boundary level. 2. The non-volatile memory of item 1 of the patent application scope, further comprising a means for applying an adjustable test read potential to at least one bit line of the memory cell during a read operation. 3. If the non-volatile memory of item 1 of the patent application scope is adjusted to perform a test read operation under test read conditions different from normal read conditions. 4. The non-volatile memory according to item 1 of the scope of patent application, further comprising a comparison component for comparing the actual threshold voltage of the memory cell with a test voltage having a different discrimination voltage during normal reading operation. 5. The non-volatile memory of item 4 of the patent application, wherein the comparison device includes a comparator that is fed with an analog test voltage. 6. If the non-volatile memory of item 4 of the patent application scope, further includes a comparator, which compares the signal of a memory unit with different measurement positions in parallel. Voltage to identify any memory cell where the actual critical voltage offset exceeds one of several predetermined margins of its planned level. 7. The non-volatile memory of item 4 of the patent application, further comprising a plurality of comparators, which compare the signals of several memory cells in parallel with the test voltage. 8. The non-volatile memory as claimed in claim 4, wherein the comparison device includes an ADC (analog-to-digital converter) for measuring an actual threshold voltage of a memory cell. 9. The non-volatile memory according to item 8 of the patent application, wherein the output of the ADC is compared by the processing unit with a value representing a test voltage. 10. The non-volatile memory according to item 8 of the patent application scope, further comprising a multiplexer for multiplexing the actual threshold voltage of several memory cells. 1 1. The non-volatile memory of item 1 of the patent application scope is adjusted to check a number of memory cells in parallel. 12. The non-volatile memory as claimed in item 1 of the patent application scope, further comprising a method for performing a read operation in a memory unit using a test read access time shorter than a normal read duration. Timing widget. 13. The non-volatile memory according to item 1 of the patent application scope, wherein the identification is part of an activation mode of the non-volatile memory. 14. The non-volatile memory according to item 1 of the patent application scope, wherein the identification is part of a power-down mode of the non-volatile memory. 15. The non-volatile memory according to item 1 of the patent application scope, wherein the identification is added to the time slot of the normal operation process of the non-volatile memory. 16. If the non-volatile memory of item 1 of the scope of patent application, further including the use of 200301487 A writing means for writing the threshold voltage of the identification memory cell as a planned level. 17. The non-volatile memory according to item 1 of the scope of patent application, further comprising a repair member for repairing the identification memory unit. 18. The non-volatile memory according to item 1 of the patent application scope, further comprising a memory component for memorizing an address of an identification memory unit. 19. The non-volatile memory according to item 1 of the patent application scope, wherein the identification circuit is adjusted to define an identification event of an identification memory cell. 2 0. The non-volatile memory of item 19 of the scope of patent application, further comprising a time measuring means for measuring the time between two events of the same memory unit. 2 1. The non-volatile memory according to item 19 of the patent application scope, further comprising a counter for calculating events of the same memory unit. 22 · An MCU (microcontroller unit) with an embedded NVM (non-volatile memory), comprising: a processing unit; a memory cell array, the memory cell systems of the array may each have a A program or a threshold voltage that can be erased to reach a planned level in a range between the range boundary levels; a read circuit for reading an actual threshold voltage range of a memory cell; and An identification circuit for identifying any memory cell with a planned level in at least a predefined range, and the actual threshold voltage offset of each memory cell exceeds a predetermined margin in the range that is different from the range boundary level 200301487 Shen Yi Jerwei continued the page level. 2 3. A method for operating a non-volatile memory, wherein the non-volatile memory includes a memory cell array, and the memory cells of the array can each have a programmable or erasable to reach a range A critical voltage at a planned level, the range being between range boundary levels; a reading circuit for reading a range of actual critical voltages of the memory cell; and an identification circuit; the method includes the following steps: Read an actual threshold voltage range of the memory cells; and identify any memory cell with a planned level in at least a predefined range, and the actual threshold voltage offset of each memory cell exceeds the sum of the range A predetermined marginal level with different boundary levels. 24. The method of claim 23, wherein the identifying step includes the following sub-steps: applying an adjustable read potential to at least one bit line of the array memory cell during a read operation . 25. The method according to item 23 of the scope of patent application, wherein the identifying step further includes the following sub-steps: performing a test read operation under a test read condition different from the normal read condition. 26. The method according to item 23 of the scope of patent application, wherein performing the test read operation includes: comparing an actual threshold voltage of a memory cell with a test voltage different from a discrimination voltage during normal read operation. 27. The method according to item 26 of the patent application scope, wherein the analog signal is compared. 200301487 28. The method according to item 26 of the patent application scope, further comprising the steps of: comparing a signal of a memory cell with different test voltages in parallel to identify several predetermined margins where the actual threshold voltage offset exceeds its planned level Any memory unit. 29. The method according to item 26 of the scope of patent application, wherein the test read operation of a plurality of memory cells is performed in parallel. 30. The method of claim 26, wherein performing the test read operation includes: measuring an actual threshold voltage of the memory cell. 31. The method of claim 30, wherein performing the test read operation comprises: comparing a measured value with a stored value, the stored value representing a test that differs from a discriminating voltage during normal read operation Voltage. 32. The method of claim 30, wherein performing the test read operation comprises: multiplexing the actual threshold voltages of several memory cells. 3 3. The method according to item 23 of the scope of patent application, wherein the inspection of a plurality of memory units is performed in parallel. 34. The method of claim 23, wherein performing the test read operation includes: using a test read access time shorter than a normal read duration to perform a read on a memory unit operating. 35. The method of claim 23, wherein the memory check mode is part of a startup mode of the non-volatile memory. 200301487 36. The method of claim 23, wherein the memory check mode is part of a power-off mode of the non-volatile memory. 37. The method according to item 23 of the scope of patent application, wherein the memory inspection mode is added to the time slot of the normal operation process of the non-volatile memory. 0 38. The method according to item 23 of the scope of patent application The non-volatile memory has a writing component that writes the threshold voltage as the planning level, and further includes a step of rewriting the threshold voltage as a planning level within the range. 39. The method according to item 23 of the patent application scope, wherein the non-volatile memory has a repair member for repairing the identification unit. 40. The method according to item 23 of the patent application scope includes the following additional steps: memorizing an address of an identification memory unit. 4 1. The method according to item 23 of the patent application scope, including the following additional steps: Defining an identification event for identifying a memory unit. 4 2. The method according to item 23 of the patent application scope, including the following additional steps: measuring the time between two events of the same memory unit. 43. The method according to item 23 of the patent application scope, including the following additional steps: Calculate events for the same memory unit. 44. The method according to item 23 of the patent application scope, including the following additional steps: a memory check mode of adding the non-volatile memory. 45. A method of operating an MCU with an embedded NVM, the embedded NVM includes a processing unit; a memory cell array, and the memory cells of the array can each have a programmable or erasable to achieve a Fan 200301487 A critical voltage within a planned level within the range, the range is between the range boundary levels; a reading circuit for reading a practical critical voltage range of the memory cell; and a recognition circuit; the method includes the following steps : Reading an actual critical voltage range of the memory cells; and identifying any memory cell with a planned level in at least a predefined range, the actual critical voltage offset of each memory cell exceeding the range A predetermined marginal level different from the range boundary level. 46. The method according to item 45 of the patent application scope, further comprising the following steps: the processing unit controls the identification circuit.