TWI892071B - Control circuit and semiconductor memory device - Google Patents

Abstract

Provided is a control circuit, which can suppress the prolongation of the delay operation, so that the sequence using the DLL circuit to adjust the delay of the internal clock signal can be finished within a predetermined execution period. A control circuit has: a delay control unit, delaying an input clock signal based on a phase difference between the input clock signal and an output clock signal, and generating the output clock signal; wherein the control circuit further has a clock control unit; wherein when the phase difference is greater than or equal to a first predetermined amount, the clock control unit inputs a clock signal delayed from the input clock signal by a second predetermined amount to the delay control unit as the input clock signal.

Description

Control circuit and semiconductor memory device

The present invention relates to a control circuit and a semiconductor memory device.

Dynamic random access memory (DRAM) features a delay-locked loop (DLL) circuit as a phase synchronization circuit. DRAM uses the DLL circuit to generate an internal clock signal for outputting data signals, which is synchronized with an external input clock signal. For example, see patent document US 20120194241 A1.

When using a DLL circuit to adjust the internal clock signal delay, a detection process involving the N value is performed. The N value represents the DLL circuit's reset operation, the DLL circuit's delay operation (activating each delay line and synchronizing the external clock with the internal clock), and the number of clock cycles of delay between the input clock signal and the internal clock signal. The lockup time Tdll caused by the DLL circuit's delay operation can be expressed using the following formula.

Tint+Tdll=N×tCK

In the above formula, Tint represents the inherent delay time within the DLL circuit, and tCK represents the clock cycle. For example, if the clock cycle (tCK) exceeds the inherent delay time (Tint) due to factors such as the temperature within the semiconductor memory device, the lockup time (Tdll) caused by the DLL circuit's delay will also increase, as shown in the above formula. If the lockup time increases, the overall execution time of the aforementioned program will increase, potentially delaying the execution of the next program. In particular, if the delay is extended, it may exceed the pre-set program execution period (tDLLK). Furthermore, to accommodate the increasing speed of semiconductor integrated circuits, it is desirable to make the delay operations in the program as fast as possible. However, this is quite complex, so a simpler structure is desirable.

The control circuit of the present invention includes a delay control unit that delays the input clock signal based on the phase difference between the input clock signal and the output clock signal to generate the output clock signal. The control circuit further includes a clock control unit. When the phase difference exceeds a first predetermined value, the clock control unit delays the phase of the input clock signal by a second predetermined value and inputs the clock signal to the delay circuit as the input clock signal.

The control circuit, semiconductor memory device, and semiconductor memory device control method of the present invention can have a simple structure and can suppress the extension of delayed operation.

1,1A: DLL circuit

10,10A: Delay control unit

11,11A: Input buffer

12,12A: Phase detection unit

13,13A:DLL control unit

14,14A: Delay circuit

15,15A: Copy Unit

16,16A: Output buffer

17: Clock control unit

71~74: Flip-flop circuit

75: AND circuit

76: Flip-flop circuit

77: Multiplexer

111: Amplifier

112: Amplifier

113: Inverter

121:D Flip-flop Circuit

171: Timing signal generation unit

172: Select the signal generating unit

173: Internal clock selection unit

CK, CLKC, CLKT: Clock signals

clk000: 1st clock signal

clk180: Second clock signal

DQS: output signal

dll_clk: Delay signal (output clock signal)

dll_code: Control signal

dll_reset_n: Reset signal

fb_clk: feedback signal

in_clk: input clock signal

ref_clk: reference clock signal

sel_clk: timing signal

sel180: Select signal

t1~t5,t11~t15,t21~t23,t31~t36,t41~t44: Time

tCK: clock cycle

tDLLK: During execution

Tdll: lock time

Tint: Both delay time

up/down: phase signal

Figure 1 is a block diagram of the control circuit of an embodiment of the present invention.

Figure 2 (1) is a schematic diagram of the input buffer structure; Figure 2 (2) is a schematic diagram of the phase detection unit structure.

Figure 3 is a schematic diagram of the clock control unit.

Figure 4 (1) is a schematic diagram of a control circuit configuration example of a known example; Figure 4 (2) is a timing diagram of the relationship between the input clock signal and the delay time in the control circuit of the known example.

Figure 5 (1) is a timing diagram showing the relationship between the input clock signal and the delay time when the phase difference is greater than 180 degrees; Figure 5 (2) is a timing diagram showing the relationship between the input clock signal and the delay time when the phase difference is less than 180 degrees.

Figure 6 (1) and (2) are schematic diagrams of the various states of this program and the learning program.

Figure 7 shows the timing diagram of the signal voltage transitions within each unit of the control circuit when the phase difference is greater than 180 degrees.

Figure 8 shows the timing diagram of the signal voltage transitions of each unit in the control circuit when the phase difference is less than 180 degrees.

Figure 9 is a block diagram showing other components of the input buffer.

Figure 1 illustrates a DLL circuit 1 (control circuit) according to an embodiment of the present invention. In this embodiment, the control circuit is provided in a semiconductor memory device such as a DRAM. For simplicity, the components of the DRAM or other semiconductor memory device (e.g., N-value detection unit, latent control unit, instruction decoder, memory cell array, input/output interface unit, etc.) are not shown.

DLL circuit 1 includes an input buffer 11, a phase detection unit 12, a DLL control unit 13, a delay circuit 14, a replica unit 15, an output buffer 16, and a clock control unit 17. The phase detection unit 12, DLL control unit 13, delay circuit 14, and replica unit 15 constitute the delay control unit 10. When the program starts, DLL circuit 1 first performs a reset operation, resetting its delay circuit 14 to its initial state. It then performs a delay operation, delaying the input clock signal and generating the desired output clock signal. In other words, the program control of this embodiment includes the reset and delay operations performed in this order.

The input buffer 11 buffers the clock signal CLKT and the clock signal CLKC input to the input buffer 11, and generates a first clock signal clk000 having the same phase as the clock signal CLKT and a second clock signal clk180 having the same phase as the clock signal CLKC. Specifically, as shown in FIG. 2 (1), the input buffer 11 includes an amplifier 111. The two clock signals CLKT and CLKC, which are complementary to each other and serve as external clock signals, are input to the amplifier 111. The input clock signal CLKT and the clock signal CLKC are amplified by the amplifier 111 to generate the first clock signal clk000 and the second clock signal clk180. The second clock signal, clk180, is generated by inverting the first clock signal, clk000.

Returning to Figure 1, the generated first clock signal clk000 and second clock signal clk180 are input to the clock control unit 17, and the first clock signal clk000 is also input to the phase detection unit 12 as the reference clock signal ref_clk.

The phase signal up/down and reset signal dll_reset_n output from phase detection unit 12 are input to clock control unit 17. When reset signal dll_reset_n is high, it indicates the completion of the reset operation. Based on the phase signal up/down, clock control unit 17 outputs either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk. This input clock signal in_clk is then fed into delay circuit 14.

Delay circuit 14 generates a delayed signal (output clock signal) dll_clk based on the delay amount set by DLL control unit 13 and transmits this signal to output buffer 16 and replica unit 15. This signal is derived by delaying the input clock signal in_clk from clock control unit 17. The delayed signal dll_clk input to output buffer 16 is buffered within output buffer 16 and output as the output signal DQS. Replica unit 15 outputs the delayed signal dll_clk generated by delay circuit 14 as the feedback signal fb_clk. The feedback signal fb_clk is input to the phase detection unit 12.

The reference clock signal ref_clk and the feedback signal fb_clk are input to the phase detection unit 12. The phase detection unit 12 generates a phase signal up/down and inputs it to the DLL control unit 13. The phase signal up/down indicates whether the phase of the feedback signal fb_clk leads (delayed by less than 180 degrees) or lags (delayed by more than 180 degrees) the reference clock signal ref_clk.

Specifically, the phase detection unit 12 is shown in FIG2 (2) and is composed of a D flip-flop circuit 121. The feedback signal fb_clk is input as an input signal to the D flip-flop circuit 121, and the reference clock signal ref_clk is input as a clock signal to the D flip-flop circuit 121. In addition, the D flip-flop circuit 121 outputs a phase signal up/down as an output signal. When the feedback signal fb_clk is delayed by less than 180 degrees relative to the reference clock signal ref_clk, the generated phase signal up/down is high (up); when the feedback signal fb_clk is delayed by more than 180 degrees relative to the reference clock signal ref_clk, the generated phase signal up/down is low (down).

Returning to Figure 1, the DLL control unit 13 determines the delay amount based on the phase difference detected by the phase detection unit 12. Specifically, the DLL control unit 13 generates and outputs a control signal dll_code consisting of multiple bits based on the up/down phase signal from the phase detection unit 12 as the delay amount during the delay operation. This output control signal dll_code is input to the delay circuit 14.

The delay circuit 14 is a variable delay unit that performs a delay operation. Specifically, the delay circuit 14 activates the delay line according to the control signal dll_code, thereby delaying the input signal in_clk and generating the delay signal dll_clk.

In addition, based on the phase signal up/down, the DLL control unit 13 determines that the delay operation has ended when it determines that the input signal in_clk and the feedback signal fb_clk corresponding to the delay signal dll_clk converge to a predetermined range. Thus, the delay operation ends.

In the DLL circuit 1 of this embodiment, the delay control unit 10 generates a delay signal dll_clk that delays the input clock signal in_clk based on the input clock signal in_clk and the feedback signal fb_clk copied from the delay signal dll_clk. The clock control unit 17 is described below. The clock control unit 17 controls the input clock signal in_clk to the delay control unit 10.

The phase signal up/down, reset signal dll_reset_n, first clock signal clk000, and second clock signal clk180 are input to clock control unit 17. Clock control unit 17 selects either first clock signal clk000 or second clock signal clk180 as input clock signal in_clk and inputs this input clock signal in_clk to delay circuit 14. Before the delay operation, clock control unit 17 selects first clock signal clk000 as input clock signal in_clk. After the delay operation begins, the clock control unit 17 selects either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk based on the phase signal up/down.

Figure 3 illustrates the detailed structure of the clock control unit 17. The clock control unit 17 includes a timing signal generating unit 171, a selection signal generating unit 172, and an internal clock selection unit 173.

When a predetermined period of time has passed since the start of the delay operation, the timing signal generation unit 171 generates a timing signal sel_clk indicating that the predetermined period of time has passed, and inputs the signal to the selection signal generation unit 172. This predetermined period of time is used when selecting the clock after the reset operation, and the clock selection is performed after the DLL circuit 1 has stabilized.

When the timing signal sel_clk indicates that the predetermined time has elapsed, the selection signal generation unit 172 determines whether the phase difference between the input clock signal (reference clock signal ref_clk) and the output clock signal (feedback signal fb_clk) of the delay control unit 10 is greater than 180 degrees. The selection signal sel180 indicating the determination result is then input to the internal clock selection unit 173. The phase signal up/down is used to determine whether the phase difference between the input clock signal and the output clock signal of the delay control unit 10 is greater than 180 degrees. As described above, when the delay of the feedback signal fb_clk (in phase with the output clock signal of the delay control unit 10) relative to the reference clock signal ref_clk (in phase with the input clock signal of the delay control unit 10) is less than 180 degrees, the phase signal up/down is high (up). When the delay is greater than 180 degrees, the phase signal up/down is low (down). Therefore, this phase signal up/down can be used to easily make judgments. In other words, when the timing signal sel_clk indicates that a predetermined period of time has elapsed, the selection signal generation unit 172 determines whether the phase signal up/down is greater than 180 degrees and generates a selection signal sel180 indicating the judgment result, which is input to the internal clock selection unit 173. Based on the judgment result indicated by the selection signal sel180, the internal clock selection unit 173 selects either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk, and outputs the input clock signal in_clk.

The clock control unit 17 is further described using Figures 4 to 6.

In the conventional example shown in FIG4 (1), the DLL circuit 1A differs from the present embodiment in that it does not include the clock control unit 17. In the DLL circuit 1A, the clock signal CK output from the input buffer 11A is input to the delay control unit 10A (phase detection unit 12A, DLL control unit 13A, and delay circuit 14A), which outputs the delay signal dll_clk. In the conventional example of such a configuration, as shown in FIG4 (2), the clock signal CK changes from a low level to a high level at time t1; in contrast, the feedback signal fb_clk changes from a low level to a high level at time t2 after the existing delay time Tint. Since the period t1 to t2 is less than half a cycle of the clock signal CK, the feedback signal fb_clk is delayed by more than 180 degrees relative to the cycle of the clock signal CK. Then, after the delay circuit 14A delays the clock signal CK, at time t5, the rising edge of the clock signal CK coincides with the rising edge of the output signal DQS, making the clock signal CK and the feedback signal fb_clk (i.e., the output signal DQS) synchronized. In the example above, if the delay of the feedback signal fb_clk relative to the clock signal CK before the delay operation exceeds half the clock period, meaning the phase difference exceeds 180 degrees, the delay that must be eliminated by the delay operation, namely the lock time Tdll, will become the period t2-t5. Therefore, the delay operation may be extended.

In contrast, the present embodiment includes a clock control unit 17 that, based on the phase signal up/down, inputs either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk to the delay circuit 14 (delay control unit 10), thereby suppressing the extension of the delay operation. First, the input clock signal in_clk input to the delay control unit 10 before the delay operation is the first clock signal clk000, so the input clock signal in_clk is in phase with the first clock signal clk000. When the phase difference between the delayed signal dll_clk output from the delay control unit 10 and the feedback signal fb_clk with the same phase is greater than 180 degrees, the clock control unit 17 uses the second clock signal clk180 as the input clock signal in_clk and outputs it to the delay circuit 14. As a result, the output clock signal from the delay circuit 14 is also delayed by 180 degrees, in phase with the same phase as fb_clk. As a result, the delay control unit 10 performs a delay operation based on the phase difference between the rising edge of the second clock signal clk180 and the rising edge of the feedback signal fb_clk, which is delayed by 180 degrees. This allows synchronization between the input clock signal in_clk and the feedback signal fb_clk to be completed as early as possible, thereby generating the desired output signal DQS.

Specifically, the situation where the phase difference between the feedback signal fb_clk and the input clock signal in_clk after the delay operation is greater than 180 degrees is described. As shown in Figure 5 (1), the input clock signal in_clk and the first clock signal clk000 change from low to high at time t11; in contrast, the feedback signal fb_clk is delayed by the existing delay time Tint and changes from low to high at time t12. Since the period t11 to t12 indicating this phase difference is less than half a cycle of the clock signal CK, the feedback signal fb_clk is delayed by more than 180 degrees relative to the cycle of the input clock signal in_clk. At this point, clock control unit 17 selects second clock signal clk180 as input clock signal in_clk. Delay control unit 10 then delays second clock signal clk180 so that the rising edge of second clock signal clk180 at time t13 coincides with the rising edge of feedback signal fb_clk, which is delayed by 180 degrees at time t14 (second clock signal clk180 and feedback signal fb_clk are synchronized). As a result, the delay required to compensate for the delay, or the lock time Tdll, falls between t14 and t15.

If we summarize it, as shown in Figure 6 (1), in the conventional example, when the phase difference between the input clock signal and the output clock signal in the delay control unit 10 is greater than 180 degrees, the lock time Tdll is prolonged, and thus the overall program time is also prolonged. In contrast, in this embodiment, when the phase difference between the input clock signal and the output clock signal in the delay control unit 10 is greater than 180 degrees, the DLL circuit 1 is formed, and the second input clock signal clk180 can be used as the input clock signal. Therefore, the delay operation can be terminated as early as possible, and the overall program time can be shortened.

In addition, FIG5 (2) shows the case where the phase difference between the feedback signal fb_clk after the delay operation and the input clock signal in_clk is less than 180 degrees. In this case, since the phase difference is small, the first clock signal clk000 is selected. Thus, as in the conventional example, the delay circuit 14 performs a delay operation on clk000 so that the rising edge of the first clock signal clk000 at time t21 coincides with the rising edge of the feedback signal fb_clk at time t22. As a result, the delay time Tint is the period t21 to t22, and the lock time Tdll is the period t22 to t23. When performing a delay operation in this way, as shown in Figure 6 (2), it is also possible to perform the delay operation as early as possible when the delay is less than 180 degrees, as we know, and thus keep the overall sequence time shortened.

Returning to Figure 3, the specific structure of the clock control unit 17 that implements this operation is described. The timing signal generation unit 171 includes a plurality of flip-flop circuits 71-74 and an AND circuit 75. While the figure illustrates four flip-flop circuits 71-74, this number is not limited to this number and can be adjusted appropriately based on the desired time required for circuit stabilization.

A plurality of flip-flop circuits 71-74 are connected in series. The externally input reset signal dll_reset_n is input to the upstream-most flip-flop circuit 71. The output signals of the adjacent upstream flip-flop circuits 71-73 are input to the subsequent flip-flop circuits 72-74. The first clock signal clk000 is inverted and input as a clock signal to each of the flip-flop circuits 71-74. Furthermore, the reset signal dll_reset_n is inverted and input to each of the flip-flop circuits 71-74. The output signal of the downstream-most flip-flop circuit 74 is inverted and input to an AND circuit 75. In addition, the output of flip-flop circuit 73, which is connected upstream of flip-flop circuit 74, is input to AND circuit 75. At the same time, the first clock signal clk000 is also input to AND circuit 75. AND circuit 75 performs an AND operation on these input signals to output the timing signal sel_clk.

The operation of timing signal generation unit 171 is described below. When the input reset signal dll_reset_n changes from a low level to a high level, this change is maintained for a predetermined period through a plurality of flip-flop circuits 71-74 and then input from flip-flop circuit 74 to AND circuit 75. Because AND circuit 75 receives the output signal of flip-flop circuit 73, the output signal of flip-flop circuit 74, and the first clock signal clk000, when the output of flip-flop circuit 74 is high, AND circuit 75 generates and outputs a high-level (assert) timing signal sel_clk. Furthermore, AND circuit 75 generates and outputs a low-level timing signal sel_clk. Therefore, the timing signal sel_clk is high only after the reset operation, from the start of the delay operation until the predetermined timing. In other words, the timing signal sel_clk is generated as a one-shot signal.

The select signal generation unit 172 is comprised of a flip-flop circuit 76. The phase signal up/down is inverted and input to the flip-flop circuit 76 as an input signal, and the timing signal sel_clk is input to the flip-flop circuit 76 as a clock signal. Furthermore, the reset signal dll_reset_n is inverted and input to the flip-flop circuit 76. The flip-flop circuit 76 then outputs the select signal sel180 as an output signal. As described above, the timing signal sel_clk is a single-trigger signal that transitions from a low level to a high level only after a predetermined period of time has elapsed since the start of the delay operation. Therefore, the select signal generation unit 172 can determine whether the delay is greater than 180 degrees only at the predetermined timing after the start of the delay operation.

The operation of the select signal generating unit 172 is described below. In the select signal generating unit 172, when the timing signal sel_clk transitions from a low level to a high level, if the reset signal dll_reset_n is high and the phase signal up/down is high (up), the select signal sel180 remains low. In this case, since the phase difference between the input signals to the delay control unit 10 is less than 180 degrees, the select signal sel180 is output at a low level, indicating that the second clock signal clk180 is not selected. On the other hand, when the timing signal sel_clk changes from a low-level input to a high-level input, if the reset signal dll_reset_n is high and the phase signal up/down is low (down), a high-level selection signal sel180 is output, indicating that the second clock signal clk180 is selected.

Internal clock selection unit 173, comprised of multiplexer 77, selects either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk and outputs it based on select signal sel180. Specifically, when select signal sel180 is high, indicating the second select signal clk180 is selected, multiplexer 77 outputs the second clock signal clk180. Otherwise, multiplexer 77 outputs the first clock signal clk000.

The clock control unit 17 can use a simple structure to set either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk according to the phase signal up/down, and input it to the delay circuit 14. In this way, the DLL circuit 1 of this embodiment can suppress the extension of the delay operation.

Next, the operation of the DLL circuit 1 of this embodiment including the clock control unit 17 will be described using the flowcharts shown in Figures 7 and 8.

Figure 7 illustrates what happens when the phase difference between the feedback signal fb_clk and the input clock signal in_clk exceeds 180 degrees. Initially, the process begins with the DLL reset state. In this state, the input clock signal in_clk is the first clock signal, clk000, and the phase difference between the feedback signal fb_clk and the input clock signal in_clk exceeds 180 degrees. The DLL state then ends at time t31, and the reset signal dll_reset_n transitions from low to high. Regarding the DLL circuit's state, the delay operation begins when the DLL reset state ends at time t31.

Then, at time t32, in timing signal generation unit 171, timing signal sel_clk transitions from low to high after a predetermined period. At this time t32, reset signal dll_reset_n transitions to high, and phase signal up/down transitions to low (down). At the rising edge of timing signal sel_clk, the high reset signal dll_reset_n and the low phase signal up/down are input to select signal generation unit 172, causing select signal sel180 to transition from low to high and be output. As a result, the input clock signal in_clk output from the clock control unit 17 becomes the second clock signal clk180. From time t32 to time t33, the input signal in_clk and the second clock signal clk180 remain at the same low level.

At time t33, the input clock signal in_clk transitions from low to high in response to the rising edge of the second clock signal clk180. Furthermore, by selecting the second clock signal clk180 as the input clock signal in_clk, the feedback signal fb_clk is also delayed by 180 degrees, remaining low from time t32 to time t34, and transitioning from low to high at time t34. As the feedback signal fb_clk transitions from low to high, the phase signal up/down transitions from low to high at time t35. This means that the phase difference between the feedback signal fb_clk and the input signal in_clk decreases (to less than 180 degrees).

Based on the phase signal up/down, the delay circuit 14 delays the input clock signal in_clk, which is the second clock signal clk180. At time t36, it is determined that the phase difference is the desired phase difference, and the delay operation ends.

Next, the flow chart shown in Figure 8 will be used to explain the operation of DLL circuit 1 when the phase difference between the feedback signal fb_clk and the input clock signal in_clk is less than 180 degrees.

When this process begins, DLL circuit 1 is in the DLL reset state. The reset operation then completes at time t41, and the reset signal dll_reset_n transitions from low to high. Simultaneously with the completion of the reset operation at time t41, the delay operation begins in DLL circuit 1.

Then, at time t42, the timing signal sel_clk in timing signal generation unit 171 transitions from a low level to a high level. At this time, the reset signal dll_reset_n is high, and the phase signal up/down is up (high). At the rising edge of timing signal sel_clk, the high reset signal dll_reset_n and the high phase signal up/down are input to selection signal generation unit 172, thereby maintaining the selection signal at a low level. This selects the first clock signal clk000 as the input clock signal in_clk. From time t42 to time t43, input signal in_clk remains high, just like the first clock signal clk000. In addition, since the input signal in_clk is the first clock signal clk000, the feedback signal fb_clk will not be delayed by 180 degrees.

Based on the phase signal up/down, the delay circuit 14 delays the input clock signal in_clk, which is the first clock signal clk000, and determines that the phase difference is the desired at time t44, thus ending the delay operation.

The following describes a variation of the present invention. As shown in FIG. 9 , input buffer 11 is configured and includes amplifier 112 and inverter 113. A clock signal CLKT and a clock signal CLKC, which are complementary to each other, are input to amplifier 112 as external clock signals. Amplifier 112 amplifies the complementary clock signals CLKT and CLKC, which then output only a first clock signal clk000 that is in phase with clock signal CLKT. Furthermore, this first clock signal clk000 is input to inverter 113, which inverts the first clock signal clk000 to generate a second clock signal clk180. In the above embodiment, since both signals are output from amplifier 111, the number of CMOS gate stages between the first clock signal clk000 and the second clock signal clk180 is the same. In contrast, in the embodiment shown in FIG9 , the number of CMOS gate stages between the first clock signal clk000 and the second clock signal clk180 differs by one stage.

The above embodiment controls the phase difference between the input signal in_clk and the delayed signal dll_clk (feedback signal fb_clk) by determining whether the phase difference is greater than 180 degrees. However, this phase difference can also be set to a desired value. Furthermore, although the second clock signal clk180 is a 180-degree delay from the first clock signal clk000, this phase difference can also be set to a desired value. Furthermore, the semiconductor memory device can be a static random access memory (SRAM), flash memory, or other semiconductor memory device.

The above embodiments and variations are described to facilitate understanding of the present invention and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments and variations are intended to include all design modifications or equivalents within the technical field of the present invention.

1: DLL circuit

10: Delay control unit

11: Input buffer

12: Phase detection unit

13:DLL control unit

14: Delay circuit

15: Copy Unit

16: Output buffer

17: Clock control unit

CLKC, CLKT: Clock signal

clk000: 1st clock signal

clk180: Second clock signal

DQS: output signal

dll_clk: Delay signal

dll_code: Control signal

fb_clk: feedback signal

in_clk: input clock signal

ref_clk: reference clock signal

up/down: phase signal

dll_reset_n: Reset signal

Claims (17)

A control circuit comprises: A delay control unit, which delays an input clock signal based on a phase difference between the input clock signal and an output clock signal, and generates the output clock signal; The control circuit further comprises a pulse control unit; When the phase difference is greater than a first predetermined amount, the pulse control unit delays the phase of the input clock signal by a second predetermined amount and inputs the clock signal to the delay control unit as the input clock signal; A first input clock signal and a second input clock signal whose phase is delayed by the second predetermined amount are input to the pulse control unit; The delay operation is performed based on a phase difference between a rising edge of the second input clock signal and a rising edge of the output clock signal. The clock control unit includes a timing signal generation unit, a selection signal generation unit, and an internal clock selection unit; the internal clock selection unit couples the first input clock signal and the second input clock signal. The clock control unit receives a reset signal and initiates the delay operation when the reset signal changes from a first level to a second level. When a predetermined period of time has elapsed since the start of the delay operation, the timing signal generation unit generates a timing signal indicating the elapse of the predetermined period of time based on the reset signal and the first input clock signal. The selection signal generating unit receives a phase signal representing the phase difference, the reset signal, and the timing signal to generate a selection signal. The internal clock selection unit selects either the first input clock signal or the second input clock signal based on the selection signal. The control circuit of claim 1, wherein when the phase difference is greater than a first predetermined value, the clock control unit selects the second input clock signal as the input clock signal. The control circuit of claim 1, wherein the clock control unit determines whether the phase difference is greater than the first predetermined amount at a predetermined time point after the delay operation begins. The control circuit of claim 1, wherein the delay control unit includes a phase detection unit that detects a phase difference between the input clock signal and the output clock signal; and wherein the phase difference detected by the phase detection unit is input to the clock control unit. The control circuit of claim 2, wherein the selection signal generating unit generates the selection signal, the selection signal indicating whether the phase difference is greater than a predetermined value; when the phase signal is at a first level, it indicates that the phase difference between the first input clock signal and the output clock signal is greater than the predetermined value; when the selection signal generating unit receives the timing signal and the phase signal at the first level, the selection signal changes from the first level to a second level and is output, causing the internal clock selection unit to select and output the second input clock signal as the input clock signal. The control circuit of claim 1, wherein: the delay control unit includes a delay circuit and a DLL control unit; the delay circuit generates the output clock signal based on a delay amount set by the DLL control unit. The control circuit of claim 6, wherein the delay control unit includes a phase detection unit coupled to the DLL control unit; the phase detection unit receives a feedback signal and a reference clock signal to generate a phase signal, wherein the phase signal indicates whether the phase of the feedback signal leads or lags behind the reference clock signal. The control circuit of claim 7, wherein the delay control unit includes a replica unit coupled to the delay circuit and the phase detection unit; the replica unit receives the output clock signal generated by the delay circuit and outputs it as the feedback signal. The control circuit of claim 1, wherein the first predetermined value is 180 degrees and the second predetermined value is 180 degrees. The control circuit of claim 2 further comprises: an input buffer to which an external clock signal is input; wherein, in the input buffer, the first input clock signal is generated from the external clock signal, and the second input clock signal is generated by inverting the external clock signal. The control circuit of claim 2 further comprises: an input buffer to which an external clock signal is input; wherein, in the input buffer, the first input clock signal is generated from the external clock signal, and the second input clock signal is generated from a compensation clock signal of the external clock signal. The control circuit of claim 1, wherein the timing signal generating unit comprises a plurality of flip-flop circuits and an AND circuit; wherein the plurality of flip-flop circuits are connected in series; wherein the reset signal is input to the flip-flop circuit most upstream of the plurality of flip-flop circuits; and wherein the output signal of one of any two adjacent flip-flop circuits serves as the input signal of the other flip-flop circuit. The control circuit of claim 12, wherein the first input clock signal is inverted and input as the clock signal to the multiple flip-flop circuits; the reset signal is inverted and input to the multiple flip-flop circuits; the output signal of the most downstream flip-flop circuit among the multiple flip-flop circuits is inverted and input to the AND circuit, the output signal of the flip-flop circuit adjacent to the most downstream flip-flop circuit is input to the AND circuit, and the first input clock signal is input to the AND circuit. The control circuit of claim 12, wherein when the reset signal changes from the first level to the second level, the change is maintained for a predetermined time through the plurality of flip-flop circuits and then input to the AND circuit from the most downstream flip-flop circuit. The control circuit of claim 14, wherein the AND circuit receives an output signal of a flip-flop circuit adjacent to the most downstream flip-flop circuit, an output signal of the most downstream flip-flop circuit, and the first input clock signal; and when the output signal of the most downstream flip-flop circuit is high, the AND circuit generates and outputs the timing signal at a high level, such that the timing signal remains high from the start of the delay operation until a predetermined time after the reset operation. A semiconductor memory device includes a control circuit: the control circuit includes: a delay control unit that delays an input clock signal based on a phase difference between the input clock signal and an output clock signal to generate the output clock signal; the control circuit further includes a clock control unit; when the phase difference is greater than a first predetermined amount, the clock control unit delays the phase of the input clock signal by a second predetermined amount and inputs the clock signal to the delay control unit as the input clock signal; a first input clock signal and a second input clock signal whose phase is delayed by the second predetermined amount are input to the clock control unit; The delay operation is performed based on a phase difference between a rising edge of the second input clock signal and a rising edge of the output clock signal. The clock control unit includes a timing signal generation unit, a selection signal generation unit, and an internal clock selection unit; the internal clock selection unit is coupled to the first input clock signal and the second input clock signal. The clock control unit receives a reset signal and initiates the delay operation when the reset signal changes from a first level to a second level. When a predetermined period of time has elapsed since the start of the delay operation, the timing signal generation unit generates a timing signal indicating the timing of the predetermined period of time based on the reset signal and the first input clock signal. The selection signal generating unit receives the phase signal representing the phase difference, the reset signal, and the timing signal to generate a selection signal. The semiconductor memory device of claim 16, wherein the semiconductor memory device is a dynamic random access memory (DRAM).