TWI303441B - Output controller with test unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor memory device; and more particularly, to an output controller having a test unit for controlling a semiconductor memory device. Data output timing. [Prior Art] Since the semiconductor memory device is highly integrated, many have been carried out - the type 5 is used to increase the operation speed. To achieve this, a synchronous memory device that operates synchronously with an external clock has been introduced. During a clock cycle, a single data rate (SDR) sync memory device inputs and outputs a data via a data plug synchronized with one of the rising edges of the external clock. However, the SDR sync memory device is insufficient to meet the speed requirements of a high speed system. Therefore, it has been proposed to process two data double data rate (DDR) sync memory devices during one clock cycle. In the DDR synchronous memory device, two feed materials are continuously input and output in synchronization with the rising and falling edges of the 邛呤 pulse via the data input/output plug. The DDR sync memory device can construct at least twice the bandwidth of the SDR sync memory device without increasing the frequency of the clock, thereby achieving high speed operation. Since the DDR memory device is required to receive or output two bedding during one clock cycle, the data access method used in conventional synchronous memory devices can no longer be used. * / The cycle of the pulse is about 10 ns, and the two consecutive data must be processed substantially in ό nsec or less 112655.doc 1303441, except for the rise time and fall time (about 0·5χ4=2 ns) and other The time required for the specification is outside. However, it is difficult to perform this process within the memory device. Therefore, only when the winter circuit (W) and the external circuit input data or output data to it, the memory device operates in synchronization with the rising and falling edges of the talk clock. In general, the two data are processed in synchronization with one edge of the clock within the memory device. In order to transfer > from a memory device to an internal core region or

The transfer of the transferred data to an external circuit requires a new method of data access. The synchronous memory device uses a number of different concepts than their non-synchronous memory placement. One of them is CAS Latent Time (CL). The CAS latency is the number of clocks from the first read fetch to the data output. If CL = 3, it means that the data is output to an external circuit after three clock cycles input from one of the read commands. The CAS latency determines the data output timing. In one of the initial operations of the semiconductor memory device, a set of detected CL values are used to access and output the data. Thus, a data output enable signal is generated after an operational clock cycle is delayed as long as the set of CAS latency. When the data output enable signal is enabled, the accessed data is output in response to the read command. The operational clock used is a delay locked loop (DLL) clock that is obtained by locking an external clock delay for a predetermined time. This DLL clock is generated from a delay locked loop (DLL) circuit. In synchronous semiconductor memory devices, the data wheel must be accurately synchronized with the rising and falling edges of the external clock. However, due to the delay time of the clock signal (which inevitably occurs during the internal period), the data output cannot be accurately synchronized with the rising and falling edges of the external clock. Figure 1 is a block diagram of a conventional output controller.

Referring to Fig. 1, the output controller includes a clock delay unit 10, a selection unit 20, an initial synchronization unit 30, and a synchronization unit 40. The clock delay unit 10 delays a rising DLL clock RCLK_DLL and a falling DLL clock FCLK_DLL by a predetermined time in response to the CAS latent information signals CL3 to CL5. The selecting unit 20 selects signals corresponding to the CAS latent information signals CL3 to CL5 in the output signals of the clock delay unit 10 and outputs the selected signals as a plurality of driving clocks RCLK_OE10 to RCLK_OE35. When a read CAS signal CASP6-RD is enabled, the initial synchronization unit 30 outputs an output enable signal OEOO. The synchronizing unit 40 synchronizes the output signal of the selecting unit 20 with the corresponding driving clock and the DLL clock, and generates output enable signals OE10 to OE45. For reference, the read CAS signal CASP6_RD is caused by a read operation in a semiconductor memory device, and only the C AS latency information signals CL3 to CL5 corresponding to the set of CLs are enabled. Although not shown in Fig. 1, the output enable signals OEOO to OE45 contain information on the delay time of the elapse of the self-reading CAS signal CASP6_RD, and provide CL information. In other words, when the wheel-out drive signals ROUTEN and FOUTEN for controlling the data output are generated, the output enable signals OEOO are used when outputting data from a memory core block in response to the read command via a data pad output. To OE45 to meet the group's CAS latency. / if*": V ' 112655.doc 1303441 The operation of the output controller without the clock delay unit 10 and the selection unit 20 will be described below. Figure 2A is a waveform diagram of a conventional output controller operating at a low frequency. Referring to FIG. 2A, when a read command RD is applied in synchronization with the external clock CLK, a corresponding read CAS signal CASP6_RD is enabled.

Subsequently, the initial synchronization unit 30 enables the output enable signal OEOO in response to the read CAS signal CASP6_RD. The first synchronization unit outputs an output enable signal OE10 synchronized with the rising edge of the first rising DLL clock RCLK_DLL from the enable output of the output enable signal OEOO. Although not shown, the second synchronization unit enables the output enable signal OE15 by synchronizing the output enable signal OE10 of the first synchronization unit with the falling DLL clock FCLK_DLL, and by outputting the second synchronization unit The signal OE15 is synchronized with the rising DLL clock RCLK_DLL, and the third synchronizing unit enables the output enable signal OE20. Through such a procedure, a plurality of output enable signals OEOO to OE45 are enabled by the self-reading CAS signal CASP6_RD and synchronized with the rising DLL clock RCLK_DLL and the falling DLL clock FCLK_DLL. However, as illustrated in Figure 2B, if the output controller is operated at a high frequency, the enable enable signal OE10 synchronized with the first rising DLL clock RCLK_DLL cannot be enabled from the enable of the read CAS signal CASP6_RD. Since the output controller is operated at a high frequency, the edge of the first rising DLL clock RCLK_DLL causes the enable time of the output enable signal OEOO to be enabled by the initial synchronization unit 30. Therefore, the first synchronization unit outputs an output enable signal 〇E1 同步 synchronized with the 112655.doc 1303441 second rising DLL clock. That is, since the activation time of the output enable signal generated from the output controller is delayed by one clock, the data outputted in synchronization with the generated output drive signal to output the enable signal cannot satisfy the group of CAS dive. At the time, the data is invalidated. To solve such problems, the conventional output controller further includes a clock delay unit for delaying the rising DLL clock and the falling dll clock according to the CAS latency and selecting a unit for outputting according to the CAS latency output. The clock acts as the driving clock. In order to prevent data failure from occurring when the first rising DLL clock is enabled earlier than reading the CAS signal, the conventional output controller adjusts the rising time point of the DLL clock according to the frequency. However, due to the fixed delay amount, it is difficult to control the actual wafer system according to the change in ρντ. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an output controller having a test unit that is capable of testing an appropriate amount of delay based on an operating frequency of a real situation. According to an aspect of the present invention, an output controller is provided, comprising: an initial synchronization unit for outputting an output enable command number when a read CAS signal is enabled, and synchronizing a plurality of serial connections The unit, for outputting the output tfL number of the previous stage as an output enable signal synchronized with the corresponding driving time, the first stage of the synchronous units receiving the first wheel. The enable signal ·, and - test unit is configured to clock the delay amount of the clock according to the plurality of test signals and output the drive clock. According to another aspect of the present invention, a semiconductor device for controlling data output timing is provided, comprising: an initial synchronization unit for outputting a first read CAS signal when enabled An output enable signal; a plurality of serially connected synchronization units, each of which is configured to output the output signal of the previous stage as an output enable signal synchronized with the corresponding drive clock, the first synchronization unit of the plurality of synchronization units Receiving a first output enable signal; and a test unit for adjusting a delay amount of the input clock based on the plurality of test-delay adjustment signals and outputting a plurality of drive clocks to respond to the plurality of test completion signals. [Embodiment] An output controller according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings. Figure 3 is a block diagram of an output controller having a test unit in accordance with the present invention. Referring to FIG. 3, an output controller according to an embodiment of the present invention includes a clock delay unit 100, a selection unit 200, an initial synchronization unit 00, a plurality of serially connected synchronization units 400, and a test unit 500. The initial synchronization unit 300 outputs an output enable signal OE00 when a read CAS signal CASP6JRD is enabled. The synchronizing unit 400 generates output enable signals OE10 to OE45 by synchronizing the output signals of the individual preceding stages with the corresponding driving clocks RCLK_OE10 to FCLK_OE35 and the rising and falling DLL clocks RCLK_DLL and FCLK_J)LL. The test unit 500 controls each delay amount of the input clock RDLL_OE10CL to FDLL^_OE3 5CL applied according to a test signal TM and outputs a drive clock RCLK_OE10 112655.doc -10- 1303441 to FCLK_OE35. The clock delay unit 100 delays the rising and falling DLL clocks RCLK^DLL and FCLK_DLL by a predetermined time in response to the CAS latent information signals CL3 to CL5. The selection unit 200 selects signals corresponding to the CAS latent information signals CL3 to CL5 among the output signals of the clock delay unit 100. Since the output controller further includes a test unit 500 that can add a delay to the driving clocks RCLK_OE10 to FCLK_OE35 input to the synchronization unit 400 for generating the output enable signals OE00 to OE45, in the case of a real wafer Test the amount of delay required based on frequency. The individual units of the output controller will be described in detail below with reference to the accompanying drawings. 4 is a circuit diagram of the test unit 500 of FIG. 3 in accordance with a first embodiment of the present invention. Referring to FIG. 4, the test unit 500 includes first to sixth delay adjustment units 510, 520, 53 0, 540, 550, and 560 for use by a test-delay increment signal TM_INC, a test-delay decrement signal. TM_DEC and a test-delay normal signal NO_TM adjust the delay amount of the input signal to output the driving clocks RCLK_OE10 to FCLK_OE3 5. FIG. 5 is a circuit diagram of the first delay adjustment unit 510 of FIG. 4. The second to sixth delay adjusting units 520 to 560 have the same circuit configuration as that of the first delay adjusting unit 510. The first delay adjustment unit 5 10 will be described as an exemplary structure. Referring to FIG. 5, the first delay adjustment unit 510 includes a first delay unit 512, a second delay unit 514, a first transfer gate TG1, a second transfer gate TG2, and a third transfer gate TG3. The first and second delay units 512 and 112655.doc -11- 1303441 5 14 are connected in series for delaying the input signal. The first transfer gate TGI transfers the input clock RDLL_OE10CL as the drive clock RCLK_OE10 in response to the test-delay down signal TM__DEC. The second transfer gate TG2 transfers the output signal of one of the first delay units 512 as the driving clock RCLK_OE10 in response to the test-delay normal signal NO_TM. The third transfer gate TG3 transfers the output signal of one of the second delay units 514 as the drive clock RCLK_OE10 in response to the test-delay increment signal TM_INC.

In the delay adjustment unit 510, when the test-delay normal signal NO_TM is enabled, the signal delayed by the first delay unit 512 is output as the drive clock RCLK_OE10, and when the test-delay increment signal TM-INC is enabled. The signals delayed by the first and second delay units 5 12 and 514 are output as the driving clocks RCLK_OE10. When the test-delay down signal TM-DEC is enabled, the input clock RDLL_OE10CL is immediately output as the drive clock RCLK_OE10. FIG. 6 is a circuit diagram of the selection unit 200 of FIG. Referring to FIG. 6, the selection unit 200 includes first to sixth selectors 210, 220, 23 0, 240, 250, and 260 for selecting output clocks of the first to third clock delay units 120, 140, and 160. One of them responds to the CAS latent information signals CL3 to CL5. The first to sixth selectors 210 to 260 have the same circuit configuration. Therefore, the first selector 210 will be selected as an example. The first selector 210 includes a first transfer gate TG4, a second transfer gate TG5, a third transfer gate TG6, and an inverter II. When the CAS latency information signal CL3 is enabled, the first transfer gate TG4 shifts the first clock RDLL_OE10DL3 among the output clocks of the first clock delay 112655.doc -12- 1303441 unit 120. When the CAS latent information signal CL4 is enabled, the second transfer gate TG5 transfers the first clock RDLL_OE10DL4 among the output clocks of the second clock delay unit 140. When the CAS latency information signal CL5 is enabled, the third transfer gate TG6 transfers the first clock RDLL_OE10DL5 of the output clock of the third clock delay unit 160. The inverter II inverts the voltages of the common output nodes of the first to third transfer gates TG4 to TG6 to output the first CAS delay clock RDLL_OE10CL.

That is, when the CAS latency information signal CL3 is enabled, the selection unit 200 transfers the plurality of delay clocks RDLL_OE10DL3 and FDLL_OE15DL3 of the first clock delay unit 120 as the CAS delay clock RDLL_OE10CL to FDLL_OE35CL, or when the CAS is latent. When the information signal CL4 is enabled, the selection unit 200 transfers the plurality of delay clocks RDLL_OE10DL4, FDLL_OE15DL4, RDLL_OE20DL4, FDLL_OE25DL4 of the second clock delay unit 140 as CAS delay clocks RDLL_OE10CL to FDLL_OE35CL. Similarly, the selection unit 200 transfers the plurality of delay clocks RDLL_OE10DL5, FDLL OE15DL5, ..., RDLL_OE30DL5, FDLL_OE35DL5 of the third clock delay unit 160 as CAS delay clocks RDLL_OE10CL to FDLL_OE35CL. Figure 7 is a circuit diagram of the initial synchronization unit 3A of Figure 3. Referring to FIG. 7, the initial synchronization unit 3A includes a disable control unit 320, a drive unit 340, a latch unit 36A, and an initialization unit 380. The deactivation control unit 320 receives a line of bursting instructions YBST and an internal 13-13426.doc } ··· " 1303441 clock CLKP4 to generate a deactivation control signal. The driving unit 340 drives an output node N1 in response to reading the CAS signal CASP6JRJD and the deactivation control signal. The latch unit 360 latches one of the output node inversion voltages and outputs the output enable signal OE00. The initialization unit 380 initializes the output node N1 in response to a power up signal PWRUP and a write/read flag WT_RDB. The deactivation control unit 320 includes an inverter 12 for inverting a burst length signal BL2, and a first NAND gate ND1 for performing one of the inverters 12 to output signals and lines. A NAND operation of the burst instruction YBST; an inverter 13 for inverting the read CAS signal CASP6_RD; a second NAND gate ND2 for performing the output signal of the first NAND gate ND1, internal a NAND operation of the clock CLKP4 and one of the inverters 13; an inverter 14 for inverting an output signal of one of the second NAND gates ND2; and a third NAND gate ND3, It is used to perform one of the output signals of the inverters 13 and 14 to output a disable control signal. The initialization unit 380 includes: an initialization signal generating unit 382 for receiving the write/read flag WT_RDB and the power-on signal PWRUP to generate an initialization signal; and a PMOS transistor PM1 having a gate for receiving The initialization signal and a source-drain path between an internal voltage (VDD) terminal and the output node N1. The operation of the initial synchronization unit 300 will be briefly described below. First, when the read CAS signal CASP6_RD is enabled to a logic high level, the drive unit 340 lowers the output node N1 to a logic low level to read 112655.doc -14 - 1303441 CAS signal CASP6_RD. Subsequently, the latch unit 360 inverts the voltage applied to the output node N1. The output enable signal OEOO is enabled to the logic high level.

When no application reads the CAS signal CASP6_RD and the burst command YBST is a logic low level or the burst length information signal BL2 is a logic high level, the initial synchronization unit 300 generates a disable control signal to return to the internal clock of the logic high level. CLKP4, thereby allowing drive unit 340 to raise output node N1. Therefore, the output node N1 is changed to a logic high level and the latch unit 360 inverts the level of the output node. Therefore, the output enable signal OEOO is deactivated. The write/read flag WTJRJDB is set to a logic when the power up signal PWRUP is not enabled because the level of the internal voltage is unstable during the initial driving of the device, or due to the application of the write command WT. At the high level on time, the initialization unit 380 raises the output node N1. Therefore, the output enable signal OEOO is disabled regardless of the input signal. FIG. 8 is a circuit diagram of the first synchronization unit 410 of FIG. The second to sixth synchronization units 420 to 480 have the same circuit configuration as the circuit configuration of the first synchronization unit 410. The first synchronization unit 410 will be described as an exemplary structure. Referring to FIG. 8, the first synchronization unit 410 includes an input unit 412, a driving unit 414, a latch unit 416, and an output control unit 418. The input unit 412 receives the output enable signal OE00 that is synchronized with the rising edge of the drive clock RCLK_OE10. The driving unit 414 drives an output node N2 to respond to the first and second output signals D2B and 112655.doc -15- 1303441 D2 of the input unit 412. The latch unit 416 latches the output applied to the driving unit 414. The signal on node N2. When a reset signal 〇E_RSTB is enabled, the output control unit 418 applies an inversion of the signal applied to the output node N2 and outputs the output enable signal OE10.

Once the first synchronization unit 410 is operated, when the reset signal 〇E_RSTB is enabled to a logic low level, the output enable signal OE10 is disabled to a logic low level regardless of the input signal. When the input signal 〇E00 is enabled and the reset signal 〇E_RSTB is deactivated, the output enable signal OE10 is output in synchronization with the rising edge of the driving clock RCLK_OE10. The operation of the output controller having the test unit 500 according to the first embodiment of the present invention will be described below with reference to Figs. First, the first to third clock delay units 120 to 160 delay the input clock by a fixed delay amount to output a plurality of delay clocks. The selection unit 200 outputs a delayed clock output from one of the first to third clock delay units 120, 140, and 160 as a CAS delay clock based on the CAS latency information signals CL3 to CL5. The test unit 500 adds an additional delay to the delay of the applied CAS delay clocks RDLL_OE10CL, FDLL_OE15CL, ..., RDLL_OE30CL, FDLL_OE35CL according to the test-delay normal signal NO_TM, the test-delay increment signal TM_INC, and the test-delay down signal TM_DEC. Or the output drive clocks RCLK OE10, RCLK OE15, ..., RCLK_OE30, FCLK_OE35 without additional delay. Similarly, when the read CAS signal CASP6_RD is enabled in response to the read command, the initial synchronization unit 300 enables the output enable signal OEOO to read the 112655.doc -16- 1303441 CAS signal CASP6_RD. Subsequently, the first synchronizing unit 410 outputs the output signal OEOO of the initial synchronizing unit 300 as the output enable signal OE10 synchronized with the first driving clock RCLK_OE10. The second synchronizing unit 420 outputs the output signal OE10 of the first synchronizing unit 410 as the output enable signal OE15 synchronized with the second driving clock FCLK_OE15. The third synchronization unit 430 outputs the output signal OE15 of the second synchronization unit 420 as the output enable signal OE20 synchronized with the third driving clock RCLK_OE20.

Accordingly, the output controller of the claimed invention generates the plurality of output enable signals OEOO through OE45, which are enabled at approximately half a clock interval from the enable time point of the read CAS signal CASP6JRD. At this time, the enable time points of the output enable signals OE00 to OE45 are adjusted by the test signals NO_TM, TM_INC and TM-DEC. In other words, the enable time point is controlled by adjusting the delay amount of the drive clock applied to the sync unit 400 based on the test signals NO_TM, TM_INC, and TM-DEC. The output controller adjusts the amount of delay required to prevent data failure based on the frequency by adjusting the amount of delay of the drive clock that controls the enable time of the output enable signal. That is, the present invention solves the problem that the prior art does not reflect the PVT variation of the actual wafer, although the delay amount is given via the conventional clock delay unit. Figure 9 is a circuit diagram of the test unit 500 of Figure 3 in accordance with a second embodiment of the present invention. Referring to FIG. 9, the test unit 500 includes a plurality of delay adjustment units 112655.doc -17- 1303441 570, 5 80, 590, 592, 594, and 596, which can be based not only on the test-delay measurement signal TM_INC, but also on the test-delay normal signal. The NOJTM and the test-delay down signal TM_DEC change the delay amount of the input clock, and can be used to determine the test based on the input clock by using the test completion signals TM-OE10, TM-OE20, and TM-OE30. FIG. 10 is a circuit diagram of the first delay adjustment unit 570 of FIG. The second to delay adjustment units 580 to 5 96 have the same circuit configuration as that of the first delay adjustment unit 570. The first delay adjustment unit 57 is described as an exemplary structure. Referring to FIG. 10, the first delay adjustment unit 570 includes first and second delay units 571 and 572, first to third transfer gates TG7, TG8, and TG9, a first control unit 573, and a second control unit 574. And a third control unit 575. The first and second delay units 571 and 572 are connected in series to delay the input clock RDLL_OE10CL. When a corresponding control signal is enabled, the first to third transfer gates TG7 to TG9 transfer the input and output signals of the first and second delay units 571 and 572 as the first drive clock rcLK_OE10. The first control unit 573 receives the first test completion signal TM_OE 10 and the test-delay reduction signal TM-DEC to control the driving of the first transfer gate TG7. The second control unit 574 receives the first test completion signal TM_OE 10 and the test-delay normal signal NO_TM to control the driving of the second transfer gate TG8. The third control unit 575 receives the first test completion signal ΤΜ_ΟΕ10 and the test-delay increment signal TM_INC to control the driving of the third transfer gate TG9. The first to third control units 573 to 575 have the same circuit configuration of 112655.doc -18 - • 1303441 except for the input signal. The first control unit 573 includes: a NAND gate ND5 for performing one NAND operation of the first test completion signal TM-OE10 and the test-delay reduction signal TM-DEC; and an inverter 17 for The output signal of one of the NAND gates ND5 is inverted to output a first control signal. The operation of the test unit 500 according to the second embodiment of the claimed invention will be described in detail. In the test unit 5, the delay amount of the driving clock is not completely controlled according to the test-delay reduction signal TM-DEC, the test_delay normal signal NO-TM, and the test-delay increment signal tmjnc, but can be borrowed The use of the test is selected according to the clock using the test completion signal TM(:^10 to TM_〇E3〇. That is, unlike the first embodiment, the invention according to the application can be executed according to the drive clocks. The test unit of the second embodiment. Since the output controller controls the enable time point of the output enable signal by using the test signal, the delay amount required to prevent data failure can be adjusted according to the drive frequency and the change of ρντ. The above description has been made for an output controller that controls timing when outputting data in response to a read command, but when applying a flag signal such as reading a CAS signal, the claimed invention can also be applied to a plurality of of which are enabled at regular intervals. The block of the tiger, that is, when t generates a plurality of signals from the flag signal at regular intervals, the required delay amount can be adjusted according to the frequency. The subject matter of the Korean Patent Application No. 2〇〇5_9〇888 and 2005 13 0444, which were filed on September 29, 2005 and December 27, 2005, by the Korea Intellectual Property Office, the entire contents of which are incorporated by reference. The present invention has been described in terms of a particular preferred embodiment, and it will be apparent to those skilled in the art that the invention may be devised without departing from the scope of the invention as defined in the following claims. Various changes and modifications are made in the context of the invention. [Simplified Schematic] FIG. 1 is a block diagram of an output controller of the prior art; FIG. 2A is a conventional output controller operating at a low frequency. FIG. 2B is a waveform diagram for explaining the problem of the conventional output controller operating at a high frequency; FIG. 3 is a schematic diagram of a spurt according to the present invention. FIG. 4 is a circuit diagram of the test unit shown in FIG. 3 according to a first embodiment of the present invention; FIG. 5 is a circuit diagram of a delay adjustment unit shown in FIG. 4; a circuit diagram showing one of the selection units; 7 is a circuit diagram of an initial synchronization unit shown in FIG. 3. FIG. 8 is a circuit diagram of one of the synchronization units shown in FIG. 3. FIG. 9 is a circuit diagram of the test unit shown in FIG. 3 according to a second embodiment of the present invention. And Fig. 10 is a circuit diagram of one delay adjustment unit shown in Fig. 9. [Description of main component symbols] 10 clock delay unit 20 selection unit 112655.doc 1303441 30 initial synchronization unit 40 synchronization unit 100 clock delay unit 120 first Clock delay unit 140 Second clock delay unit 160 Third clock delay unit 200 Selection unit 210 First selector 220 Second selector 230 Third selector 240 Fourth selector 250 Fifth selector 260 Sixth selection 300 initial synchronization unit 320 deactivation control unit 340 drive unit 360 latch unit 380 initialization unit 400 synchronization unit 410 first synchronization unit 412 input unit 414 drive unit 416 latch unit 418 output control unit-21 - ·, ϋ 1 »*- 5 . 112655.doc 1303441

420 second synchronization unit 430 third synchronization unit 440 fourth synchronization unit 450 fifth synchronization unit 460 sixth synchronization unit 470 seventh synchronization unit 480 eighth synchronization unit 500 test unit 510 first delay adjustment unit 512 first delay unit 514 Second delay unit 520 second delay adjustment unit 530 third delay adjustment unit 540 fourth delay adjustment unit 550 fifth delay adjustment unit 560 sixth delay adjustment unit 570 first delay adjustment unit 571 first delay unit 572 second delay unit 573 first control unit 574 second control unit 575 third control unit 580 second delay adjustment unit 590 third delay adjustment unit 112655.doc -22- 1303441

592 Fourth delay adjustment unit 594 Fifth delay adjustment unit 596 Sixth delay adjustment unit 112655.doc -23-

Claims (1)

1303441 X. Patent Application Range·· 1 · An output controller comprising: an initial synchronization unit 'for initializing a first output enable signal when a read CAS signal is enabled; a plurality of serial connections An additional synchronization unit level, each of which is configured to output an output signal of a previous stage as an output enable signal synchronized with a corresponding driving clock, and the first one of the levels receives the first output enable signal; and a test unit for adjusting an amount of delay of the clock according to the plurality of test signals and outputting the drive clock of the drive clock 2, wherein the test unit includes a plurality of delay adjustment units, the delays The adjusting unit increases or decreases the delay amount of the input clock according to a test_delay increment signal, a test-delay reduction signal, and a test-delay normal signal, and outputs a driving clock. The output controller of claim 2, wherein when the test_delay normal signal is enabled, the delay adjustment unit outputs the drive clock by adding a "normal delay" to the corresponding input clock, when the test When the delay increment is enabled, it outputs the drive clock by adding a delay longer than the normal delay, and when the test delay decrement signal is enabled, it outputs the corresponding input clock as the drive pulse. 4. The output controller of claim 3, wherein the delay adjustment unit comprises: a first delay unit for delaying the input clock; and a delay unit for delaying an output of the first delay unit Signal; 112655.doc 1303441 - a first-transfer gate that is used to transfer the input clock as the drive clock to return a test "delay reduction signal; a second transfer gate for transferring the first The output of the delay unit is used as the driving clock to return the test and delay the normal signal; and a third transfer gate is used for transferring the output signal of the second delay unit as the driving clock to return the test-delay Incremental signal. 5. The output controller of claim 4, wherein the first delay unit and the second delay unit comprise a plurality of inverters connected in series. #6. The output controller of claim 1, further comprising: a clock delay unit for delaying a rising delay locked loop (DLL) clock and a falling DLL clock according to a corresponding CAS latent time information a delay amount of the signal determination; and a selection block for selecting a signal corresponding to the CAS latent information signal among the output signals of the clock delay unit, and applying the selected signal as the test unit The input clock. 7. The output controller of claim 6, wherein the clock delay unit comprises: _ a first clock delay unit for delaying the rising DLL clock and the falling DLL according to a first CAS latent information signal The clock outputs a plurality of first delay clocks; a second clock delay unit configured to delay the rising DLL clock and the falling DLL clock according to a second CAS latent information signal to output a plurality of second a delay clock; and a third clock delay unit, configured to delay the rising DLL clock and the falling DLL clock according to a third C AS latent information signal to output a plurality of third delays of 112655.doc 1303441 a clock, wherein each of the first clock delay unit to the third clock delay unit has a different amount of delay from each other. 8. The output controller of claim 7, wherein when the first-CAS latency information signal is enabled, the selection block outputs the plurality of first delay clocks as the input clocks, when the second CAS When the latent time information signal is enabled, the plurality of second delayed clocks are output as the input clocks, and when the second CAS latent time information signal is enabled, the plurality of third delayed clocks are output as These input clocks. 9. The output controller of claim 8, wherein the selection block includes first to sixth selection units for receiving the plurality of first to third delay time pulses and outputting a clock as the driving time The pulse should return the first ca S latent information signal to the third CAS latent information signal. The output controller of claim 9, wherein the first selection unit comprises: a fourth transfer gate, configured to transfer the plurality of first delay clocks when the first c AS latency information signal is enabled The first clock; a fifth transfer gate, configured to transfer the first clock of the plurality of second delay clocks when the second CAS latent information signal is enabled; a sixth transfer gate, The first clock is used to transfer the plurality of third delay clocks when the third CAS latency information signal is enabled; and the first inverter is configured to apply one to the fourth The voltage is inverted by the transfer gate to a common output node of the sixth transfer gate to output the first drive clock. 11. The output controller of claim 10, wherein the initial synchronization unit comprises: 1126551doc 1303441 V control unit for receiving a line of burst instructions and the internal clock to generate a disable control signal; a driving unit for driving an output node to read back the CAS signal and Deactivating the control signal; a first latching H unit for latching one of the input (four) points of the inverted voltage and outputting the first output enable signal; and a chemistry unit for initializing the output node In response to a power-on signal and a write operation. 12. A semiconductor device for controlling a data output timing, comprising: an initial sync unit 70 for outputting a first output enable signal when a read CAS signal is enabled; synchronizing a plurality of serial connections The unit, each of which is configured to output a front, and an output signal as an output enable signal synchronized with a corresponding drive clock, the first synchronization unit of the plurality of synchronization units receiving the first output And a test unit for adjusting a delay amount of an input clock based on the plurality of test-delay adjustment signals and outputting a plurality of drive clocks to respond to the plurality of test completion signals. 13. The semiconductor device of claim 12, wherein the test unit comprises first to eighth delay adjustment units, each of which is configured to output the input when one of the plurality of test completions = a corresponding signal is enabled The clock is used as the driving pulse, and is increased or decreased according to a test delay signal, a test_delay reduction signal, and a test_delay positive tenth, when a corresponding test completion signal is deactivated. The 112655.doc 1303441 drive clock is output by the delay amount of the input clock. 14. The semiconductor device of claim 13, wherein the first delay adjustment unit comprises: a delay unit for delaying the driving clock; and a second delay unit for delaying output of one of the first delay units a signal; a diverter gate for transferring the input clock as the driving clock to respond to a first control signal; a first transfer gate for transferring the output signal of the first delay unit as the drive clock to respond to the second control signal; a third transfer gate for transferring one of the output signals of the second delay unit The first control signal is received in response to a third control signal; the first control unit is configured to receive a first test completion signal and the test-delay reduction signal to generate the first control signal; a second control unit, It is configured to receive the first completion signal and the column test-delay normal signal to generate the second control signal, and the second control unit is configured to receive the test completion signal and the net test delay delay signal To generate the third control signal. The semiconductor device of claim 14, wherein the first control unit comprises a -NAN gate for performing the first test completion signal and the test-delay reduction signal 2 - NAND operation, and a first inverter for inverting one of the first NAND gates to rotate the first control signal; the second control unit includes: a first NAND gate for performing The first type of signal and the test _ 112655.doc 1303441 delay the normal signal - NAND operation; and - the second inverter is used to invert the output signal of one of the first NAND gates of the s Outputting the second control signal 'and-the second control unit includes: a third nand idler for performing the first test completion signal and the test/delay increment signal-NAND operation; and a third reverse And a phase detector for inverting an output signal of one of the third sub D gates to output the third control signal. The semiconductor device of claim 14, wherein the first delay unit and the second delay unit are constructed with a plurality of inverters connected in series. The semiconductor device of claim 12, further comprising: a clock delay unit for delaying a rising DLL·clock and a falling dll clock by a delay amount determined according to the corresponding CAS latent information signal; and And selecting a block for selecting a signal corresponding to the CAS latent information signal from the output signal of the clock delay unit, and outputting the selected signal as the input clock of the test unit. 18. The semiconductor device of claim 17, wherein the clock delay unit comprises: a first clock delay unit for delaying the rising DLL clock and the falling DLL according to a first C as latent time information signal The clock outputs a plurality of first delay clocks; a second clock delay unit configured to delay the rising DLL clock and the falling DLL clock according to a second C AS latency information signal to turn the plural a second delay clock; and a third clock delay unit for delaying the rising DLL clock and the falling DLL clock according to a third CAS latency 112655.doc -6 - 1303441 signal signal A plurality of third delay clocks are output, wherein each of the first clock delay unit to the third clock delay unit has a different amount of delay from each other. The semiconductor device of claim 18, wherein when the first CAS latent information signal is enabled, the selected block outputs the plurality of first delayed clocks as the plurality of input clocks, when the second CAS When the latent time information signal is enabled, it outputs the plurality of second delayed clocks as the plurality of input clocks, or when the third CAS latent time information signal is enabled, it outputs the plurality of second delay clocks As the multiple input clocks. 20. The semiconductor device of claim 19, wherein the selection block comprises first to sixth selection units for receiving the plurality of first to third delay clocks to output one of the input clocks The clock serves as the corresponding driving clock to respond to the first CAS latent information signal to the third cas potential information signal. 21. The semiconductor device of claim 20, wherein the first selection unit comprises: a fourth transfer gate for transferring the plurality of first delayed clocks when the first CAS latent information signal is enabled a first clock; a fifth transfer gate, configured to receive one of the plurality of second delay clocks when the second CAS latency information signal is enabled; a sixth transfer gate And a first clock for receiving the plurality of third delay clocks when the third time information signal is enabled; and an inverter for applying a fourth transfer gate to the sixth The voltage on one of the transfer gates is inverted on the common output node to output the 112965.doc 1303441 drive clock. The semiconductor device of claim 21, wherein the initial synchronization unit comprises: a disable control unit for receiving a line of burst instructions and the internal clock to generate a disable control signal; a driver for Driving an output node to read back the cAS signal and the deactivation control signal; a latch unit for inverting a voltage applied to the output node, latching the inverted voltage and And outputting the latched signal as the first output enable signal; and an initialization unit for initializing the output node in response to a power up signal and a write operation. An output controller comprising: a plurality of serially connected synchronization units, each of which is configured to output a plurality of interval signals by synchronizing one of the January 'J level one output signals with a corresponding drive clock The first synchronization unit of the plurality of synchronization units receives a flag signal; and a test unit is configured to adjust an amount of delay of an input clock to output the drive clock according to the plurality of test signals. The output controller of claim 23, wherein the test unit comprises a plurality of delay adjustment units for increasing or according to a test_delay reduction signal, a test-delay increment signal, and a test delaying normal signal The amount of delay of the input clock is reduced and the individual drive clock is output. 25. The output controller of claim 24, wherein when the test-delay normal signal is enabled, the delay adjustment unit outputs the drive clock by adding a normal delay to the corresponding input clock of the H2655.doc 1303441 When the test_delay increment signal is enabled, it outputs the drive clock by adding a delay longer than the normal delay; and when the test delay delay signal is enabled, it outputs the corresponding input clock As the driving clock. The output controller of claim 25, wherein the delay adjustment unit comprises: a first delay unit for delaying the input clock; and a second delay unit for delaying one of the first delay units An output signal; a first transfer gate for transferring the input clock as the drive clock to return a test_delay reduction signal; and a second transfer gate for transferring the output signal of the first delay unit As the driving clock, the test-delay normal signal is returned; and a third transfer gate is used to transfer one of the output signals of the second delay unit as the driving clock to respond to the test-delay increment signal. 27. A semiconductor device for controlling a data output timing, comprising: a plurality of serially connected sync sheets & each of which is configured to output a signal from a previous stage and a corresponding drive clock Synchronizing and outputting a plurality of interval signals, wherein the first synchronization unit of the plurality of synchronization units receives a flag signal; and a test unit configured to adjust the input signal based on the plurality of test_delay adjustment signals The pulse selects the _ delay amount of the signal and outputs the plurality of drive clocks in response to the plurality of test completion signals. 28. The semiconductor device of claim 27, wherein the test unit comprises first to sixth delay adjustment units for outputting the input clock as the corresponding signal of the plurality of test completion signals 112655.doc 1303441 is enabled The driving clock, t increases or decreases the delay amount of the input clock by stopping the data according to the -test-delay signal, the test-delay down signal, and the test delaying normal signal after the corresponding test completion signal is stopped. And output the pulse. 29. The semiconductor device of claim 28, wherein the first delay adjustment unit comprises: a delay unit for delaying the drive clock; and a first delay unit 70 for delaying one of the first delay units a first transfer gate for transferring the input clock as the drive clock in response to a first control signal; "a second transfer gate for transferring the wheel of the first delay unit The output signal is used as the driving clock to respond to a second control signal; a third transfer gate is used for transferring one of the second delay units to turn the 丨tit number as the driving clock to respond to the third control signal; a first control unit, configured to receive a first test completion signal and a blue test 4 - delay decrement signal to generate the first control signal; - a second control unit, configured to receive the first completion signal and the test 4 - delaying the normal signal to generate the second control signal; and - the third control unit 'for receiving the test completion signal and the test-delay increment signal to generate the third control signal. 30. Semi-guide The first control unit includes: - a - NAND gate 15 for performing the first test completion signal and 112655.doc -10- 1303441 one of the test-delay reduction signals NAND operation; and a first An inverter for inverting an output signal of one of the first NAND gates to output the first control signal; the second control unit includes: a second NAND gate for performing the first a test completion signal and a NAND operation of the test-delay normal signal; and a second inverter for inverting an output signal of one of the second NAND gates to output the second control signal; The third control unit includes: a third NAND gate for performing the NAND operation of the first test completion signal and the test-delay increment signal; and a third inverter for using the third One of the NAND gate output signals is inverted to output the third control signal 112655.doc -11 -