KR102898303B1 - Control circuit and semiconductor memory device - Google Patents

Abstract

[Task] To provide a control circuit capable of suppressing the prolongation of delay operation and completing a sequence for adjusting the delay of an internal clock signal using a DLL circuit within a predetermined execution period.
[Solution] The control circuit is a control circuit including a delay control unit (10) that generates an output clock signal by delaying an input clock signal based on a phase difference between an input clock signal and an output clock signal, and further includes a clock control unit (17), wherein, when the phase difference is equal to or greater than a first predetermined amount, the clock control unit inputs a clock signal, in which the phase of the input clock signal is delayed by a second predetermined amount, as an input clock signal, to the delay control unit.

Description

Control circuit and semiconductor memory device

The present invention relates to a control circuit and a semiconductor memory device.

DRAM (Dynamic Random Access Memory), a type of semiconductor memory device, is a volatile memory that stores information by accumulating electric charge in a capacitor (condenser) and loses the stored information when power is cut off. DRAM is equipped with a delay locked loop (DLL) circuit as a phase-locked circuit. DRAM uses the DLL circuit to generate an internal clock signal for outputting a data signal by synchronizing it with an input clock signal input from an external source. For example, a DLL circuit such as the one described in Patent Document 1 is known.

US 2012/0194241 A

However, when adjusting the delay of an internal clock signal using a DLL circuit, a sequence is executed that includes, for example, a reset operation of the DLL circuit, a delay (lock) operation of the DLL circuit (for example, an operation of synchronizing an external clock and an internal clock by activating delay lines one by one), and an operation of detecting an N value indicating the number of delay clock cycles between an input clock signal and an internal clock signal.

Here, the lock time (Tdll) due to the delay operation of the DLL circuit can be expressed by the following equation.

Tint+Tdll=N×tCK

In the above equation, Tint represents the inherent delay time in the DLL circuit, and tCK represents the clock cycle. For example, if the clock cycle (tCK) becomes longer than the inherent delay time (Tint) due to the temperature in the semiconductor memory device, etc., the lock time (Tdll) due to the delay operation of the DLL circuit also becomes longer as expressed in the above equation. If the lock time becomes longer in this way, the execution time of the entire sequence becomes longer, and there is a concern that the execution of the next sequence may be delayed. In particular, if the delay becomes longer, there is a concern that the execution period (tDLLK) of the sequence determined in advance may be exceeded. In addition, in order to cope with the current high-speed semiconductor integrated circuits, it is desirable to speed up the delay operation during the sequence as much as possible.

The synchronous circuit described in Patent Document 1 is intended to speed up such delay operation, but its configuration is complex, and a simpler configuration is desirable.

The present invention has been made in consideration of the above-mentioned problems, and its purpose is to provide a control circuit and a semiconductor memory device capable of suppressing prolonged delay operation with a simple configuration.

The control circuit of the present invention is a control circuit including a delay control unit that generates the output clock signal by delaying the input clock signal based on the phase difference between the input clock signal and the output clock signal, and further includes a clock control unit, wherein the clock control unit is characterized in that, when the phase difference is equal to or greater than a first predetermined amount, inputs a clock signal, which delays the phase of the input clock signal by a second predetermined amount, as the input clock signal, to the delay circuit.

In the present invention, when the phase difference is equal to or greater than the first predetermined amount, the clock control unit inputs a clock signal whose phase is delayed by a second predetermined amount as the input clock signal to the delay circuit, thereby performing a delay operation using the clock signal delayed by the second predetermined amount, thereby shortening the phase difference between the input clock signal and the output clock signal. This makes it possible to suppress the delay operation from becoming prolonged.

The clock control unit is preferably configured to input a first input clock signal and a second input clock signal whose phase is delayed by the second predetermined amount from the first input clock signal, and the clock control unit preferably selects the second input clock signal as the input clock when the phase difference is equal to or greater than the first predetermined amount. By configuring the circuit so that one of the first input clock signal and the second input clock signal can be selected based on whether or not the phase difference is equal to or greater than the first predetermined amount, there is no need to delay the input clock signal in order to generate the second clock signal whose phase difference is equal to or greater than the first predetermined amount. In other words, by generating two input clocks in advance in this way, there is no need to delay the input clock signal according to the control, so that the lengthening of the delay operation can be further suppressed, and at the same time, it is possible to simplify the configuration of the entire circuit.

The above clock control unit preferably determines whether the phase difference is equal to or greater than the first predetermined amount at a predetermined timing after the start of the delay operation. The entire circuit can determine the phase difference at a predetermined timing after the start of a stable delay operation.

The above delay control unit preferably includes a phase detection unit that detects the phase difference between the input clock signal and the output clock signal, and the phase difference detected by the phase detection unit is input to the clock control unit. By inputting the phase difference detected by the phase detection unit of the delay control unit to the clock control unit, it is possible to make the entire control circuit into a simple configuration.

The clock control unit preferably includes a selection signal generation unit and an internal clock selection unit into which the selection signal generated by the selection signal generation unit is input, wherein the selection signal generation unit generates a selection signal indicating whether the phase difference is equal to or greater than a predetermined value, and the internal clock selection unit is configured to select one of the first input clock signal and the second input clock signal based on the selection signal. By configuring it in this way, it is possible to make the entire circuit into a simple configuration.

It is preferable that the above first predetermined amount be 180 degrees. By setting the first predetermined amount to 180 degrees, the entire control circuit is easy to control, and it is also possible to make the entire circuit into a simple configuration.

It is preferable that the above second predetermined amount be 180 degrees. By setting the second predetermined amount to 180 degrees, the entire control circuit becomes easy to control, and also, it is possible to make the entire circuit into a simple configuration.

It is preferable that an input buffer into which an external clock signal is input is included, wherein a first input clock signal is generated from the external clock signal in the input buffer, and a second input clock signal is generated by inverting the external clock signal, or an input buffer into which an external clock signal is input is included, and wherein, in the input buffer, a first input clock signal is generated from the external clock signal in the input buffer, and a second input clock signal is generated from a compensation clock signal of the external clock signal in the input buffer. By configuring the input buffer in this way, the first input clock signal and the second input clock signal can be stably supplied to a control circuit, and can be generated simply.

It is preferable to perform the delay operation based on the phase difference between the rising edge of the second input clock signal and the rising edge of the output clock signal. By performing the delay operation at the rising edges of the two signals in this way, the time required for the delay operation is shortened, thereby suppressing its extension.

The semiconductor memory device of the present invention is characterized by including any of the control circuits described above. By including any of the control circuits, the execution time of a sequence can be shortened, and since the control circuit is included so that the execution time of the sequence does not exceed a predetermined period of the sequence, the return operation from the predetermined sequence can be fast, and the response time can be shortened.

As a preferred embodiment of the present invention, the semiconductor memory device may be a dynamic random access memory.

According to the control circuit, semiconductor memory device and method for controlling a semiconductor memory device of the present invention, it is possible to suppress the prolongation of delay operation.

Fig. 1 is a block diagram showing an example configuration of a control circuit according to an embodiment of the present invention.
Fig. 2(1) is a drawing showing the configuration of an input buffer, and Fig. 2(2) is a drawing showing the configuration of a phase detection unit.
Figure 3 is a diagram showing the configuration of a clock control unit.
Fig. 4(1) is a block diagram showing an example of a configuration of a conventional control circuit, and Fig. 4(2) is a time chart showing the relationship between an input clock signal and a delay time within the conventional control circuit.
Fig. 5(1) is a time chart showing the relationship between an input clock signal and a delay time when the phase difference is 180 degrees or more, and Fig. 5(2) is a time chart showing the relationship between an input clock signal and a delay time when the phase difference is less than 180 degrees.
Figures 6(1) and (2) are drawings showing each state of the present sequence and the conventional sequence.
Figure 7 is a time chart showing the voltage trend of signals of each part in the control circuit when the phase difference is 180 degrees or more.
Figure 8 is a time chart showing the voltage trend of signals of each part in the control circuit when the phase difference is less than 180 degrees.
Figure 9 is a block diagram showing another configuration of an input buffer.

Hereinafter, a control circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the attached drawings. However, this embodiment is an example, and the present invention is not limited thereto.

In addition, the notations "first," "second," etc. in this specification and elsewhere are used to distinguish certain components from other components, and are not intended to limit the number, order, priority, etc. of the components. For example, if there is a description of "first element" and "second element," it does not mean that only two elements, "first element" and "second element," are employed, nor does it mean that the "first element" must precede the "second element."

Fig. 1 shows a DLL circuit (1) (control circuit) according to an embodiment of the present invention. In addition, in the present embodiment, the control circuit is installed in a semiconductor memory device such as a DRAM, for example.

In addition, in this embodiment, in order to simplify the explanation, well-known components installed in semiconductor memory devices such as DRAM (e.g., N value detection unit, latency control unit, command decoder, memory cell array, interface unit for input/output, etc.) are not shown.

The DLL circuit (1) includes an input buffer (11), a phase detection unit (12), a DLL control unit (13), a delay circuit (14), a replica unit (15), an output buffer (16), and a clock control unit (17). The delay control unit (10) of the present embodiment is configured from the phase detection unit (12), the DLL control unit (13), the delay circuit (14), and the replica unit (15). In addition, the delay control unit (10) may be configured at least with the phase detection unit (12), the DLL control unit (13), and the delay circuit (14). When a sequence is started, the DLL circuit (1) first performs a reset operation for resetting the delay circuit (14) of the DLL circuit (1) to an initial state, and then performs a delay operation for delaying an input clock signal in the delay circuit (14) to generate a desired output clock signal. That is, in the present embodiment, the sequence control includes the reset operation and the delay operation in this order.

The input buffer (11) buffers the clock signal (CLKT) and the clock signal (CLKC) input to the input buffer (11), and generates a first clock signal (clk000) having the same phase as the clock signal (CLKT) and a second clock signal (clk180) having the same phase as the clock signal (CLKC). Specifically, as shown in Fig. 2(1), the input buffer (11) includes an amplifier (111). Two complementary clock signals (CLKT) and a clock signal (CLKC) as external clock signals are input to the amplifier (111). The input clock signal (CLKT) and the clock signal (CLKC) are amplified in the amplifier (111), thereby generating a first clock signal (clk000) and a second clock signal (clk180). The second clock signal (clk180) is generated as a clock signal that inverts the first clock signal (clk000).

Returning to Fig. 1, the generated first clock signal (clk000) and second clock signal (clk180) are input to the clock control unit (17), and the first clock signal (clk000) is also input to the phase detection unit (12) as a reference clock signal (ref_clk). That is, the reference clock signal (ref_clk) is identical to the first clock signal (clk000).

The clock control unit (17) also receives a phase signal (up/down) and a reset signal (dll_reset_n) output from the phase detection unit (12). The reset signal (dll_reset_n) indicates that the reset operation has been completed when it is at a high level. As described in detail later, the clock control unit (17) outputs one of the first clock signal (clk000) and the second clock signal (clk180) as an input clock signal (in_clk) based on the phase signal (up/down), and this input clock signal (in_clk) is input to the delay circuit (14).

The delay circuit (14) generates a delayed signal (output clock signal) (dll_clk) that delays the input clock signal (in_clk) input from the clock control unit (17) based on the delay amount set by the DLL control unit (13), and transmits the delayed signal (output clock signal) (dll_clk) to the output buffer (16) and the replica unit (15). The delayed signal (dll_clk) input to the output buffer (16) is buffered within the output buffer (16) and output as an output signal (DQS), and the replica unit (15) outputs the delayed signal (dll_clk) generated by the delay circuit (14) as a feedback signal (fb_clk). The feedback signal (fb_clk) is input to the phase detection unit (12).

A reference clock signal (ref_clk) and a feedback signal (fb_clk) are input to the phase detection unit (12). In the phase detection unit (12), a phase signal (up/down) representing a phase advance (delay less than 180 degrees) or delay (delay more than 180 degrees) of the feedback signal (fb_clk) with respect to the reference clock signal (ref_clk) is generated and input to the DLL control unit (13).

Specifically, the phase detection unit (12) is configured with a D-flip-flop circuit (121), as shown in Fig. 2(2). In the D-flip-flop circuit (121), a feedback signal (fb_clk) is input as an input signal, a reference clock signal (ref_clk) is input as a clock signal, and a phase signal (up/down) is output as an output signal. When the feedback signal (fb_clk) is delayed by less than 180 degrees with respect to the reference clock signal (ref_clk), the generated phase signal (up/down) becomes a high level (up), and when the feedback signal (fb_clk) is delayed by more than 180 degrees with respect to the reference clock signal (ref_clk), the generated phase signal (up/down) becomes a low level (down).

Returning to Fig. 1, the DLL control unit (13) determines the delay amount from the phase difference detected by the phase detection unit (12). Specifically, the DLL control unit (13) generates and outputs a control signal (dll_code) composed of multiple bits as a signal representing the delay amount in the delay operation, based on the phase signal (up/down) from the phase detection unit (12). This output control signal (dll_code) is input to the delay circuit (14).

The delay circuit (14) is a variable delay unit that performs a delay operation. Specifically, the delay circuit (14) delays the input clock signal (in_clk) by activating the delay line according to the control signal (dll_code) to generate a delay signal (dll_clk).

In addition, the DLL control unit (13) determines that the delay operation has ended when it determines that the feedback signal (fb_clk) corresponding to the input clock signal (in_clk) and the delay signal (dll_clk) have reached a predetermined range based on the phase signal (up/down). As a result, the delay operation ends.

In this way, in the DLL circuit (1) of the present embodiment, the delay control unit (10) delays the input clock signal (in_clk) based on the phase difference between the input clock signal (in_clk) and the feedback signal (fb_clk), which is the delay signal (dll_clk), to generate the delay signal (dll_clk). Hereinafter, the clock control unit (17) that controls the input clock signal (in_clk) input to the delay control unit (10) will be described.

A phase signal (up/down), a reset signal (dll_reset_n), a first clock signal (clk000) and a second clock signal (clk180) are input to a clock control unit (17). The clock control unit (17) selects either the first clock signal (clk000) or the second clock signal (clk180) as an input clock signal (in_clk) and outputs the input clock signal (in_clk) to the delay circuit (14). Before the delay operation, the clock control unit (17) selects the first clock signal (clk000) as the input clock signal (in_clk). When the delay operation starts, either the first clock signal (clk000) or the second clock signal (clk180) is selected as the input clock signal (in_clk) according to the phase signal (up/down).

The details of the configuration of the clock control unit (17) are explained using Fig. 3. The clock control unit (17) includes a timing signal generation unit (171), a selection signal generation unit (172), and an internal clock selection unit (173).

The timing signal generation unit (171) generates a timing signal (sel_clk) indicating the timing of the passage of a predetermined period of time after the start of the delay operation, and inputs the timing signal to the selection signal generation unit (172). This predetermined period of time is for selecting a clock after the DLL circuit (1) becomes stable when selecting a clock after the reset operation.

The selection signal generation unit (172) determines whether the phase difference between the input clock signal (reference clock signal (ref_clk)) and the output clock signal (feedback signal (fb_clk)) of the delay control unit (10) is 180 degrees or more when the timing signal (sel_clk) indicates the timing of the passage of a predetermined period of time, and generates a selection signal (sel180) indicating the determination result and inputs it to the internal clock selection unit (173). Here, a phase signal (up/down) is used to determine whether the phase difference between the input clock signal and the output clock signal of the delay control unit (10) is 180 degrees or more. As described above, when the feedback signal (fb_clk) (same phase as the output clock signal of the delay control unit (10)) is delayed by less than 180 degrees with respect to the reference clock signal (ref_clk) (same phase as the input clock signal of the delay control unit (10)), the phase signal (up/down) becomes high level (up), and when the delay is 180 degrees or more, the generated phase signal (up/down) becomes low level (down), so that judgment can be made simply using this phase signal (up/down). That is, when the timing signal (sel_clk) indicates the timing of the passage of a predetermined period, the selection signal generation unit (172) judges whether the phase signal (up/down) is 180 degrees or more, generates a selection signal (sel180) indicating the judgment result, and inputs it to the internal clock selection unit (173).

The internal clock selection unit (173) selects one of the first clock signal (clk000) and the second clock signal (clk180) as the input clock signal (in_clk) based on the judgment result indicated by this selection signal (sel180), and outputs the input clock signal (in_clk).

The clock control unit (17) is further explained using FIGS. 4 to 6.

In the conventional example shown in Fig. 4(1), the DLL circuit (1A) differs from the present embodiment in that it does not include a clock control unit (17). In the DLL circuit (1A), a clock signal (CK) output from an input buffer (11A) is input to a delay control unit (10A) (phase detection unit (12A), DLL control unit (13A), and delay circuit (14A)), and a delay signal (dll_clk) is output. In a conventional example of this configuration, as shown in Fig. 4(2), if the feedback signal (fb_clk) is delayed by the inherent delay (Tint) and changes from the low level to the high level at time t2 while the clock signal (CK) changes from the low level to the high level at time t1, the period t1 to t2 is less than half a cycle of the clock signal (CK), so that the feedback signal (fb_clk) is delayed by 180 degrees or more with respect to the cycle of the clock signal (CK). Then, when the delay circuit (14A) performs a delay operation with respect to the clock signal (CK) so that the clock signal (CK) and the feedback signal (fb_clk) (i.e., the output signal (DQS)) are synchronized, the rising edge of the clock signal (CK) and the rising edge of the output signal (DQS) coincide at time t5. In this way, in the conventional example, when the feedback signal (fb_clk) before the delay operation is delayed by more than half a clock cycle with respect to the clock signal (CK), i.e., the phase difference is more than 180 degrees, the lock time (Tdll), which is the delay amount to be resolved by the delay operation, becomes a period of t2 to t5, so there is a possibility that the delay operation may be prolonged.

In this regard, in the present embodiment, the delay operation is suppressed from becoming prolonged by including a clock control unit (17) that inputs either the first clock signal (clk000) or the second clock signal (clk180) as an input clock signal (in_clk) to the delay circuit (14) (delay control unit (10)) according to the phase signal (up/down). First, since the input clock signal (in_clk) input to the delay control unit (10) before the delay operation is the first clock signal (clk000), the input clock signal (in_clk) and the first clock signal (clk000) are in the same phase. When the phase difference between the first clock signal (clk000) and the feedback signal (fb_clk) of the same phase as the delay signal (dll_clk) output from the delay control unit (10) is 180 degrees or more, the clock control unit (17) outputs the second clock signal (clk180) as the input clock signal (in_clk) to the delay circuit (14). As a result, fb_clk, which is of the same phase as the output clock signal from the delay circuit (14), is also delayed by 180 degrees. As a result, in the delay control unit (10), by performing a delay operation according to the phase difference between the rising edge of the second clock signal (clk180) and the rising edge of the feedback signal (fb_clk) delayed by 180 degrees, synchronization of the input clock signal (in_clk) and the feedback signal (fb_clk) is terminated early, and a desired output signal (DQS) can be generated.

A case where the phase difference between the feedback signal (fb_clk) and the input clock signal (in_clk) after a delay operation is 180 degrees or more will be specifically described. As shown in Fig. 5(1), while the input clock signal (in_clk), the first clock signal (clk000), changes from a low level to a high level at time t11, the feedback signal (fb_clk) is delayed by a unique delay (Tint) and changes from a low level to a high level at time t12. Since the period t11 to t12 representing this phase difference is less than half a cycle of the clock signal (CK), the feedback signal (fb_clk) is delayed by 180 degrees or more with respect to the cycle of the input clock signal (in_clk). In this case, the clock control unit (17) selects the second clock signal (clk180) as the input clock signal (in_clk). By this, the delay control unit (10) performs a delay operation on the second input clock signal (clk180) so that the rising edge of the second clock signal (clk180) at time t13 and the rising edge of the 180-degree delayed feedback signal (fb_clk) at time t14 are at the same timing (so that the second clock signal (clk180) and the feedback signal (fb_clk) are synchronized). As a result, the lock time (Tdll), which is a delay that must be resolved by the delay operation, becomes a period of t14 to t15.

To summarize, as shown in Fig. 6(1), in the conventional example, when the phase difference between the input clock signal and the output clock signal in the delay control unit (10) is 180 degrees or more, the lock time (Tdll) is prolonged, thereby prolonging the time of the entire sequence. In contrast, in the present embodiment, when the phase difference between the input clock signal and the output clock signal in the delay control unit (10) is 180 degrees or more, the DLL circuit (1) is configured so that the second input clock signal (clk180) can be made into the input clock signal (in_clk), so that the delay operation can be completed early, and the time of the entire sequence can be shortened.

In addition, a case in which the phase difference between the feedback signal (fb_clk) and the input clock signal (in_clk) after the delay operation is less than 180 degrees is shown in Fig. 5(2). In this case, since the phase difference is small, the clock signal (clk000) is selected as the input clock signal (in_clk). As a result, as in the conventional example, the delay circuit (14) performs a delay operation for clk000 so that the rising edge of the clock signal (clk000) at time t21 and the rising edge of the feedback signal (fb_clk) at time t22 coincide, and as a result, the inherent delay (Tint) is a period from t21 to t22, and the lock time (Tdll) is a period from t22 to t23. When a delay operation is performed in this manner, as shown in Fig. 6(2), the delay operation can be performed early, as in the case where the delay is less than 180 degrees, so that the time of the entire sequence can be maintained in a shortened state.

Returning to Fig. 3, the specific configuration of the clock control unit (17) that realizes this operation will be described. Furthermore, it should be understood that the configuration of the clock control unit (17) is not limited to the configuration exemplified below.

The timing signal generation unit (171) includes a plurality of flip-flop circuits (71 to 74) and a NAND circuit (75). Four flip-flop circuits (71 to 74) are illustrated in the drawing, but this number is not limited and can be appropriately changed depending on the length of a predetermined period required for circuit stability.

A plurality of flip-flop circuits (71 to 74) are connected in series. An externally input reset signal (dll_reset_n) is input as an input signal to the most upstream flip-flop circuit (71). Output signals of adjacent upstream flip-flop circuits (71 to 73) are input as input signals to the other flip-flop circuits (72 to 74). A first clock signal (clk000) is inverted and input as a clock signal to each of the plurality of flip-flop circuits (71 to 74). In addition, a reset signal (dll_reset_n) is inverted and input to each of the plurality of flip-flop circuits (71 to 74). An output signal of the most downstream flip-flop circuit (74) is inverted and input to the NAND circuit (75). In addition, the output of the flip-flop circuit (73) adjacent to the upstream side of the flip-flop circuit (74) is input to the NAND circuit (75), and at the same time, the first clock signal (clk000) is input. In the NAND circuit (75), these input signals are subjected to a NAND operation, thereby outputting a timing signal (sel_clk).

The operation of the timing signal generation unit (171) will be described. When the input reset signal (dll_reset_n) changes from a low level to a high level, this change is maintained for a predetermined period of time by a plurality of flip-flop circuits (71 to 74) and input from the flip-flop circuit (74) to the NAND circuit (75). Since the output signal of the flip-flop circuit (73), the output signal of the flip-flop circuit (74), and the first clock signal (clk000) are input to the NAND circuit (75), when the output from the flip-flop circuit (74) becomes a high level, the timing signal (sel_clk) is generated at a high level (asserted) in the NAND circuit (75) and output. In any other case, the timing signal (sel_clk) is generated at a low level in the NAND circuit (75) and output. By this, after the reset operation, the delay operation starts and only at a predetermined timing, the timing signal (sel_clk) is output at a high level. That is, the timing signal (sel_clk) is generated as a one-shot signal.

The selection signal generation unit (172) is composed of a flip-flop circuit (76). To the flip-flop circuit (76), an inverted phase signal (up/down) is input as an input signal, and a timing signal (sel_clk) is input as a clock signal. In addition, an inverted reset signal (dll_reset_n) is input. Then, a selection signal (sel180) is output from the flip-flop circuit (76) as an output signal. As described above, the timing signal (sel_clk) is a one-shot signal that changes from a level to a high level only after a predetermined period of time has elapsed after the start of the delay operation, so the selection signal generation unit (172) can determine whether the delay is 180 degrees or more only at a predetermined timing after the start of the delay operation.

The operation of the selection signal generation unit (172) is described. In the selection signal generation unit (172), when the timing signal (sel_clk) is input from a low level to a high level at a rising edge, the reset signal (dll_reset_n) is at a high level and the phase signal (up/down) is at a high level (up), the selection signal (sel180) maintains a low level. In this case, since the phase difference of the input signal to the delay control unit (10) is less than 180 degrees, the selection signal (sel180) is output at a low level indicating that the second clock signal (clk180) is not selected. On the other hand, when the timing signal (sel_clk) is inputted at a rising edge from a low level to a high level, the reset signal (dll_reset_n) is at a high level and the phase signal (up/down) is at a low level (down), the selection signal (sel180) is outputted at a high level indicating that the second clock signal (clk180) is selected.

The internal clock selection unit (173) is composed of a multiplexer (77) and is configured to select one of the input first clock signal (clk000) and the second clock signal (clk180) according to a selection signal (sel180) and output it as an input clock signal (in_clk). That is, when the selection signal (sel180) is at a high level indicating that the second clock signal (clk180) is selected, the second clock signal (clk180) is output from the multiplexer (77), and in other cases, the first clock signal (clk000) is output from the multiplexer (77).

In this way, the clock control unit (17) can, with a simple configuration, set either the first clock signal (clk000) or the second clock signal (clk180) as an input clock signal (in_clk) according to the phase signal (up/down) and input it to the delay circuit (14). By this, the DLL circuit (1) of the present embodiment can suppress the prolongation of the delay operation.

Next, the operation of the DLL circuit (1) of the present embodiment including the clock control unit (17) is explained using the flow charts shown in FIGS. 7 and 8.

Fig. 7 shows a case where the phase difference between the feedback signal (fb_clk) and the input clock signal (in_clk) is 180 degrees or more. Initially, this sequence starts and the DLL reset state is established first. In this state, the input clock signal (in_clk) is the first clock signal (clk000), and the phase difference between the feedback signal (fb_clk) and the input clock signal (in_clk) is 180 degrees or more. Then, the DLL reset state ends at time t31, and the reset signal (dll_reset_n) changes from a low level to a high level. As a state of the DLL circuit, a delay operation starts at the same time as the DLL reset state ends at time t31.

And, at time t32, in the timing signal generation unit (171), after a predetermined period of time has elapsed, the timing signal (sel_clk) changes from a low level to a high level. At this time t32, the reset signal (dll_reset_n) is at a high level, and the phase signal (up/down) is at a low level (down). At the rising edge of the timing signal (sel_clk), the reset signal (dll_reset_n) at a high level and the phase signal (up/down) at a low level are input to the selection signal generation unit (172), so that the selection signal (sel180) changes from a low level to a high level and is output. By this, the input clock signal (in_clk) output from the clock control unit (17) becomes the second clock signal (clk180), so the input clock signal (in_clk) is maintained at a low level from time t32 to time t33, similar to the second clock signal (clk180).

The input clock signal (in_clk) changes from a low level to a high level at time t33 in accordance with the rise of the second clock signal (clk180). In addition, since the second clock signal (clk180) is selected as the input clock signal (in_clk), the feedback signal (fb_clk) is also delayed by 180 degrees, and is maintained at a low level from time t32 to time t34, and changes from a low level to a high level at time t34. As the feedback signal (fb_clk) changes from a low level to a high level in this way, the phase signal (up/down) changes from a low level to a high level at time t35. That is, the phase difference between the feedback signal (fb_clk) and the input clock signal (in_clk) becomes small (less than 180 degrees).

In the delay circuit (14), based on this phase signal (up/down), the input clock signal (in_clk), which is the second clock signal (clk180), is delayed, and at time t36, it is determined that the desired phase difference has been reached, and the delay operation is terminated.

Next, the operation of the DLL circuit (1) when the phase difference between the feedback signal (fb_clk) and the input clock signal (in_clk) is less than 180 degrees is explained using the flow chart shown in Fig. 8.

Initially, this sequence control starts, and the state of the DLL circuit (1) first becomes the DLL reset state. Then, the reset operation ends at time t41, and the reset signal (dll_reset_n) changes from a low level to a high level. At the same time that the reset operation ends at time t41, a delay operation starts in the DLL circuit (1).

And, at time t42, in the timing signal generation unit (171), the timing signal (sel_clk) changes from a low level to a high level. At this time t42, the reset signal (dll_reset_n) is at a high level, and the phase signal (up/down) is up (high level). At the rising edge of the timing signal (sel_clk), in the selection signal generation unit (172), the reset signal (dll_reset_n) at a high level and the phase signal (up/down) at a high level are input, so that the selection signal (sel180) is maintained at a low level. Thereby, since the first clock signal (clk000) is selected as the input clock signal (in_clk), the input clock signal (in_clk) is maintained at a high level from time t42 to time t43, similarly to the first clock signal (clk000). Additionally, since the input clock signal (in_clk) becomes the clock signal (clk000), the feedback signal (fb_clk) is not delayed by 180 degrees.

In the delay circuit (14), based on this phase signal (up/down), the input clock signal (in_clk), which is the first clock signal (clk000), is delayed, and at time t44, it is determined that the desired phase difference has been reached, and the delay operation is terminated.

In this way, the clock control unit (17) can, with a simple configuration, set either the first clock signal (clk000) or the second clock signal (clk180) as an input clock signal (in_clk) according to the phase signal (up/down), and input it to the delay circuit (14) (delay control unit (10)). By this, it is possible to suppress the prolongation of the delay operation in the DLL circuit (1).

Hereinafter, a modified example of the present invention will be described.

The configuration of the DLL circuit (1) in the above-described embodiment is an example, and may be appropriately changed, and various other configurations may be adopted. For example, as shown in Fig. 9, an input buffer (11) may be configured. In this case, the input buffer (11) includes an amplifier (112) and an inverter (113). A clock signal (CLKT) and a clock signal (CLKC) that are complementary to each other as external clock signals are input to the amplifier (112). The input complementary clock signals (CLKT) and the clock signal (CLKC) are amplified in the amplifier (112), and the amplifier (112) outputs only a first clock signal (clk000) that is in the same phase as the clock signal (CLKT). In addition, this first clock signal (clk000) is input to the inverter (113), and a second clock signal (clk180) that inverts the first clock signal (clk000) is generated. In the above-described embodiment, since both signals are output from the amplifier (111), the first clock signal (clk000) and the second clock signal (clk180) have the same number of cmosgate stages, but in the embodiment shown in Fig. 9, the first clock signal (clk000) and the second clock signal (clk180) have different numbers of cmosgate stages by one stage of the inverter (113).

Also, in the above-described embodiment, the control was changed depending on whether the phase difference between the input clock signal (in_clk) and the delay signal (dll_clk) (feedback signal (fb_clk)) was 180 degrees or more, but this phase difference can be set to a desired value. Also, the second clock signal (clk180) was obtained by delaying the phase of the input clock signal by 180 degrees with respect to the first clock signal (clk000), but this phase difference can also be set to a desired value. On the other hand, by making them all 180 degrees as in the above-described embodiment, the control is simple, and the configuration of the entire circuit can also be made simple. Also, although the first clock signal (clk000) and the second clock signal (clk180) were generated in advance and configured so that they can be selected, this is not limited thereto. For example, it is possible to generate a clock signal with three or more phases different from each other in advance, or to configure it to generate multiple clock signals with different phases during a delay operation.

In addition, in this embodiment, in order to simplify the configuration, the phase detection unit (12) that the delay control unit (10) normally has is used to detect the phase difference between the input clock signal (in_clk) and the delay signal (dll_clk) (feedback signal (fb_clk)), but this is not limited to this, and a separate phase detection unit may be installed.

In addition, in the above-described embodiment, the semiconductor memory device including the control circuit is described as an example of a DRAM, but the present invention is not limited to this case. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a flash memory, or another semiconductor memory device.

The embodiments and variations described above are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Therefore, each element disclosed in the embodiments and variations is intended to encompass all design modifications and equivalents within the technical scope of the present invention.

1… DLL circuit
10… Delay control unit
11… Input buffer
12… phase detection unit
13… DLL control unit
14… Delay circuit
15… Replica Department
16… Output buffer
17… Clock control unit
fb_clk… feedback signal
in_clk… input clock signal
clk000… first clock signal
clk180… Second clock signal
up/down… phase signal

Claims (18)

A control circuit including a delay control unit that delays the input clock signal based on the phase difference between the input clock signal and the output clock signal to generate the output clock signal,
Further including a clock control unit,
The above clock control unit, when the phase difference is greater than or equal to the first predetermined amount,
As the input clock signal, a clock signal whose phase of the input clock signal is delayed by a second predetermined amount is input to the delay control unit as the input clock,
In the clock control unit, a first input clock signal and a second input clock signal that delays the first input clock signal by a second predetermined amount are input,
The clock control unit selects the second input clock signal as the input clock signal when the phase difference is greater than or equal to the first predetermined amount,
The above clock control unit includes a timing signal generation unit (171), a selection signal generation unit, and an internal clock selection unit.
The timing signal generation unit generates a timing signal (sel_clk) indicating the timing of the passage of a predetermined period of time after the start of a delay operation, and the timing signal is input to the selection signal generation unit, a control circuit. delete In the first paragraph,
A control circuit characterized in that the clock control unit determines, at a predetermined timing after the start of the delay operation, whether the phase difference is greater than or equal to the first predetermined amount. In the first paragraph,
The above delay control unit includes a phase detection unit that detects the phase difference between the input clock signal and the output clock signal,
A control circuit characterized in that the phase difference detected by the phase detection unit is input to the clock control unit. In the first paragraph,
The selection signal generated in the above selection signal generation unit is input to the internal clock selection unit,
The above selection signal generating unit generates a selection signal indicating whether the phase difference is greater than or equal to a predetermined value,
A control circuit characterized in that the internal clock selection unit is configured to select one of the first input clock signal and the second input clock signal based on the selection signal. In the first paragraph,
The above first predetermined amount is 180 degrees,
A control circuit characterized in that the second predetermined amount is 180 degrees. In the first paragraph,
Including an input buffer into which an external clock signal is input,
A control circuit characterized in that, in the input buffer, the first input clock signal is generated from the external clock signal, and the second input clock signal is generated by inverting the external clock signal. In the first paragraph,
Including an input buffer into which an external clock signal is input,
A control circuit characterized in that, in the input buffer, the first input clock signal is generated from the external clock signal, and at the same time, the second input clock signal is generated from a compensation clock signal of the external clock signal. In the first paragraph,
A control circuit characterized in that it performs a delay operation based on the phase difference between the rising edge of the second input clock signal and the rising edge of the output clock signal. In the first paragraph,
The above delay control unit includes a delay circuit and a DLL control unit,
A control circuit characterized in that the above delay circuit generates the output clock signal based on the delay amount set by the DLL control unit. In Article 10,
The above delay control unit includes a phase detection unit connected to the DLL control unit,
A control circuit characterized in that the phase detection unit receives a feedback signal and a reference clock signal and generates a phase signal indicating a phase advance or delay of the feedback signal with respect to the reference clock signal. In Article 11,
The above delay control unit includes a replica unit connected to the delay circuit and the phase detection unit,
A control circuit characterized in that the replica unit receives the output clock signal generated by the delay circuit and outputs the feedback signal. A semiconductor memory device characterized by including the control circuit described in claim 1. In Article 13,
A semiconductor memory device characterized in that the above semiconductor memory device is a dynamic random access memory. In the first paragraph,
The above timing signal generation unit (171) includes a plurality of flip-flop circuits and a NAND circuit (75),
The above plurality of flip-flop circuits are connected in series,
A reset signal (dll_reset_n) input from the outside is input as an input signal to the flip-flop circuit on the most upstream side among the plurality of flip-flop circuits,
A control circuit in which the output signals of the flip-flop circuits on the adjacent upstream side are configured as input signals to each other flip-flop circuit. In Article 15,
After the first clock signal (clk000) is inverted, the first clock signal is input as the clock signal to the plurality of flip-flop circuits,
After the reset signal is inverted, the reset signal is input to the plurality of flip-flop circuits,
A control circuit in which an output signal of a flip-flop circuit on the most downstream side among the plurality of flip-flop circuits is inverted and then input to the NAND circuit, an output of a flip-flop circuit adjacent to the flip-flop circuit on the most downstream side is input to the NAND circuit, and the first clock signal is input to the NAND circuit. In Article 16,
A control circuit in which, when the input reset signal (dll_reset_n) changes from a low level to a high level, the change is maintained for a predetermined period of time through the plurality of flip-flop circuits and input from the most downstream flip-flop circuit to the NAND circuit. In Article 17,
The NAND circuit receives an output signal of a flip-flop circuit adjacent to the most downstream flip-flop circuit, an output signal of the most downstream flip-flop circuit, and the first clock signal, and when the output of the most downstream flip-flop circuit is at a high level, the NAND circuit generates and outputs a high-level timing signal, such that the timing signal is at a high level only for a predetermined time from the start of the delay operation after the reset operation. A control circuit.