TWI891177B - Power supply device with high output stability - Google Patents

Abstract

A power supply device with high output stability includes a bridge rectifier, a voltage divider circuit a sense resistor, a first inductor, a power switch element, an output stage circuit, an MCU (Microcontroller Unit), a selection circuit, a first buck converter, and a second buck converter. The voltage divider circuit generates a first voltage difference. A second voltage difference is formed across the sense resistor. The MCU generates a first control voltage and a second control voltage according to the first voltage difference and the second voltage difference. The selection circuit selects the first buck converter or the second buck converter as a work buck converter according to the first control voltage and the second control voltage.

Description

High output stability power supply

The present invention relates to a power supply, and more particularly to a power supply with high output stability.

Power supplies are essential components in laptop computers. However, if the power supply's output stability is insufficient, it can easily lead to a decline in the overall operating performance of the laptop. Therefore, a new solution is necessary to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention provides a power supply with high output stability, comprising: a bridge rectifier that generates a rectified potential based on a first input potential and a second input potential; a voltage divider circuit that generates a first potential difference based on the rectified potential; a sensing resistor; a first inductor that receives the rectified potential via the sensing resistor; a power switch that selectively couples the first inductor to a ground potential based on a clock potential; and an output stage circuit that is coupled to the first inductor and generates an intermediate voltage. A microcontroller generates the clock potential and obtains a second potential difference across the sense resistor, wherein the microcontroller further generates a first control potential and a second control potential based on the first potential difference and the second potential difference; a first buck converter; a second buck converter; and a selection circuit selects the first buck converter or the second buck converter as an operating buck converter based on the first control potential and the second control potential, wherein the operating buck converter generates an output potential based on the intermediate potential.

In some embodiments, the microcontroller further searches for a first peak of the first potential difference and a second peak of the second potential difference, and then calculates a phase difference between the first peak and the second peak.

In some embodiments, if the phase difference is greater than or equal to 18 degrees, the selection circuit selects the first buck converter as the working buck converter, and if the phase difference is less than 18 degrees, the selection circuit selects the second buck converter as the working buck converter.

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, The cathode of the second diode is coupled to the first node; a third diode has an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode has an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node.

In some embodiments, the voltage divider circuit includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node to receive the rectified potential, and the second end of the first resistor is coupled to a second node; and a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second node, and the second end of the second resistor is coupled to the ground potential. wherein the first potential difference is across the second resistor; wherein the sensing resistor has a first terminal and a second terminal, the first terminal of the sensing resistor is coupled to the first node to receive the rectified potential, and the second terminal of the sensing resistor is coupled to a third node; wherein the first inductor has a first terminal and a second terminal, the first terminal of the first inductor is coupled to the third node, and the second terminal of the first inductor is coupled to a fourth node.

In some embodiments, the power switch includes a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is configured to receive the clock potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the fourth node.

In some embodiments, the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fourth node, and the cathode of the fifth diode is coupled to a fifth node to output the intermediate potential; and a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the fifth node, and the second terminal of the first capacitor is coupled to the ground potential.

In some embodiments, the selection circuit includes: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the first control potential, the first terminal of the second transistor is coupled to a sixth node, and the second terminal of the second transistor is coupled to the fifth node to receive the intermediate potential; and a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the second control potential, the first terminal of the third transistor is coupled to a seventh node, and the second terminal of the third transistor is coupled to the fifth node to receive the intermediate potential.

In some embodiments, the first buck converter includes: a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the clock potential, the first terminal of the fourth transistor is coupled to an eighth node, and the second terminal of the fourth transistor is coupled to the sixth node; a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to a common node. The cathode of the sixth diode is coupled to the eighth node; a second inductor has a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the eighth node, and the second terminal of the second inductor is coupled to an output node; and a second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node.

In some embodiments, the second buck converter includes: a pulse width modulation integrated circuit that generates a first drive potential and a second drive potential; a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is used to receive the first drive potential, the first terminal of the fifth transistor is coupled to a ninth node, and the second terminal of the fifth transistor is coupled to the seventh node; a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is used to receive the second drive potential, the first terminal of the sixth transistor is coupled to The ground potential, and the second end of the sixth transistor is coupled to the ninth node; a transformer, including a main coil, a first secondary coil, and a second secondary coil, wherein the transformer further has a built-in leakage inductor and an excitation inductor; a resonant capacitor, wherein the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the ninth node, the second end of the leakage inductor is coupled to a tenth node, the main coil has a first end and a second end, the first end of the main coil is coupled to the tenth node, the second end of the main coil is coupled to an eleventh node, and the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the tenth node, the second end of the excitation inductor is coupled to the eleventh node, the resonant capacitor has a first end and a second end, the first end of the resonant capacitor is coupled to the eleventh node, the second end of the resonant capacitor is coupled to the ground potential, the first secondary coil has a first end and a second end, the first end of the first secondary coil is coupled to a twelfth node, the second end of the first secondary coil is coupled to the common node, the second secondary coil has a first end and a second end, the first end of the second secondary coil is coupled to the common node, The second end of the second secondary coil is coupled to a thirteenth node; a seventh diode has an anode and a cathode, wherein the anode of the seventh diode is coupled to the twelfth node, and the cathode of the seventh diode is coupled to the output node; an eighth diode has an anode and a cathode, wherein the anode of the eighth diode is coupled to the thirteenth node, and the cathode of the eighth diode is coupled to the output node; and a third capacitor has a first end and a second end, wherein the first end of the third capacitor is coupled to the output node, and the second end of the third capacitor is coupled to the common node.

100,200: Power supply

110,210: Bridge rectifier

120,220: Voltage divider circuit

130,230: Power switch

140,240: Output stage circuit

150,250: Microcontroller

160,260: Select circuit

170,270: First buck converter

180,280: Second buck converter

282: Pulse Width Modulation Integrated Circuit

284: Transformer

285: Main coil

286: First coil

287: Second coil

C1: First capacitor

C2: Second capacitor

C3: The third capacitor

CR: Resonant Capacitor

D1: First diode

D2: Second diode

D3: The third diode

D4: Fourth Diode

D5: Fifth Diode

D6: Sixth Diode

D7: Seventh Diode

D8: Eighth Diode

L1: First inductor

L2: Second inductor

LM: Magnetizing Inductor

LR: Leakage Inductor

M1: First transistor

M2: Second transistor

M3: The third transistor

M4: Fourth transistor

M5: Fifth transistor

M6: Sixth transistor

N1: First Node

N2: Second Node

N3: Third Node

N4: Fourth Node

N5: Fifth Node

N6: Node 6

N7: Seventh Node

N8: Node 8

N9: Ninth Node

N10: Node 10

N11: Node 11

N12: Node 12

N13: Node 13

NCM: Common Node

NIN1: First input node

NIN2: Second input node

NOUT: output node

P1: First peak

P2: Second peak

R1: First resistor

R2: Second resistor

RS: Sense resistor

T1: First time point

T2: Second time point

TA: Cycle duration

VA: Pulse potential

VC1: First control voltage

VC2: First control voltage

VD1: First drive potential

VD2: Second drive potential

VE: intermediate potential

VIN1: First input potential

VIN2: Second input potential

VOUT: output voltage

VR: Rectification potential

VSS: Ground potential

△T: time difference

△V1: First potential difference

△V2: Second potential difference

△θ: Phase difference

Figure 1 is a schematic diagram of a power supply according to one embodiment of the present invention.

Figure 2 shows a circuit diagram of a power supply according to one embodiment of the present invention.

Figure 3 shows a signal waveform diagram of a power supply according to an embodiment of the present invention.

To make the purpose, features, and advantages of the present invention more clearly understood, specific embodiments of the present invention are given below, along with accompanying drawings for detailed description.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in name as a way to distinguish components, but rather use differences in the functions of the components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open-ended terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

FIG1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, power supply 100 can be used in a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG1 , power supply 100 includes a bridge rectifier 110, a voltage divider circuit 120, a sensing resistor RS, a first inductor L1, a power switch 130, an output stage circuit 140, a microcontroller unit (MCU) 150, a selection circuit 160, a first buck converter 170, and a second buck converter 180. It should be noted that, although not shown in FIG. 1 , the power supply 100 may further include other components, such as a voltage regulator and/or a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR based on a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage having any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50 Hz or 60 Hz, and the root mean square (RMS) value of the AC voltage can be approximately between 90 V and 264 V, but is not limited thereto. The voltage divider circuit 120 can generate a first potential difference ΔV1 based on the rectified potential VR. The first inductor L1 can receive the rectified potential VR via the sense resistor RS. The power switch 130 can selectively couple the first inductor L1 to a ground potential VSS (e.g., 0 V) based on a clock potential VA. For example, if the clock potential VA is at a high logic level (i.e., a logic "1"), the power switch 130 can couple the first inductor L1 to the ground potential VSS (i.e., the power switch 130 can be similar to a short circuit path). Conversely, if the clock potential VA is at a low logic level (i.e., a logic "0"), the power switch 130 will not couple the first inductor L1 to the ground potential VSS (i.e., the power switch 130 can be similar to an open circuit path). The output stage circuit 140 is coupled to the first inductor L1 and can generate an intermediate potential VE. Microcontroller 150 can generate a clock voltage VA and obtain a second potential difference ΔV2 across sense resistor RS. Microcontroller 150 can further generate a first control voltage VC1 and a second control voltage VC2 based on the first potential difference ΔV1 and the second potential difference ΔV2. Selection circuit 160 can select either first buck converter 170 or second buck converter 180 as the active buck converter based on the first control voltage VC1 and the second control voltage VC2. The active buck converter can generate an output voltage VOUT based on the intermediate voltage VE. For example, output voltage VOUT can be a DC voltage with a voltage level between 18V and 22V, but is not limited to this. It should be noted that the first buck converter 170 and the second buck converter 180 belong to different types of buck converters. According to actual measurement results, with this selective buck design, the power supply 100 of the present invention can significantly improve its output stability.

The following embodiments will introduce the detailed structure and operation of the power supply 100. It must be understood that these figures and descriptions are for illustrative purposes only and are not intended to limit the scope of the present invention.

FIG2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG2 , the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes: a bridge rectifier 210, a voltage divider circuit 220, a sense resistor RS, a first inductor L1, a power switch 230, an output stage circuit 240, a microcontroller 250, a selection circuit 260, a first buck converter 270, and a second buck converter 280. The first input node NIN1 and the second input node NIN2 of the power supply 200 can respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power source (not shown). The output node NOUT of the power supply 200 can be used to output an output potential VOUT to an external device, such as a laptop computer (not shown).

Bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. First diode D1 has an anode and a cathode. The anode of first diode D1 is coupled to first input node NIN1, while the cathode of first diode D1 is coupled to first node N1 to output a rectified potential VR. Second diode D2 has an anode and a cathode. The anode of second diode D2 is coupled to second input node NIN2, while the cathode of second diode D2 is coupled to first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The voltage divider circuit 220 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first terminal and a second terminal. The first terminal of the first resistor R1 is coupled to the first node N1 to receive the rectified potential VR, while the second terminal of the first resistor R1 is coupled to the second node N2. The second resistor R2 has a first terminal and a second terminal. The first terminal of the second resistor R2 is coupled to the second node N2, while the second terminal of the second resistor R2 is coupled to the ground potential VSS. Furthermore, a first potential difference ΔV1 may be formed across the second resistor R2. That is, the first potential difference ΔV1 may be equal to the potential difference between the first terminal and the second terminal of the second resistor R2.

The sensing resistor RS has a first terminal and a second terminal. The first terminal of the sensing resistor RS is coupled to the first node N1 to receive the rectified potential VR, and the second terminal of the sensing resistor RS is coupled to a third node N3. Furthermore, a second potential difference ΔV2 may be formed across the sensing resistor RS. That is, the second potential difference ΔV2 may be equal to the potential difference between the first terminal and the second terminal of the sensing resistor RS. The resistance of the sensing resistor RS may be significantly smaller than the resistance of each of the first resistor R1 and the second resistor R2. For example, the resistance of the sensing resistor RS may be less than 20Ω, while the resistance of each of the first resistor R1 and the second resistor R2 may be greater than or equal to 1MΩ, but this is not limited to such resistances.

The first inductor L1 has a first end and a second end, wherein the first end of the first inductor L1 is coupled to the third node N3, and the second end of the first inductor L1 is coupled to a fourth node N4.

The power switch 230 includes a first transistor M1. For example, the first transistor M1 can be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the first transistor M1 is configured to receive a clock potential VA. The first terminal of the first transistor M1 is coupled to the ground potential VSS. The second terminal of the first transistor M1 is coupled to the fourth node N4.

The output stage circuit 240 includes a fifth diode D5 and a first capacitor C1. The fifth diode D5 has an anode and a cathode. The anode of the fifth diode D5 is coupled to the fourth node N4, and the cathode of the fifth diode D5 is coupled to the fifth node N5 to output an intermediate potential VE. The first capacitor C1 has a first terminal and a second terminal. The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

Microcontroller 250 can generate a clock potential VA. Microcontroller 250 is coupled to voltage divider circuit 220 and sensing resistor RS to obtain information related to the first potential difference ΔV1 and the second potential difference ΔV2. Furthermore, microcontroller 250 can generate a first control potential VC1 and a second control potential VC2 based on the first potential difference ΔV1 and the second potential difference ΔV2.

The selection circuit 260 includes a second transistor M2 and a third transistor M3. For example, the second transistor M2 and the third transistor M3 can each be an N-type metal oxide semiconductor field effect transistor. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the second transistor M2 is configured to receive a first control potential VC1. The first terminal of the second transistor M2 is coupled to a sixth node N6. The second terminal of the second transistor M2 is coupled to a fifth node N5 to receive an intermediate potential VE. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the third transistor M3 is used to receive the second control potential VC2. The first terminal of the third transistor M3 is coupled to a seventh node N7. The second terminal of the third transistor M3 is coupled to the fifth node N5 to receive the intermediate potential VE.

The first buck converter 270 includes a fourth transistor M4, a sixth diode D6, a second inductor L2, and a second capacitor C2. For example, the fourth transistor M4 can be an N-type metal oxide semiconductor field effect transistor. The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fourth transistor M4 is configured to receive the clock potential VA. The first terminal of the fourth transistor M4 is coupled to an eighth node N8, and the second terminal of the fourth transistor M4 is coupled to the sixth node N6. The sixth diode D6 has an anode and a cathode. The anode of the sixth diode D6 is coupled to a common node NCM, and the cathode of the sixth diode D6 is coupled to the eighth node N8. The second inductor L2 has a first terminal and a second terminal. The first terminal of the second inductor L2 is coupled to the eighth node N8, and the second terminal of the second inductor L2 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal. The first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the common node NCM. For example, the common node NCM can provide a common potential, which can be considered another ground potential and can be the same as or different from the aforementioned ground potential VSS.

The second buck converter 280 includes a pulse width modulation integrated circuit (PWM IC) 282, a transformer 284, a fifth transistor M5, a sixth transistor M6, a seventh diode D7, an eighth diode D8, a resonant capacitor CR, and a third capacitor C3. For example, the fifth transistor M5 and the sixth transistor M6 can each be an N-type metal oxide semiconductor field effect transistor.

The pulse width modulation integrated circuit 282 can generate a first drive potential VD1 and a second drive potential VD2. For example, the first drive potential VD1 and the second drive potential VD2 can have substantially complementary logical levels. The fifth transistor M5 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fifth transistor M5 is configured to receive the first drive potential VD1. The first terminal of the fifth transistor M5 is coupled to a ninth node N9, and the second terminal of the fifth transistor M5 is coupled to the seventh node N7. The sixth transistor M6 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the sixth transistor M6 is used to receive the second drive potential VD2. The first terminal of the sixth transistor M6 is coupled to the ground potential VSS, and the second terminal of the sixth transistor M6 is coupled to the ninth node N9.

Transformer 284 includes a main coil 285, a first secondary coil 286, and a second secondary coil 287. Transformer 284 further includes a built-in leakage inductor LR and a magnetizing inductor LM. Leakage inductor LR and magnetizing inductor LM can be inherent components that are included with the manufacture of transformer 284 and are not external, independent components. Leakage inductor LR, main coil 285, and magnetizing inductor LM can all be located on the same side of transformer 284 (e.g., the primary side), while first secondary coil 286 and second secondary coil 287 can both be located on the opposite side of transformer 284 (e.g., the secondary side, which can be isolated from the primary side). The leakage inductor LR has a first terminal and a second terminal, wherein the first terminal of the leakage inductor LR is coupled to the ninth node N9, and the second terminal of the leakage inductor LR is coupled to the tenth node N10. The main coil 285 has a first terminal and a second terminal, wherein the first terminal of the main coil 285 is coupled to the tenth node N10, and the second terminal of the main coil 285 is coupled to the eleventh node N11. The magnetizing inductor LM has a first terminal and a second terminal, wherein the first terminal of the magnetizing inductor LM is coupled to the tenth node N10, and the second terminal of the magnetizing inductor LM is coupled to the eleventh node N11. The resonant capacitor CR has a first terminal and a second terminal, wherein the first terminal of the resonant capacitor CR is coupled to the eleventh node N11, and the second terminal of the resonant capacitor CR is coupled to the ground potential VSS. For example, the leakage inductor LR, the magnetizing inductor LM, and the resonant capacitor CR can collectively form a resonant tank of the second buck converter 280. The first sub-coil 286 has a first end and a second end. The first end of the first sub-coil 286 is coupled to a twelfth node N12, and the second end of the first sub-coil 286 is coupled to the common node NCM. The second sub-coil 287 has a first end and a second end. The first end of the second sub-coil 287 is coupled to the common node NCM, and the second end of the second sub-coil 287 is coupled to a thirteenth node N13.

The seventh diode D7 has an anode and a cathode, wherein the anode of the seventh diode D7 is coupled to the twelfth node N12, and the cathode of the seventh diode D7 is coupled to the output node NOUT. The eighth diode D8 has an anode and a cathode, wherein the anode of the eighth diode D8 is coupled to the thirteenth node N13, and the cathode of the eighth diode D8 is coupled to the output node NOUT. The third capacitor C3 has a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the output node NOUT, and the second terminal of the third capacitor C3 is coupled to the common node NCM.

Figure 3 shows a signal waveform diagram of a power supply 200 according to an embodiment of the present invention, where the horizontal axis represents time (s) and the vertical axis represents potential level (V). The microcontroller 250 may execute a sampling process at a predetermined frequency for the first potential difference ΔV1 and the second potential difference ΔV2. For example, the predetermined frequency may be approximately 60 Hz, but is not limited thereto. Please refer to Figures 2 and 3 together. In some embodiments, the operating principle of the power supply 200 may be as described below.

It should be noted that both the first potential difference ΔV1 and the second potential difference ΔV2 are periodic signals, and each cycle has a period duration TA. Figure 3 only shows the relevant periods of the first potential difference ΔV1 and the second potential difference ΔV2. Generally speaking, the microcontroller 250 can first search for a first peak value P1 of the first potential difference ΔV1 and a second peak value P2 of the second potential difference ΔV2, and then calculate a phase difference Δθ between the first peak value P1 and the second peak value P2. For example, the first peak value P1 of the first potential difference ΔV1 may occur at a first time point T1, while the second peak value P2 of the second potential difference ΔV2 may occur at a second time point T2. In addition, there may be a time difference ΔT between the second time point T2 and the first time point T1. In some embodiments, the aforementioned phase difference Δθ can be calculated according to the following equation (1): Wherein, “Δθ” represents the phase difference Δθ, “ΔT” represents the time difference ΔT between the second time point T2 and the first time point T1, and “TA” represents the cycle time length TA.

In detail, the first potential difference ΔV1 can be used to indicate information related to an input voltage of the power supply 200, and the second potential difference ΔV2 can be used to indicate information related to an input current of the power supply 200. Therefore, the aforementioned phase difference Δθ can also be used as the phase difference between the input voltage and the input current of the power supply 200. In some embodiments, a power factor of the power supply 200 can be calculated according to the following equation (2): PF=cos(Δθ)…………………………………………(2)wherein "PF" represents the power factor of the power supply 200, and "Δθ" represents the phase difference Δθ.

Based on equation (2), if the phase difference Δθ is greater than or equal to 18 degrees, the power factor of the power supply 200 will be relatively low (e.g., less than 0.95); conversely, if the phase difference Δθ is less than 18 degrees, the power factor of the power supply 200 will be relatively high (e.g., greater than 0.95). It must be understood that the phase difference Δθ of 18 degrees here is obtained based on multiple experimental results. It can be used as a better switching benchmark, but it can also be fine-tuned according to different needs.

In some embodiments, if the phase difference Δθ is greater than or equal to 18 degrees, the selection circuit 260 selects the first buck converter 270 as the active buck converter. For example, the microcontroller 250 may output a first control voltage VC1 with a high logic level to enable the second transistor M2 and the first buck converter 270, and may output a second control voltage VC2 with a low logic level to disable the third transistor M3 and the second buck converter 280. At this point, the enabled first buck converter 270 generates an output voltage VOUT based on the intermediate voltage VE.

In other embodiments, if the phase difference Δθ is less than 18 degrees, the selection circuit 260 selects the second buck converter 280 as the active buck converter. For example, the microcontroller 250 may output a first control voltage VC1 having a low logic level to disable the second transistor M2 and the first buck converter 270, and may output a second control voltage VC2 having a high logic level to enable the third transistor M3 and the second buck converter 280. At this point, the enabled second buck converter 280 generates an output voltage VOUT based on the intermediate voltage VE. According to actual measurement results, this selective step-down design helps suppress non-ideal distortion in power supply 200, thereby effectively improving the output stability of power supply 200.

This invention proposes a novel power supply. Based on actual measurement results, the overall output stability of a power supply using the aforementioned design can be significantly improved, making it well-suited for use in a wide variety of devices.

It is important to note that the voltage, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers may adjust these settings according to different needs. The power supply of the present invention is not limited to the conditions illustrated in Figures 1-3. The present invention may include only one or more features of any one or more of the embodiments in Figures 1-3. In other words, not all illustrated features must be implemented simultaneously in the power supply of the present invention. Although the embodiments of the present invention use metal oxide semiconductor field-effect transistors (MOSFETs), the present invention is not limited to this. Those skilled in the art may use other types of transistors, such as junction field-effect transistors (JFETs) or fin field-effect transistors (FFETs), without affecting the effectiveness of the present invention.

In this specification and the scope of the patent application, ordinal numbers, such as "first," "second," "third," etc., do not have a sequential relationship with each other and are only used to distinguish two different components with the same name.

Although the present invention is disclosed above with reference to preferred embodiments, these are not intended to limit the scope of the present invention. Anyone skilled in the art may make modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Power supply 110: Bridge rectifier 120: Voltage divider circuit 130: Power switch 140: Output stage circuit 150: Microcontroller 160: Selection circuit 170: First buck converter 180: Second buck converter L1: First inductor RS: Sense resistor VA: Clock voltage VC1: First control voltage VC2: First control voltage VE: Intermediate voltage VIN1: First input voltage VIN2: Second input voltage VOUT: Output voltage VR: Rectified voltage VSS: Ground voltage ΔV1: First potential difference ΔV2: Second potential difference

Claims (10)

A power supply with high output stability comprises: a bridge rectifier generating a rectified potential based on a first input potential and a second input potential; a voltage divider circuit generating a first potential difference based on the rectified potential; a sensing resistor; a first inductor receiving the rectified potential via the sensing resistor; a power switch selectively coupling the first inductor to a ground potential based on a pulse potential; an output stage circuit coupled to the first inductor and generating an intermediate potential; a microcontroller generating the pulse potential and obtaining a second potential difference across the sensing resistor, wherein the microcontroller further generates a first control potential and a second control potential based on the first potential difference and the second potential difference; A first buck converter; a second buck converter; and a selection circuit for selecting the first buck converter or the second buck converter as an operating buck converter based on the first control potential and the second control potential, wherein the operating buck converter generates an output potential based on the intermediate potential. The power supply as described in claim 1, wherein the microcontroller further searches for a first peak value of the first potential difference and a second peak value of the second potential difference, and then calculates a phase difference between the first peak value and the second peak value. A power supply as described in claim 2, wherein if the phase difference is greater than or equal to 18 degrees, the selection circuit will select the first buck converter as the working buck converter, and if the phase difference is less than 18 degrees, the selection circuit will select the second buck converter as the working buck converter. The power supply of claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node. The power supply of claim 4, wherein the voltage divider circuit comprises: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node to receive the rectified potential, and the second end of the first resistor is coupled to a second node; and a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second node, and the second end of the second resistor is coupled to the ground potential; wherein the first potential difference is across the second resistor; wherein the sensing resistor has a first end and a second end, wherein the first end of the sensing resistor is coupled to the first node to receive the rectified potential, and the second end of the sensing resistor is coupled to a third node; The first inductor has a first end and a second end, the first end of the first inductor is coupled to the third node, and the second end of the first inductor is coupled to a fourth node. The power supply of claim 5, wherein the power switch comprises: A first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is configured to receive the clock potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the fourth node. The power supply of claim 5, wherein the output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fourth node, and the cathode of the fifth diode is coupled to a fifth node to output the intermediate potential; and a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the fifth node, and the second terminal of the first capacitor is coupled to the ground potential. The power supply of claim 7, wherein the selection circuit comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is configured to receive the first control potential, the first terminal of the second transistor is coupled to a sixth node, and the second terminal of the second transistor is coupled to the fifth node to receive the intermediate potential; and a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is configured to receive the second control potential, the first terminal of the third transistor is coupled to a seventh node, and the second terminal of the third transistor is coupled to the fifth node to receive the intermediate potential. The power supply of claim 8, wherein the first buck converter comprises: a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the clock potential, the first terminal of the fourth transistor is coupled to an eighth node, and the second terminal of the fourth transistor is coupled to the sixth node; a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to a common node, and the cathode of the sixth diode is coupled to the eighth node; a second inductor having a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the eighth node, and the second terminal of the second inductor is coupled to an output node; and A second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node. The power supply of claim 9, wherein the second buck converter comprises: a pulse width modulation integrated circuit generating a first drive potential and a second drive potential; a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is configured to receive the first drive potential, the first terminal of the fifth transistor is coupled to a ninth node, and the second terminal of the fifth transistor is coupled to the seventh node; a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is configured to receive the second drive potential, the first terminal of the sixth transistor is coupled to the ground potential, and the second terminal of the sixth transistor is coupled to the ninth node; A transformer comprising a main coil, a first secondary coil, and a second secondary coil, wherein the transformer further includes a leakage inductor and an excitation inductor; a resonant capacitor, wherein the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the ninth node, and the second end of the leakage inductor is coupled to a tenth node; the main coil has a first end and a second end, the first end of the main coil is coupled to the tenth node, and the second end of the main coil is coupled to an eleventh node; the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the tenth node, and the second end of the excitation inductor is coupled to the eleventh node; The resonant capacitor has a first end and a second end, the first end of the resonant capacitor is coupled to the eleventh node, and the second end of the resonant capacitor is coupled to the ground potential. The first secondary coil has a first end and a second end, the first end of the first secondary coil is coupled to a twelfth node, and the second end of the first secondary coil is coupled to the common node. The second secondary coil has a first end and a second end, the first end of the second secondary coil is coupled to the common node, and the second end of the second secondary coil is coupled to a thirteenth node. a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the twelfth node, and the cathode of the seventh diode is coupled to the output node; an eighth diode having an anode and a cathode, wherein the anode of the eighth diode is coupled to the thirteenth node, and the cathode of the eighth diode is coupled to the output node; and a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the output node, and the second terminal of the third capacitor is coupled to the common node.