TWI889040B - Semiconductor device - Google Patents

Abstract

The semiconductor element includes a first-type semiconductor structure, an active structure, a second-type semiconductor structure, an insulating structure, a first metal layer and a second metal layer. The first-type semiconductor structure includes a first region and a second region surrounding the first region, and a top surface in the first region. The active structure is on the second region, and there is no active structure on the first region. The second-type semiconductor structure is on the active structure. The insulating structure covers the first-type semiconductor structure and has a first opening in the first region. The first opening exposes the top surfaces. The first metal layer is in the first opening and in contact with the top surface. The first metal layer has an upper surface away from the top surface, and the upper surface does not contact the insulating structure. The second metal layer is on the first metal layer and has a metal material different from the first metal layer.

Description

Semiconductor components

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having good ohmic contact.

Semiconductor components are widely used, and the development and research of related materials are also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various semiconductor components such as light-emitting chips (e.g., light-emitting diodes or laser diodes), light-absorbing chips (photodetectors or solar cells) or non-light-emitting chips (e.g., power components of switches or rectifiers), which can be used in lighting, medical, display, communication, sensing, power supply systems and other fields. With the development of technology, there are still many technical research and development needs for semiconductor components. Although existing semiconductor components generally meet general needs, they are not satisfactory in all aspects and still need further improvement.

The disclosed embodiment provides a semiconductor element. The semiconductor element includes a first type semiconductor structure, an active structure, a second type semiconductor structure, an insulating structure, a first metal layer and a second metal layer. The first type semiconductor structure includes a first region and a second region surrounding the first region, and a top surface located in the first region. The active structure is located on the second region, and the first region does not have an active structure. The second type semiconductor structure is located on the active structure. The insulating structure covers the first type semiconductor structure and has a first opening located in the first region. The first opening exposes the above-mentioned top surface. The first metal layer is located in the first opening and contacts the top surface. The first metal layer has an upper surface away from the top surface, and the upper surface does not contact the insulating structure. The second metal layer is located on the first metal layer and has a metal material different from that of the first metal layer.

10, 10’, 10”: semiconductor components

100: Base

102: Type I semiconductor structure

104: Active structure

106: Type II semiconductor structure

108: Insulation structure

112: First opening

114: Second opening

116: Groove

118: First metal structure

119: Second metal structure

118a, 119a: first metal layer

118b, 119b: Second metal layer

118c, 119c: The third metal layer

120: Side wall

121: first top surface

122: Second top surface

1081-1082: Side wall

110a1, 110a2, 110a3: first area

110b1, 110b2: Second area

20: Semiconductor components

θ1-θ2: Tilt angle

Wa-Wc: Width

D: Depth

T:Thickness

S1, S2: short side

L1, L2: long side

SC: Short side center line

LC: Long side center line

LL: Left long line

LR: Right long sideline

The present disclosed embodiments are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the sizes of various components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosed embodiments.

Figures 1 to 5 are schematic cross-sectional views of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

FIG. 6 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

FIG. 8 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

FIG. 9 is a schematic top view of a semiconductor device according to another embodiment of the present disclosure.

The following disclosure provides a number of embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the disclosed embodiments. Of course, these are only examples and are not intended to limit the disclosed embodiments. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are directly in contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not directly in contact. In addition, the disclosed embodiments may repeat reference values and/or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not used to indicate the relationship between the different embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "under", "below", "lower", "above", "higher" and the like may be used to facilitate the description of the relationship between one (or more) parts or features and another (or more) parts or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the rotation.

Figures 1 to 5 are schematic diagrams of the process cross-section of the semiconductor element 10 according to an embodiment of the present disclosure. In the various schematic diagrams and exemplary embodiments described below, similar element symbols are used to represent similar elements. The semiconductor element 10 of the present disclosure may include a light-emitting chip (e.g., a light-emitting diode or a laser diode), a light-absorbing chip (e.g., a photodetector or a solar cell), or a non-light-emitting chip (e.g., a power element of a switch or a rectifier). In the embodiment of the present disclosure, the length of the semiconductor element 10 is not greater than 150 microns, preferably in the range of 10 microns to 150 microns, or 10 microns to 60 microns, or 60 microns to 150 microns, and the width is not greater than 100 microns, preferably in the range of 5 microns to 100 microns, or 5 microns to 30 microns, or 30 microns to 75 microns.

Referring to FIG. 1 , a substrate 100 is provided, and a first type semiconductor structure 102, an active structure 104, and a second type semiconductor structure 106 are sequentially formed on the substrate 100. Parts of the first type semiconductor structure 102, the active structure 104, and the second type semiconductor structure 106 can be etched by, for example, a dry etching process, a wet etching process, or a combination thereof, to expose a portion of the first type semiconductor structure 102. As shown in FIG. 1 , the first type semiconductor structure 102 includes a first region and a second region. In this embodiment, in a cross-sectional view, the first type semiconductor structure 102 includes three first regions 110a1, 110a2, and 110a3 and two second regions 110b1 and 110b2. The first region 110a1 is surrounded by the second regions 110b1 and 110b2 and the first region 110a1 is located between the other two first regions 110a2 and 110a3. The active structure 104 and the second type semiconductor structure 106 are located in the second regions 110b1 and 110b2 and are not located in the first regions 110a1, 110a2, and 110a3.

In some embodiments, the substrate 100 may include an insulating material, a semiconductor material, or both. The insulating material may include, for example, the following materials: sapphire, diamond, glass, quartz, or AlN. The semiconductor material may include, for example, the following materials: gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc oxide (ZnO), zinc selenide (ZnSe), gallium nitride (GaN), aluminum nitride (AlN), lithium gallate (LiGaO ₂ ), lithium aluminate (LiAlO ₂ ), germanium (Ge), or silicon (Si). In some embodiments, the substrate 100 is a gallium arsenide substrate. In some embodiments, the thickness of the substrate 100 may be between 50 μm and 1300 μm.

In the disclosed embodiment, the first semiconductor structure 102, the second semiconductor structure 106, and the active structure 104 include a single layer or multiple layers. The first semiconductor structure 102, the second semiconductor structure 106, and the active structure 104 may include III-V semiconductor materials, such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), indium (In), or nitrogen (N). Specifically, in the disclosed embodiment, the III-V semiconductor material may be a binary compound semiconductor (such as GaAs, GaP, or GaN), a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In some embodiments, the thickness of the first type semiconductor structure 102 may be between 1.5 μm and 4 μm. In some embodiments, the thickness of the second type semiconductor structure 106 may be between 0.1 μm and 2 μm. In some embodiments, the thickness of the active structure 104 may be between 0.01 μm and 1.0 μm. The first type semiconductor structure 102 or the second type semiconductor structure 106 may include a Bragg reflector structure (DBR), which is formed by alternately stacking two or more semiconductor materials with different refractive indices.

In some embodiments, the first type semiconductor structure 102, the second type semiconductor structure 106, and the active structure 104 can be formed by the following epitaxial growth processes, such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) or liquid-phase epitaxy (LPE), vapor phase epitaxy (VPE), or a combination thereof.

In some embodiments, the doping of the first type semiconductor structure 102 and the second type semiconductor structure 106 can be performed by in-situ doping during epitaxial growth and/or by implanting the dopant after epitaxial growth. The first type semiconductor structure 102 can include a first dopant to have a first conductivity type, and the second type semiconductor structure 106 can include a second dopant to have a second conductivity type. The first type semiconductor structure 102 and the second type semiconductor structure 106 have different conductivity types, that is, the first conductivity type is different from the second conductivity type. The first conductivity type is, for example, p-type and the second conductivity type is, for example, n-type or the first conductivity type is, for example, n-type and the second conductivity type is, for example, p-type. When the semiconductor element 10 is a light-emitting element, the first type semiconductor structure 102 and the second type semiconductor structure 106 provide holes and electrons or electrons or holes to combine in the active structure 104 to emit light. The first dopant or the second dopant may include silicon, tellurium, carbon, curium, magnesium).

In some embodiments, the semiconductor element 10 may include multiple quantum wells (MQW), single-quantum wells (SQW), homojunctions, and heterojunctions.

When the semiconductor device 10 is a light emitting device and the semiconductor device 10 is in operation, the active structure 104 can emit light. The light emitted by the active structure 104 includes visible light or invisible light. The wavelength of the light emitted by the semiconductor device 10 depends on the material composition of the active structure 104. For example, when the material of the active structure 104 includes the InGaN series, blue light or deep blue light with a peak wavelength of 400 nm to 490 nm or green light with a peak wavelength of 490 nm to 550 nm can be emitted; when the material of the active structure 104 includes the AlGaN series, ultraviolet light with a peak wavelength of 250 nm to 400 nm can be emitted; when the material of the active structure 104 includes the InGaAs series, InGaAsP series, AlGaAs series, or AlGaInAs series, infrared light with a peak wavelength of 700 nm to 1700 nm can be emitted; when the material of the active structure 104 includes the InGaP series or AlGaInP series, red light with a peak wavelength of 610 nm to 700 nm or yellow light with a peak wavelength of 530 nm to 600 nm can be emitted.

Referring to FIG. 2 , the insulating structure 108 covers the upper surface of the structure shown in FIG. 1 . In other words, the insulating structure 108 covers the first semiconductor structure 102, the active structure 104 and the second semiconductor structure 106 . Although the insulating structure 108 is shown as only one layer in the figure, the insulating structure 108 may be more than one film layer. In some embodiments, the insulating structure 108 may be formed of a non-conductive material, including an organic material, such as benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or an inorganic material, such as silicone, glass, or a dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). In one embodiment of the present disclosure, the insulating structure 108 is an insulating reflective structure, which allows the semiconductor device 10 to emit light toward the substrate 100 to reduce light loss on the electrode side, thereby increasing the light output of the semiconductor device 10. In one embodiment, the insulating structure 108 may include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more insulating materials with different refractive indices. For example, a high reflectivity insulating reflective layer may be formed by stacking layers of _SiO2 / _TiO2 , _SiO2 / _Nb2O5 , _etc.

In some embodiments, a deposition process may be used to form the insulating structure 108. The deposition process may be, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or a combination thereof.

Referring to FIG. 3 , the insulating structure 108 located in the first region 110a1 and the second region 110b1 can be etched by an etching process to form a first opening 112 in the first region 110a1 and a second opening 114 in the second region 110b1, respectively, to expose the first type semiconductor structure 102 and the second type semiconductor structure 106. The process used to etch the insulating structure 108 may include a dry etching process, a wet etching process, or a combination thereof. For example, the wet etching process may use an acidic solution or an alkaline solution. The acidic solution may include a solution of hydrofluoric acid, phosphoric acid, nitric acid, acetic acid, or a combination thereof; the alkaline solution may include a solution containing potassium hydroxide, ammonia, hydrogen peroxide, or a combination thereof. For example, the dry etching process may include plasma etching (PE), reactive ion etching (RIE), and inductively coupled plasma reactive ion etching (ICP-RIE). The gases in the above etching reactions may include oxygen-containing gas, fluorine-containing gas, chlorine-containing gas, boron-containing gas, argon-containing gas, and/or a combination thereof.

Next, referring to FIG. 4 , the first type semiconductor structure 102 in the first region 110a1 is further etched through the first opening 112 to form a groove 116, which corresponds to the position of the first opening and overlaps with the first opening. The first type semiconductor structure 102 has a first top surface 121 and a second top surface 122. The first top surface 121 is the bottom of the groove and is located in the first region 110a1. The second top surface 122 is covered by the insulating structure 108. In some embodiments, the first opening 112 exposes the first top surface 121. The first top surface 121 is closer to the substrate 100 than the second top surface 122. In one embodiment, the groove 116 has a depth D that may be greater than 0.001 μm or between 0.001 μm and 0.1 μm.

In some embodiments, as shown in FIG. 3 and FIG. 4, a two-stage dry etching method may be used, wherein the first etching process is used to form the first opening 112 and the second opening 114, and then the second etching process is used to form the groove 116. Specifically, the first etching process may be dry etching, in which a portion of the insulating structure 108 is etched to form the first opening 112 and the second opening 114. The second etching process is also dry etching, in which a portion of the first semiconductor structure 102 and the byproducts generated in the first etching process are etched to form the groove 116. The reaction gas of the first etching process is different from the reaction gas of the second etching process. In other embodiments, the dry etching method may include one or more processes, for example, three or more etching processes.

In one embodiment, a contact layer (not shown) may be formed on the second type semiconductor structure 106, and then, as shown in FIG. 2, an insulating structure 108 covers the contact layer. The contact layer may be transparent and include a metal oxide (e.g., ITO) or a semiconductor material (e.g., GaAs or InGaAs). As shown in FIG. 3, in the step of performing an etching process to etch the insulating structure 108 located in the first region 110a1 and the second region 110b1 to form the first opening 112 and the second opening 114, a portion of the contact layer is etched.

Referring to FIG. 5, the first metal structure 118 is filled into the groove 116 and the first opening 112, and the second metal structure 119 is filled into the second opening 114. FIG. 6 is a schematic top view of the semiconductor element 10, and FIG. 5 is a schematic cross-sectional view of FIG. 6 along the I-I line.

As shown in FIG. 5 , the first metal structure 118 and the second metal structure 119 cover a portion of the top surface of the insulating structure 108. In one embodiment, the first metal structure 118 and the second metal structure 119 may each include a metal material, such as germanium (Ge), benzene (Be), zinc (Zn), chromium (Cr), tungsten (W), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or copper (Cu) or an alloy of the above materials; the first metal structure 118 and the second metal structure 119 may be composed of multiple layers. For example, it may include a Cr/Au layer, a Cr/Cu layer, a Ni/Au layer, a Ti/Au layer, a Ti/Cu layer, a Cr/Pt/Au layer, a Ni/Pt/Au layer, a Ti/Pt/Au layer, a Cr/Ti/Pt/Au layer, an Au/Be layer, a Cr/Ti/Pt/Ni/Au/Sn layer, a Cr/Ti/Pt/Ni/Au/In layer, an Au/GeAu/Au layer, or a Cr/Al/Ti/Ni/Au layer.

As shown in FIG. 5 , the insulating structure 108 has a sidewall 1081 and a sidewall 1082, and the sidewall 1081 is closer to the groove 116 than the sidewall 1082. The first type semiconductor structure 102 has a sidewall 120, the sidewall 120 defines the groove 116 and the sidewall 1081 defines the first opening 112. The sidewall 120 of the first type semiconductor structure 102 and the sidewall 1081 of the insulating structure 108 have a first tilt angle θ1 and a second tilt angle θ2, respectively. In some embodiments, the first tilt angle θ1 is different from the second tilt angle θ2, that is, the first slope of the sidewall 120 is different from the second slope of the sidewall 1081. In some embodiments, the first tilt angle θ1 is greater than the second tilt angle θ2 (the first slope is greater than the second slope), which can help the first metal structure 118 to have good adhesion and coverage with the first type semiconductor structure 102 when the groove 116 is filled. In one embodiment, the first tilt angle θ1 can range from 20 to 80 degrees. If the first tilt angle θ1 is greater than 80 degrees, the coverage of the first metal structure 118 in the groove 116 may be poor, which may cause the semiconductor device 10 to fail to conduct smoothly or fail to have reliability problems during operation; if the first tilt angle θ1 is less than 20 degrees, it may cause poor process yield. On the contrary, for the second tilt angle θ2 (second slope), a smaller second tilt angle θ2 (i.e., a smaller second slope) can make the first metal structure 118 have better adhesion and coverage in the first opening 112. In one embodiment, the second tilt angle θ2 can range from 10 to 70 degrees. If the second tilt angle θ2 is less than 10 degrees, it may cause poor process yield; if the second tilt angle θ2 is greater than 70, the first metal structure 118 has poor coverage with the insulating structure 108 in the first opening 112, so that the semiconductor device 10 may not be turned on smoothly or the device reliability may fail during operation.

In this embodiment, the first metal structure 118 includes a first metal layer 118a, a second metal layer 118b, and a third metal layer 118c in sequence, and their respective average widths Wa<Wb<Wc. The first metal layer 118a fills the groove 116 of the first opening 112, is formed on the first type semiconductor structure 102 and directly contacts the bottom and sidewall of the groove 116 (i.e., directly contacts the sidewall 120 and the first top surface 121 of the first type semiconductor structure 102). The second metal layer 118b is formed on the first metal layer 118a and fills the first opening 112 and directly contacts the sidewall 1081 of the insulating structure 108. The third metal layer 118c is formed on the second metal layer 118b and directly contacts the sidewall 1082 of the insulating structure 108. In some embodiments, the upper surface of the first metal layer 118a is away from the first top surface 121 of the first semiconductor structure 102 and does not contact the insulating structure 108. The provision of the groove 116 can increase the contact area between the first metal layer 118a and the first semiconductor structure 102, thereby reducing the forward voltage (Vf) and improving the device performance. Similarly, the second metal structure 119 can include a first metal layer 119a, a second metal layer 119b, and a third metal layer 119c in sequence, as shown in FIG. 5. In some embodiments, the width of the second metal layer 119b is greater than the width of the first metal layer 119a and the width of the third metal layer 119c is greater than the width of the second metal layer 119b, as shown in FIG. 5.

In some embodiments, the first metal layer 118a/119a, the second metal layer 118b/119b, and the third metal layer 118c/119c each include different metal materials. The first metal layer 118a/119a can be selected from materials suitable for forming ohmic contact with semiconductors, such as Cr, Ti, Ni, BeAu, GeAu. The second metal layer 118b/119b can be selected from metal materials with a reflective function, such as Pt, Al, Ti, Ni, TiW, Au. The third metal layer 118c/119c can be selected from conductive materials suitable for external connections, such as Au, AuSn, Sn, Sn alloy, In, Cu, Ni. In one embodiment, the first metal structure 118 and the second metal structure 119 may each be a three-layer structure composed of Cr/Pt/Au layers. However, it should be understood that in other embodiments, the first metal structure 118 and the second metal structure 119 may each be a single-layer structure, a double-layer structure, or a multi-layer structure of more than three layers, and the material of each film layer may be selected from the materials used for the first metal layer, the second metal layer, and the third metal layer or a combination thereof.

In one embodiment, the second metal structure 119 and the first metal structure 118 may be respectively filled into the first opening 112 and the second opening 114 in the same or different deposition process. In some embodiments, the thickness T of the first metal layer 118a may be between 50Å and 500Å. The thickness of the second metal layer 118b may be between 50Å and 1000Å. The thickness of the third metal layer 118c may be between 0.1μm and 3μm. In some embodiments, the thickness of the first metal layer 119a may be between 50Å and 500Å. The thickness of the second metal layer 119b may be between 50Å and 1000Å. The thickness of the third metal layer 119c may be between 0.1μm and 3μm. In one embodiment, the thickness T of the first metal layer 118a is smaller than that of the second metal layer 118b, and the thickness of the second metal layer 118b is smaller than that of the third metal layer 118c. In detail, the first metal layers 118a and 119a have a thinner thickness, which can increase the light transmittance of the first metal layers 118a and 119a, and the light emitted by the active structure 104 can pass through the first metal layers 118a and 119a and be reflected by the second metal layers 118b and 119b. Since the second metal layers 118b and 119b are used as reflective layers, they need to have a certain thickness and have a thickness greater than that of the first metal layers 118a and 119a. The third metal layers 118c and 119c are used to connect to external circuits. If they are thicker, the bonding yield of the semiconductor element 10 and the external circuit can be increased to improve the optoelectronic properties of the semiconductor element 10.

In some embodiments, the ratio of the thickness T of the first metal layer 118a to the depth D of the groove 116 is between 0.5 and 2. In one embodiment, as shown in FIG. 5, the thickness T of the first metal layer 118a is greater than the depth D of the groove 116. In one embodiment, the ratio of the thickness T of the first metal layer 118a to the depth D of the groove 116 is greater than 1.0 and less than or equal to 2.0. In this embodiment, the first metal layer 118a fills the groove 116, directly contacts the sidewall 120 of the first semiconductor structure 102, and covers a portion of the sidewall 1081 of the insulating structure 108, but does not cover the sidewall 1082.

FIG. 7 is a schematic cross-sectional view of a semiconductor device 10' according to another embodiment of the present disclosure. The main difference between FIG. 7 and FIG. 5 is that the thickness T of the first metal layer 118a is equal to the depth D of the groove 116, and the first metal layer 118a only fills the groove 116, that is, the ratio of the thickness T of the first metal layer 118a to the depth D of the groove 116 is equal to 1.0.

FIG. 8 is a cross-sectional schematic diagram of a semiconductor device 10" according to another embodiment of the present disclosure. The main difference between FIG. 8 and FIG. 5 is that the thickness T of the first metal layer 118a is less than the depth D of the groove 116, and the second metal layer 118b fills the groove 116 and directly contacts the sidewall 120. That is, the ratio of the thickness T of the first metal layer 118a to the depth D of the groove 116 is greater than or equal to 0.5 and less than 1.0.

FIG. 9 is a schematic top view of a semiconductor element 20 according to another embodiment of the present disclosure. The semiconductor element 20 has a similar structure to the semiconductor element 10. In the present embodiment, the shape of the semiconductor element 20 may be square or rectangular and include two short sides S1, S2 and two long sides L1, L2. A short side center line SC passes through the centers of the two short sides S1, S2 to divide the semiconductor element 20 into an upper half and a lower half; a long side center line LC passes through the centers of the two long sides L1, L2 to divide the semiconductor element 20 into a left half and a right half. A left long side line LL is located between the long side center line LC and the short side S1 and divides the left half into two equal parts; a right long side line LR is located between the long side center line LC and the short side S2 and divides the right half into two equal parts. The first opening 112, the groove 116 and the first metal structure 118 are arranged on the left half of the semiconductor element 20, and the second opening 114 and the second metal structure 119 are arranged on the right half of the semiconductor element 20. When the first opening 112, the groove 116 or the first metal structure 118 is circular or square, the center or center thereof is arranged on the short side center line SC or/and the left long side line LL. In other words, the center or center of the first opening 112, the groove 116 or the first metal structure 118 overlaps with the short side center line SC or/and the left long side line LL. When the second opening 114 or the second metal structure 119 is circular or square, its center is set on the short side centerline SC or/and the right long sideline LR. In other words, the center of the second opening 114 or the second metal structure 119 overlaps with the short side centerline SC or/and the right long sideline LR. The center of the first opening 112 or the first metal structure 118 is symmetrical or mirrored with the center of the second opening 114 or the second metal structure 119 relative to the long side centerline LC. In one embodiment, the left long sideline LL, the long side centerline LC and the right long sideline LR divide the long side into four equal parts.

In summary, the disclosed embodiment further etches a portion of the semiconductor layer to form a groove, so that the metal structure directly contacts the sidewall of the semiconductor layer exposed in the groove, which can improve the electrical contact between the metal and the semiconductor, thereby improving the abnormal voltage of the device to maintain the performance of the product. It should be understood that not all advantages are necessarily discussed here, and not all embodiments need to have specific advantages, and other embodiments can provide different advantages.

The above summarizes the components of several embodiments so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the viewpoints of the disclosed embodiments. Those with ordinary knowledge in the art to which the present invention belongs should understand that they can design or modify other processes and structures based on the disclosed embodiments to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

104: active structure 106: second type semiconductor structure 110a1, 110a2, 110a3: first region 110b1, 110b2: second region 112 first opening 116: groove 118: first metal structure 119: second metal structure 118a, 119a: first metal layer 118b, 119b: second metal layer 118c, 119c: third metal layer 120: side wall 121: first top surface 122: second top surface 1081, 1082: side wall θ1-θ2: tilt angle Wa-Wc: width D: depth T: thickness

Claims (10)

A semiconductor element comprises: A first-type semiconductor structure comprising a first region and a second region surrounding the first region, and the first-type semiconductor structure comprises a top surface located in the first region; An active structure located on the second region, and the first region does not have the active structure; A second-type semiconductor structure located on the active structure; An insulating structure covering the first-type semiconductor structure and having a first opening located in the first region, the first opening exposing the top surface; A first metal layer located in the first opening and in contact with the top surface, the first metal layer having an upper surface away from the top surface, and the upper surface does not contact the insulating structure; and A second metal layer is located on the first metal layer, and the second metal layer has a different metal material from the first metal layer. A semiconductor device as claimed in claim 1, wherein the first metal layer has a first width and the second metal layer has a second width greater than the first width. A semiconductor device as claimed in claim 1, wherein the material of the first metal layer is Cr, Ti, Ni, BeAu or GeAu. A semiconductor device as claimed in claim 1, wherein the insulating structure has a side wall and the first metal layer contacts the side wall. A semiconductor device as claimed in claim 4, wherein the second metal layer contacts the side wall. A semiconductor device as claimed in claim 1, wherein the material of the second metal layer is Pt, Al, Ti, Ni, TiW or Au. A semiconductor device as claimed in claim 1, wherein the insulating structure covers the second type semiconductor structure and has a second opening located in the second region. The semiconductor element of claim 7 further includes a third metal layer located in the second opening and in contact with the second type semiconductor structure, and a fourth metal layer located in the second opening and in contact with the third metal layer, the third metal layer has a third width and the fourth metal layer has a fourth width greater than the third width. A semiconductor device as claimed in claim 1, wherein the insulating structure includes a Bragg reflection structure. A semiconductor device as claimed in claim 1, wherein the first metal layer has a first thickness, and the second metal layer has a second thickness greater than the first thickness.

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