TWI811778B - Optoelectronic semiconductor device - Google Patents

Abstract

An optoelectronic semiconductor device is provided, including: a first semiconductor structure including a first laminated mirror, having a first intrinsic lattice constant and a first width of less than 50 μm; a second semiconductor structure located on the first semiconductor structure, wherein the second semiconductor structure includes an active region and has a second intrinsic lattice constant. The difference between the first intrinsic lattice constant and the second intrinsic lattice constant is greater than 0.5%, and the active region is in direct contact with the first semiconductor structure.

Description

Optoelectronic semiconductor components

The present invention relates to an optoelectronic semiconductor element, and in particular to an optoelectronic semiconductor element having a laminated mirror.

Semiconductor components are used in a wide range of applications, and research and development on related materials continues. For example, III-V semiconductor materials containing Group III and Group V elements can be used in various optoelectronic semiconductor devices such as light-emitting wafers (such as light-emitting diodes or laser diodes), light-absorbing wafers (photodetectors) or solar cells) or non-luminous wafers (such as power components of switches or rectifiers), which can be used in lighting, medical, display, communications, sensing, power supply systems and other fields. With the development of science and technology, there are still many technical research and development needs for semiconductor components. Although existing semiconductor devices have generally met various needs, they are not satisfactory in all aspects and require further improvement.

Some embodiments of the present invention provide an optoelectronic semiconductor element, including: a first semiconductor structure including a first stacked mirror having a first intrinsic lattice constant and a first width less than 50 μm ; a second semiconductor structure located at the On a semiconductor structure, the second semiconductor structure includes an active region and has a second intrinsic lattice constant; wherein the difference between the first intrinsic lattice constant and the second intrinsic lattice constant is greater than 0.5%, and the active region and the first semiconductor structure direct contact.

1: Epitaxial layer

10: Optoelectronic semiconductor components

11:Part One

12:Part 2

13:Trench

101:Substrate

103: First semiconductor structure

1031:First platform

1032:Second platform

105:Trench

106:Trench

107: Second semiconductor structure

109:Third semiconductor structure

109a: Top surface of third semiconductor structure

111: Localization layer

1111: District 1

1112:Second District

113: First insulation layer

113a: Top surface

114: Second insulation layer

114a:Open your mouth

115: Upper electrode

115a: Conductive part

115b:Connection part

115c:joint part

116:Opening

117: Lower electrode

W1: first width

W2: second width

W: Width

w: extended width

d: Epitaxial defects

AA:line

BB:line

D:Outer diameter

E: edge

F: Predetermined cutting position

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of elements may be arbitrarily enlarged or reduced in order to clearly illustrate the features of the embodiments of the invention.

Figure 1A is a top view of an optoelectronic semiconductor device according to some embodiments of the present invention.

Figure 1B is a cross-sectional view along line A-A in Figure 1A, according to some embodiments of the present invention.

Figure 1C is a cross-sectional view along line B-B in Figure 1A, according to some embodiments of the present invention.

2 to 8 are partial cross-sectional views illustrating various intermediate stages in the process of forming an optoelectronic semiconductor device according to some embodiments of the present invention.

The following provides a number of different embodiments or examples for implementing different components of the invention. Specific examples of components and configurations are described below to simplify the invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example It is said that the description mentioning that the first component is formed on the second component may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components, such that Embodiments in which the first and second components are not in direct contact. In addition, the present invention may repeat reference symbols and/or letters in various examples. Such repetition is for purposes of simplicity and clarity and does not in itself govern the relationship between the various embodiments and/or configurations discussed. Additionally, different components may be arbitrarily drawn at different scales for purposes of simplicity and clarity.

Furthermore, spatially related terms may be used here, such as "under", "below", "below", "above", "above", and similar terms may be used This is used to describe the relationship between one element or component and other elements or components as shown in the figures. These spatial terms are intended to cover the various orientations of the device in use or operation, in addition to the orientation depicted in the diagrams. For example, if the device in the picture is turned over, elements described as "lower than" or "beneath" other elements or features would then be described as "above" the other elements or features. Therefore, the exemplary term "below" can have both the orientations of "above" and "below". When the device is rotated 90° or at other orientations, the spatially relative descriptors used herein may be interpreted similarly to the rotated orientation.

The composition of each layer, dopant and defects included in the semiconductor device of the present invention can be analyzed by any suitable method, such as: secondary ion mass spectrometer (SIMS), transmission electron microscope (transmission electron) microscopy (TEM) or scanning electron microscope (SEM); the thickness of each layer can also be Analyzed by any suitable method, such as: transmission electron microscope (transmissionelectron microscopy, TEM) or scanning electron microscope (scanning electron microscope, SEM).

According to some embodiments of the present invention, by forming the first semiconductor structure with a small mesa with a smaller width, the ability to tolerate lattice mismatch is improved to facilitate the growth of the second semiconductor structure in the lattice mismatch. on the first semiconductor structure, and at the same time has good epitaxial quality, thus improving the luminous efficiency of the optoelectronic semiconductor element.

Optoelectronic semiconductor components include light-emitting wafers (such as light-emitting diodes or laser diodes), light-absorbing wafers (photodetectors or solar cells), or non-light-emitting wafers (such as power components of switches or rectifiers). In some embodiments, the optoelectronic semiconductor element 10 is a laser element, such as a vertical-cavity surface-emitting laser (VCSEL). In some specific embodiments, the optoelectronic semiconductor device 10 is a surface-emitting laser diode that emits infrared light.

Figures 1A and 1B are respectively a top view and a cross-sectional view of an optoelectronic semiconductor device according to an embodiment of the present invention. The optoelectronic semiconductor device 10 includes an epitaxial stack 1 having a first portion 11 and a second portion 12 separated from each other. In the top view, the first part 11 is surrounded by the second part 12, and the first part 11 has a first top view area, the second part 12 has a second top view area larger than the first top view area, and the second top view area is the first 2 to 10 times the upper viewing area. In this embodiment, when viewed from above, the first part 11 is generally circular. There is a groove 13 between the first part 11 and the second part 12 , and the groove 13 is generally annular surrounding the first part 11 . In this embodiment, viewed from the cross section, the trench 13 is located between the first part 11 , the second part 12 and the substrate 101 . Optoelectronic semiconductor element The device 10 further includes an upper electrode 115 located above the first portion 11, the second portion 12 and the trench 13, and the upper electrode 115 has an opening 116 to expose a portion of the first portion 11. The optoelectronic semiconductor element 10 is The generated light can be emitted outside the optoelectronic semiconductor element 10 through the opening 116 .

Specifically, in this embodiment, the first part 11 is used to emit light, and the second part 12 provides a platform for subsequent wire bonding. That is, if the optoelectronic semiconductor element 10 is a light-emitting element, the light is emitted from the first part 11 emitted, the second part 12 does not emit light. Or, when the second part 12 can emit light, most or all of the light emitted by it will be blocked by the upper electrode 115 and cannot emit out of the optoelectronic semiconductor element 10 , so the brightness of the light emitted by the second part 12 (mW) Less than the brightness of the light emitted by the first part 11 (for example, the brightness of the light emitted by the second part 12 is 0% to 10% of the brightness of the light emitted by the first part 11).

Figure 1B is a schematic cross-sectional view along line A-A in Figure 1A, and Figure 1C is a schematic cross-sectional view along line B-B in Figure 1A. The optoelectronic semiconductor device 10 includes a substrate 101 on which the epitaxial layer 1 is located, and the first portion 11 and the second portion 12 each include a first semiconductor structure 103 and a second semiconductor structure 107 .

The first part 11 and the second part 12 each further include a third semiconductor structure 109 located on the second semiconductor structure 107 and optionally a confinement layer 111 located between the second semiconductor structure 107 and the third semiconductor structure 109 . In other embodiments, the confinement layer 111 may also be selectively located between the first semiconductor structure 103 and the second semiconductor structure 107; in another embodiment, the confinement layer 111 may be selectively located in the third semiconductor structure 109. The localization layer 111 includes a first area 1111 and a second area 1112 surrounded by the first area 111 Surrounded by; and viewed from above, the first area 1111 is ring-shaped. The second area 1112 is used to allow current to pass through and the first area 1111 is used to limit the current to pass through. In this embodiment, the confinement layer 111 of the second part 12 is located on the side close to the trench 13, the second part 12 is on the side away from the trench 13, and the edge E adjacent to the optoelectronic semiconductor element 10 does not have any The first zone 1111 through which current flows. In addition, in this embodiment, through the arrangement of the upper electrode 115 and the second insulating layer 114, current is only injected into the first part 11. Therefore, even though the second part 12 has a structural second region 1112, in practice there is almost no Electric current passes through the second zone 1112 of the second portion 12 . In this embodiment, the sidewalls of the first semiconductor structure 103, the second semiconductor structure 107, the third semiconductor structure 109 and the confinement layer 111 may be aligned. The first semiconductor structure 103 , the second semiconductor structure 107 , the third semiconductor structure 109 and the confinement layer 111 together form the epitaxial stack 1 .

The optoelectronic semiconductor device 10 further includes a first insulating layer 113 covering the first semiconductor structure 103 , the second semiconductor structure 107 , the third semiconductor structure 109 and the sidewalls of the confinement layer 111 , and the first insulating layer 113 is located in the trench 13 . The second insulating layer 114 is located on the first insulating layer 113 and the epitaxial layer 1 , and has a plurality of openings 114 a to expose a portion of the top surface 109 a of the third semiconductor structure 109 of the first portion 11 . The trench 13 has an outer diameter D between 50 μm and 70 μm , as shown in Figure 1A.

As shown in FIG. 1A, the upper electrode 115 is located on the second insulating layer 114 and includes a conductive portion 115a, a connecting portion 115b, and a joint portion 115c. The conductive part 115a covers part of the second insulating layer 114 and the first part 11, and has an opening 116 to expose part of the second insulating layer 114. The bonding portion 115c is used as a wire bonding area, and the bonding portion 115c is generally circular. In this embodiment, the diameter of the joint portion 115c is between 40 μm and 60 μm . The connection part 115b connects the conductive part 115a and the joint part 115c, and is located on the trench 13.

The first semiconductor structure 103 and the third semiconductor structure 109 include III-V compound semiconductor materials. In this embodiment, the first semiconductor structure 103 and the third semiconductor structure 109 are formed by stacking a plurality of III-V compound semiconductor materials. A first laminated reflector and a second laminated reflector. Specifically, the first semiconductor structure 103 and the third semiconductor structure 109 include an alternating periodic stacking of a plurality of film layers with different refractive indexes (for example, an alternating periodic stacking of an AlGaAs layer with a high aluminum content and an AlGaAs layer with a low aluminum content). ) to form a Distributed Bragg Reflector (DBR), whereby the light emitted from the second semiconductor structure 107 can be reflected in the two reflectors (the first semiconductor structure 103 and the third semiconductor structure 109) To form synchronized light. In some embodiments, the number of film pairs formed by alternately stacking two film layers with different refractive indexes may range from 2 pairs to about 100 pairs. The reflectivity of the first semiconductor structure 103 is higher than the reflectivity of the third semiconductor structure 109 , thereby causing the coherent light to be emitted toward the direction of the upper electrode 115 . In some embodiments, the first semiconductor structure 103 and the third semiconductor structure 109 include _{AlxGa1 -xAs} , where 0<x<1. In some embodiments, the materials of the first semiconductor structure 103 and the third semiconductor structure 109 include AlGaAs and/or InGaP.

The second semiconductor structure 107 includes an active region that can be used to emit light or receive light. The active region can be selected as a Multi Quantum Wells (MQWs) structure (not shown), which can emit near-infrared light wavelengths, for example, can emit a peak wavelength between 800nm and 2000nm (for example: 1200nm, 1550nm). In some embodiments, the second semiconductor structure 107 may include a III-V semiconductor material, such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In some embodiments, the material of the second semiconductor structure 107 is InP.

＊100%>0.5%。在一些實施例中，第一本質晶格常數A1與第二本質晶格常數A2相差介於2%至6%之間，例如介於2%至3%之間、介於3%至4%之間、介於5%至6%之間。當第一半導體結構103具有複數層半導體材料時，上述之第一本質晶格常數A1係指第一半導體結構103中與第二半導體結構107直接接觸之層的本質晶格常數。「本質晶格常數」係定義為一實質上無應變(strain)之層的晶格常數a₀。 In this embodiment, the first semiconductor structure 103 has a first intrinsic lattice constant A1, and the second semiconductor structure 107 has a second intrinsic lattice constant A2 different from the first intrinsic lattice constant A1. In detail, the difference between the first intrinsic lattice constant A1 of the first semiconductor structure 103 and the second intrinsic lattice constant A2 of the second semiconductor structure 107 is greater than 0.5%, that is,

*100%>0.5%. In some embodiments, the difference between the first intrinsic lattice constant A1 and the second intrinsic lattice constant A2 is between 2% and 6%, such as between 2% and 3%, between 3% and 4%. between, between 5% and 6%. When the first semiconductor structure 103 has a plurality of layers of semiconductor material, the above-mentioned first intrinsic lattice constant A1 refers to the intrinsic lattice constant of the layer in the first semiconductor structure 103 that is in direct contact with the second semiconductor structure 107 . "Intrinsic lattice constant" is defined as the lattice constant a ₀ of a substantially strain-free layer.

As mentioned above, the difference in intrinsic lattice constants of the first semiconductor structure 103 and the second semiconductor structure 107 is greater than 0.5%, that is, the first semiconductor structure 103 and the second semiconductor structure 107 do not have a lattice matching. Due to lattice mismatch, epitaxial defects and stress will be formed in the second semiconductor structure 107 on the first semiconductor structure 103. Therefore, the second semiconductor structure 107 is usually prone to poor epitaxial quality, which affects the luminous efficiency of the optoelectronic semiconductor device. . However, by designing the width of the first semiconductor structure 103, the second semiconductor structure 107 subsequently grown thereon can have lower epitaxial defects and stress and have good epitaxial quality. Specifically, in this embodiment, the first width W1 of the first semiconductor structure 103 in the first part 11 is less than 50 μm , which enables the second semiconductor structure 107 subsequently grown thereon to have good epitaxial quality, thereby improving Luminous efficiency of optoelectronic semiconductor devices (process steps will be described later). In some embodiments, the first width W1 is between 20 μm and 50 μm , such as between 30 μm and 40 μm . Correspondingly, the second portion 12 has a second width W2 greater than 50 μm , so the second semiconductor structure 107 subsequently grown thereon has a poor ability to tolerate lattice mismatch, and has a higher density and a larger number of epitaxial defects. (Here represented by a black line d), for example: V-defect, edge dislocation, screw dislocation, or mix dislocation. In some embodiments, the second width W2 is between 50 μm and 300 μm , between 80 μm and 280 μm , between 100 μm and 250 μm , or between 150 μm and 200 μm . between. In this embodiment, the second width W2 is 2 times to 8 times the first width W1.

In one embodiment, the first portion 11 has a first defect density, and the second portion 12 has a second defect density greater than the first defect density. The above defect density can be observed and calculated by TEM. For example, the defect area (or number of defects) located in the first part 11 divided by the cross-sectional area of the first part 11 is the first defect density. Similarly, the defect density located in the second part The defect area (or number of defects) in 12 divided by the cross-sectional area of the second part 12 is the second defect density.

In this embodiment, the second semiconductor structure 107 has a thickness between 5 μm and 200 μm , for example, between 10 μm and 50 μm . Since the second semiconductor structure 107 is an active region where holes and electrons recombine to emit light, if its thickness is less than 5 μm , poor luminous efficiency may result; at the same time, as mentioned above, the second semiconductor structure 107 and the first semiconductor structure 103 Due to lattice mismatch, although the width of the first semiconductor structure 103 (for example, the first portion 11) can be designed to effectively suppress defect generation, when the thickness of the second semiconductor structure 107 is greater than 200 μm , the defects cannot be effectively suppressed. As a result, the luminous efficiency of the optoelectronic semiconductor 10 is drastically reduced.

To sum up, the optoelectronic semiconductor element 10 of this embodiment includes a first part 11 and a second part 12 with different epitaxial qualities. Since the first part 11 is used to emit light, good epitaxial quality helps to improve the luminous efficiency, and The second part 12 is only used as a support area during wire bonding. Even if the epitaxial quality is not as good as the first part 11 , it still does not affect the characteristics of the optoelectronic semiconductor element 10 .

2 to 8 are cross-sectional views of the first part 11 and the second part 12 at various stages in the process of forming the optoelectronic semiconductor device 10 according to some embodiments of the present invention, and are as shown in FIG. 1A The A-A direction is illustrated as a cross-section.

＊100%<0.5%。(例如0.01%至0.45%、0.05%至0.3%、0.1%至0.2%)，藉由採用與第一半導體結構103晶格相近的基板101，可以使生長於基板101的第一半導體結構103擁有良好的磊晶品質。在一些實施例中，基板101可具有厚度介於50μm至500μm之間。基板101可為砷化鎵。 Referring to FIG. 2 , a substrate 101 is provided, and a first semiconductor structure 103 is formed on the substrate 101 . Substrate 101 may include insulating materials, conductive materials, or both. The insulating material may include, for example, materials such as sapphire, diamond, glass, quartz, acrylic or AlN. The conductive material may include, for example, the following materials: Gallium Arsenide (GaAs), Indium Phosphide (InP), Silicon Carbide (SiC), Gallium Phosphide (GaP), Gallium Arsenide Phosphide (GaAsP) , zinc oxide (ZnO), zinc selenide (ZnSe), gallium nitride (GaN), aluminum nitride (AlN), lithium gallate (LiGaO ₂ ), lithium aluminate (LiAlO ₂ ), germanium (Ge) or silicon (Si). In some embodiments, when the substrate 101 is used to provide the first semiconductor structure 103 with epitaxial growth thereon, its material can be selected from materials with a lattice close to that of the first semiconductor structure 103. The above lattice similarity is defined as the substrate. The difference between the intrinsic lattice constants of 101 and the first semiconductor structure 103 is less than 0.5%, that is, the substrate 101 has a third intrinsic lattice constant A3, where,

*100%<0.5%. (For example, 0.01% to 0.45%, 0.05% to 0.3%, 0.1% to 0.2%), by using a substrate 101 with a crystal lattice similar to that of the first semiconductor structure 103, the first semiconductor structure 103 grown on the substrate 101 can have Good epitaxial quality. In some embodiments, the substrate 101 may have a thickness between 50 μm and 500 μm . The substrate 101 may be gallium arsenide.

Referring to FIG. 3 , a suitable selective etching process can be used to remove part of the first semiconductor structure 103 to create a plurality of first trenches 105 in the first semiconductor structure 103 to form a plurality of first platforms 1031 and a plurality of first platforms 1031 . Two platforms 1032. The first platform 1031 and the second platform 1032 have different widths. The first platform 1031 has a width W less than 50 μm . The value of the width W mentioned here is approximately equal to the value of the first width W1 of the first portion 11 of the optoelectronic semiconductor element 10 .

In some embodiments, the etching process for forming the first trench 105 may include dry etching, wet etching, and/or other suitable processes. For example, the dry etching process may include plasma etching (PE), reactive ion etching (RIE), and inductively coupled plasma reactive ion etching (ICP-RIE). The gas for the above-mentioned etching reaction may include oxygen-containing gas, fluorine-containing gas (such as tetrafluorocarbon, sulfur hexafluoride, difluoromethane, fluoroform, and/or hexafluoroethane), chlorine-containing gas (such as chlorine, chloroform , carbon tetrachloride, and/or boron trichloride), bromine-containing gases (such as hydrogen bromide and/or bromoform), iodine-containing gases, and/or combinations of the above. For example, the wet etching process may use an acidic solution or an alkaline solution. Acidic solutions may include hydrofluoric acid, phosphorus A solution of acid, nitric acid, acetic acid or a combination of the foregoing; the alkaline solution may include a solution containing potassium hydroxide, ammonia, hydrogen peroxide or a combination of the foregoing.

Referring to FIGS. 4 and 5 , a second semiconductor structure 107 is formed on the first semiconductor structure 103 , and a third semiconductor structure 109 is formed on the second semiconductor structure 107 . In this embodiment, before forming the third semiconductor structure 109, a confinement layer 111 can be preformed on the second semiconductor structure 107. Then, parts of the second semiconductor structure 107 and the third semiconductor structure 109 are removed, and a plurality of second trenches 106 are formed in the second semiconductor structure 107 and the third semiconductor structure 109, and the second trenches 106 are generally aligned with the second semiconductor structure 107 and the third semiconductor structure 109. A groove 105, both of which together form the above-mentioned groove 13. The method of forming the second trench 106 may refer to the above-described method of forming the first trench 105 .

In some embodiments, the first semiconductor structure 103 , the second semiconductor structure 107 , the confinement layer 111 and the third semiconductor structure 109 can be formed by the following epitaxial growth process, such as metal-organic chemical vapor deposition (metal-organic chemical vapor deposition). chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) or liquid-phase epitaxy (LPE), gas Phase epitaxy (vapor phase epitaxy, VPE), or a combination of the above. In this embodiment, MOCVD is used to form the first, second, and third semiconductor structures.

In some embodiments, the first semiconductor structure 103 and the second semiconductor structure 103 may be formed by in-situ doping during epitaxial growth and/or by implanting using dopants after epitaxial growth. Doping of the three-semiconductor structure 109. The first semiconductor structure 103 may include a first dopant to have a first conductivity type, The third semiconductor structure 109 may include a second dopant to have a second conductivity type. The first semiconductor structure 103 and the third semiconductor structure 109 have different conductivity types, that is, the first conductivity type and the second conductivity type are different. The first conductivity type is, for example, p-type and the second conductivity type, such as n-type, is provided to provide holes and electrons respectively. Alternatively, the first conductivity type is, for example, n-type and the second conductivity type is, for example, p-type, to provide electrons or electrons respectively. Hole. In an embodiment, the first dopant or the second dopant may be magnesium (Mg), zinc (Zn), silicon (Si), carbon (C) or tellurium (Te).

Continue to refer to Figure 6. The confinement layer 111 can be oxidized through a wet oxidation process to form the first region 1111 and the second region 1112 to facilitate transverse confinement of light and electricity. The extension width w of the first region 1111 of the confinement layer 111 can be adjusted by appropriately controlling the oxidation rate and process time. The lateral extension width w of the first region 1111 can be between 5 μm and about 20 μm, such as 10 μm. The material of the confinement layer 111 has a high aluminum content, and the aluminum content in the confinement layer 111 is higher than that of the first semiconductor structure 103, the second semiconductor structure 107, and the third semiconductor structure 109. Therefore, during the wet oxidation process, the confinement layer 111 The oxidation rate is greater than the oxidation rate of other layers to form the first region 1111 with a current localization effect. In this embodiment, the localization layer 111 includes _{AlxGa1 -xAs} , where 0.9<x<1.

Next, referring to FIG. 7 , insulating material is filled in the trench 13 to form the first insulating layer 113 . In some embodiments, the first insulating layer 113 is in contact with the first semiconductor structure 103, the second semiconductor structure 107, the confinement layer 111 and the third semiconductor structure 109, and surrounds the active area, thereby protecting the first semiconductor structure 103, The second semiconductor structure 107, the confinement layer 111 and the sidewalls of the third semiconductor structure 109 further improve the life and reliability of the optoelectronic semiconductor element. In some embodiments, the insulating material may include an oxide insulating material, a non-oxide insulating material, or a combination of the foregoing. For example, the oxide insulating material may include silicon oxide (SiO _x ); the non-oxide insulating material may include silicon nitride (SiN _x ), benzocyclobutene (BCB), cycloolefin copolymer (cycloolefin copolymer) , COC) or fluorocarbon polymer, calcium fluoride (CaF ₂ ) or magnesium fluoride (MgF ₂ ). In some embodiments, the insulating material is preferably benzocyclobutene (BCB). In some embodiments, a deposition process may be used to form the first insulating layer 113, such as chemical vapor deposition (CVD), spin coating, atomic layer deposition (ALD) or combination thereof.

In one embodiment, after filling the insulating material, a planarization process (for example, a chemical mechanical planarization (CMP) process) may be performed, so that the top surface 113a of the first insulating layer 113 is in contact with the third semiconductor structure. The top surface 109a of 109 is coplanar to provide a flat surface to facilitate the placement of upper electrodes in subsequent processes, so that each upper electrode can be connected at the same level, thereby improving yield and reliability. Next, a second insulating layer 114 is formed on the top surfaces 109a and 113a. The second insulating layer 114 has a plurality of openings 114a to expose part of the upper surface of the first part 11. The material of the second insulating layer 114 can be selected as the material of the first insulating layer 113 described above. In other embodiments, the first insulating layer 113 and the second insulating layer 114 can also be made in one step. For example, when making the insulating layer, in addition to filling the trench 13 with the insulating material, the insulating material continues to be deposited on the epitaxial layer. On layer 1, a plurality of openings 114a are patterned to expose a portion of the upper surface of the first portion 11. Referring to Figure 8, an upper electrode 115 is formed on the third semiconductor structure 109. The upper electrode 115 fills a plurality of openings 114a to contact the epitaxial layer 1, and the upper electrode 115 has openings 116 to connect part of the second insulating layer. 114 exposed. Next, a lower electrode 117 is formed below the substrate 101 . In some embodiments, the materials of the upper electrode 115 and the lower electrode 117 may be the same or different, and each may include a metal oxide material, a metal, or an alloy. Metal oxide materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO) ), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). Examples of metals include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), and copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), and zinc gold (ZnAu).

The structure in Figure 8 is cut and singulated to form a plurality of optoelectronic semiconductor elements 10 as shown in Figures 1A to 1C. The cutting process can be carried out by laser cutting or wheel knife cutting. In other embodiments, a plurality of trenches can be selectively formed at the predetermined cutting position F for single graining. Specifically, the epitaxial layer 1 at the predetermined cutting position F is removed and then cut, so as to Improve cutting yield.

As shown in FIGS. 1A, 1B, and 8, the first platform 1031, the second semiconductor structure 107, the localization layer 111, and the third semiconductor structure 109 formed thereon are defined as the first portion 11. The two second platforms adjacent to the first platform 1031 are A portion of the second platform 1032 and the second semiconductor structure 107, the confinement layer 111, and the third semiconductor structure 109 formed thereon are Defined as Part II 12.

As described in the above process, in the present disclosure, since the first platform 1031 with a width W of less than 50 μm is formed in the step of FIG. 3, the subsequent growth has a lattice mismatch with the first semiconductor structure 103. The second semiconductor structure 107 can have good quality epitaxial crystals, thereby improving the luminous efficiency of the optoelectronic semiconductor element. Compared with the complicated process required by the bonding process for alleviating the lattice mismatch, the process of the present invention is relatively simple.

The components of several embodiments are summarized above so that those with ordinary skill in the technical field to which the present invention belongs can more easily understand the concepts of the embodiments of the present invention. Those with ordinary skill in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments introduced here. Those with ordinary skill in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can be used without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and substitutions.

10: Optoelectronic semiconductor components

11:Part One

12:Part 2

13:Trench

101:Substrate

103: First semiconductor structure

107: Second semiconductor structure

109:Third semiconductor structure

109a: Top surface of third semiconductor structure

111: Localization layer

1111: District 1

1112:Second District

113: First insulation layer

114: Second insulation layer

114a:Open your mouth

115: Upper electrode

115a: Conductive part

115b:Connection part

115c:joint part

116:Opening

117: Lower electrode

W1: first width

d: Epitaxial defects

E: edge

Claims (10)

An optoelectronic semiconductor component, including: A first semiconductor structure including a first stacked mirror and having a first intrinsic lattice constant and a first width less than 50 μm; and a second semiconductor structure located on the first semiconductor structure, wherein the second semiconductor structure includes an active region in direct contact with the first semiconductor structure and has a second intrinsic lattice constant; The difference between the first intrinsic lattice constant and the second intrinsic lattice constant is greater than 0.5%. The optoelectronic semiconductor element according to claim 1, wherein the optoelectronic semiconductor element is a laser element. The optoelectronic semiconductor device as claimed in claim 1, wherein the active region can emit light with a wavelength between 800 nm and 2000 nm. The optoelectronic semiconductor device according to claim 1, wherein the material of the first semiconductor structure includes AlGaAs and/or InGaP, and the material of the second semiconductor structure is InP. The optoelectronic semiconductor device according to claim 1, wherein the difference between the first intrinsic lattice constant and the second intrinsic lattice constant is between 2% and 6%. The optoelectronic semiconductor device according to claim 1, wherein the first width of the first semiconductor structure is between 20 μm and 50 μm. The optoelectronic semiconductor component as described in claim 1 further includes: A third semiconductor structure is located on the second semiconductor structure and has a second stacked mirror. The optoelectronic semiconductor device as claimed in claim 7, comprising: an epitaxial stack including a first part and a second part, and the first part has a first defect density, and the second part has a second defect density. Greater than the first defect density; a trench located between the first part and the second part; and an electrode located on the epitaxial stack and having an opening on the first part; wherein, the epitaxial The stack includes the first stacked mirror, the active area and the second stacked mirror. The optoelectronic semiconductor device as claimed in claim 8, wherein the trench surrounds the first part. The optoelectronic semiconductor device according to claim 8, wherein the first portion has a first width between 20 μm and 50 μm .

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