TWI888068B - Semiconductor structure for 3d memory device and manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor structure for a three-dimensional (3D) memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate, an insulating wall and a stacked structure. The substrate has an array region and a staircase region surrounding the array region. The insulating wall is disposed on the substrate and surrounds the array region and the staircase region. The stacked structure is disposed on the substrate in the array region and the staircase region, and includes a plurality of insulating layers and a plurality of conductive layers alternately stacked. The plurality of insulating layers and the plurality of conductive layers extend conformally onto the insulating wall.

Description

Semiconductor structure for three-dimensional memory and method for manufacturing the same

The present invention relates to a semiconductor structure and a method for manufacturing the same, and in particular to a semiconductor structure for three-dimensional memory and a method for manufacturing the same.

Non-volatile memory (such as flash memory) has the advantage that the stored data will not disappear even after power failure, so it has become a type of memory widely used in personal computers and other electronic devices.

In current three-dimensional flash memory, in the stacked structure located in the staircase region, each word line is electrically connected to the upper wiring layer through the contact-on-array (COA) above the memory array. These COAs are important keys to operate memory cells at different levels.

Generally speaking, during the process of forming COA, COA holes that expose word lines are formed in the stacking structure in the step area through an etching process. These COA holes have different depths corresponding to word lines of different layers, so a longer etching time is required to form deeper COA holes. As a result, during the etching process, the word lines located at the upper part of the stacking structure are easily damaged by over-etching. In addition, when forming COA holes, if the alignment is insufficient, the position of the formed COA holes will be offset, resulting in bridge problems for word lines of different layers.

The present invention provides a semiconductor structure for three-dimensional memory and a manufacturing method thereof, wherein an insulating wall is formed on a substrate and surrounds an array region and a step region, and a stacking structure including a plurality of insulating layers and a plurality of conductive layers stacked alternately is formed on the substrate in the array region and the step region and conformally extends to the insulating wall.

The semiconductor structure for three-dimensional memory of the present invention includes a substrate, an insulating wall and a stacking structure. The substrate has an array region and a step region surrounding the array region. The insulating wall is arranged on the substrate and surrounds the array region and the step region. The stacking structure is arranged on the substrate in the array region and the step region, and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend to the insulating wall.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the insulating wall has a stepped profile and includes a plurality of steps, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend onto the plurality of steps.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, each of the plurality of steps includes a top surface and a side wall; each of the plurality of insulating layers and the plurality of conductive layers except the top insulating layer includes a main body and an extension connected to the main body, and the top insulating layer includes the main body; the extension of each of the plurality of insulating layers and the plurality of conductive layers except the top insulating layer and the top conductive layer includes at least one first portion and at least one second portion. The second portion is provided on the uppermost conductive layer, and the extension of the uppermost conductive layer includes a second portion, wherein the first portion is provided corresponding to the top surface, and the second portion is provided corresponding to the side wall; the uppermost second portion of each of the conductive layers except the uppermost conductive layer and the second portion of the uppermost conductive layer are exposed by the uppermost first portion of each of the insulating layers except the uppermost insulating layer and the main body of the uppermost insulating layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the topmost second portion of each of the conductive layers except the topmost conductive layer and the top surface of the second portion of the topmost conductive layer are coplanar with the topmost first portion of each of the insulating layers except the topmost insulating layer and the top surface of the main body of the topmost insulating layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, each of the conductive layers has a first thickness, each of the insulating layers has a second thickness, the top surface of each of the steps has a depth, and the distance between the centers of the second portions of two adjacent conductive layers is the sum of the first thickness, the second thickness and the depth.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the end of the extension portion of the conductive layer is connected to the end of the main body.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, a supporting column is further included, which penetrates the stacking structure from the end of the extension portion of the insulating layer and is disposed on the substrate.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the supporting pillar further penetrates the insulating wall.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, a supporting wall is further included, which penetrates the stacking structure and the insulating wall and is disposed on the substrate and extends in the plane direction of the substrate.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, it further includes a plurality of contact windows, each of which is connected to the end of the corresponding conductive layer.

The manufacturing method of the semiconductor structure for three-dimensional memory of the present invention includes the following steps. Providing a substrate, wherein the substrate has an array region and a step region surrounding the array region; forming an insulating wall surrounding the array region and the step region on the substrate, wherein; forming a stacking structure on the substrate in the array region and the step region, wherein the stacking structure includes a plurality of insulating layers and a plurality of conductive layers stacked alternately. The plurality of insulating layers and the plurality of conductive layers conformally extend to the insulating wall.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, the insulating wall has a stepped profile and includes a plurality of steps, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend onto the plurality of steps.

In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory of the present invention, each of the plurality of steps includes a top surface and a side wall; each of the plurality of insulating layers and the plurality of conductive layers except the top insulating layer includes a main body and an extension connected to the main body, and the top insulating layer includes the main body; the extension of each of the plurality of insulating layers and the plurality of conductive layers except the top insulating layer and the top conductive layer includes at least one first portion and a second portion. At least one second portion, the extension portion of the topmost conductive layer includes a second portion, wherein the first portion is arranged corresponding to the top surface, and the second portion is arranged corresponding to the side wall; the topmost second portion of each of the conductive layers except the topmost conductive layer and the second portion of the topmost conductive layer are exposed by the topmost first portion of each of the insulating layers except the topmost insulating layer and the main body of the topmost insulating layer.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, the topmost second portion of each of the conductive layers except the topmost conductive layer and the top surface of the second portion of the topmost conductive layer are coplanar with the topmost first portion of each of the insulating layers except the topmost insulating layer and the top surface of the main body of the topmost insulating layer.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, each of the conductive layers has a first thickness, each of the insulating layers has a second thickness, the top surface of each of the steps has a depth, and the distance between the centers of the second portions of two adjacent conductive layers is the sum of the first thickness, the second thickness and the depth.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, the end of the extension portion of the conductive layer is connected to the end of the main body.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, a supporting column is formed on the substrate from the end of the extension portion of the insulating layer and penetrates the stacking structure.

In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory of the present invention, the supporting pillar further penetrates the insulating wall.

In one embodiment of the manufacturing method of the semiconductor structure for three-dimensional memory of the present invention, the method for forming the stacking structure includes the following steps. After forming the insulating wall, an initial stacking structure is formed on the substrate surrounded by the insulating wall, wherein the initial stacking structure includes the multiple insulating layers and the multiple sacrificial layers stacked alternately, and the multiple insulating layers and the multiple sacrificial layers conformally extend to the multiple steps. The multiple sacrificial layers are replaced by the multiple conductive layers.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, the insulating layer is a silicon oxide layer, and the sacrificial layer is a silicon nitride layer.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, after forming the initial stacking structure and before replacing the multiple sacrificial layers with the multiple conductive layers, a supporting wall is formed on the substrate, penetrating the initial stacking structure and the insulating wall and extending in the plane direction of the substrate.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, a contact window is formed at the end of each of the conductive layers.

Based on the above, in the semiconductor structure for three-dimensional memory and the manufacturing method thereof of the present invention, an insulating wall is formed on the substrate and surrounds the array region and the step region, and a stacking structure including a plurality of insulating layers and a plurality of conductive layers stacked alternately is formed on the substrate in the array region and the step region and conformally extends to the insulating wall. Therefore, when the semiconductor structure of the present invention is applied to a memory device, the conductive layer in the stacking structure can simultaneously serve as a word line and a contact window connected to the word line, that is, the word line and the contact window are formed in one piece. In this way, the problem of alignment offset between word lines and contact windows can be effectively solved, and there is no need to form contact window holes of different depths to form contact windows connected to word lines of different layers, thereby avoiding the problem of word line damage caused by over-etching during the etching process of forming contact window holes of different depths.

10, 30, 40, 50, 60, 70: semiconductor structure

100: Base

100a: Array area

100b: Stairway area

102, 110: Conductive layer

104: Insulation layer

104a, 300: Insulation wall

106: Initial stack structure

106a, 108: Insulating layer

106b: Sacrifice layer

112, 302: stacking structure

300a:Stairs

400:Supporting column

500:Supporting wall

600: Channel structure

700: Narrow seam

BL: Bit Line

BLOCK:Block

CT: Contact window

DP: Drain column

d: depth

E1, E3: Part 1

E2, E4: Part 2

MC: memory unit

MSC, MSC1, MSC2: memory array

P1, P3, P5: Main body

P2, P2’, P4, P4’: extension

R: Groove

TF: Top

t1, t2: thickness

SL: source line

SP: Source column

SW: side wall

WL: character line

Figures 1A to 1E are schematic cross-sectional views of the manufacturing process of the semiconductor structure of the first embodiment of the present invention.

Figure 2 is a schematic top view of the substrate in Figure 1A.

Figure 3 is a cross-sectional schematic diagram of the semiconductor structure of the second embodiment of the present invention.

Figure 4A and Figure 4B are respectively top view and cross-sectional schematic diagrams of the semiconductor structure of the third embodiment of the present invention.

Figure 5 is a top view schematic diagram of the semiconductor structure of the fourth embodiment of the present invention.

Figure 6 is a top view schematic diagram of the semiconductor structure of the fifth embodiment of the present invention.

FIG7 is a top view schematic diagram of the semiconductor structure of the sixth embodiment of the present invention.

FIG8 is a circuit diagram of a 3D AND flash memory array including the semiconductor structure of the present invention.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

The terms "include", "including", "have", etc. used in this article are all open terms, which means "including but not limited to".

When the terms "first", "second", etc. are used to describe an element, they are only used to distinguish these elements from each other and do not limit the order or importance of these elements. Therefore, in some cases, the first element may also be called the second element, and the second element may also be called the first element, and this does not deviate from the scope of the present invention.

In addition, the directional terms mentioned in the text, such as "upper", "lower", etc., are only used to refer to the direction of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or a film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

Figures 1A to 1E are schematic cross-sectional views of the manufacturing process of the semiconductor structure of the first embodiment of the present invention.

First, referring to FIG. 1A , a substrate 100 is provided. In this embodiment, the substrate 100 may include a silicon substrate. The substrate 100 has an array region 100a and a step region 100b. As shown in FIG. 2 , from a top view from above the substrate 100 , the step region 100b surrounds the array region 100a, and the array region 100a and the step region 100b constitute a memory element region. In this embodiment, FIG. 1A to FIG. 1E are cross-sectional schematic diagrams drawn according to the A-A section line in FIG. 2 .

In this embodiment, the substrate 100 may also include a device structure layer (not shown) formed on a silicon substrate. The device structure layer may include various semiconductor devices that are generally known. For example, the device structure layer may include a transistor formed on the surface of the silicon substrate, an interconnect structure electrically connected to the transistor, and a dielectric layer covering the transistor and the interconnect structure, but the present invention is not limited thereto.

Then, a conductive layer 102 is formed on the substrate 100. In the present embodiment, the conductive layer 102 may be a ground layer, such as a polysilicon layer, but the present invention is not limited thereto. Then, an insulating layer 104 is formed on the conductive layer 102. In the present embodiment, the insulating layer 104 may be a silicon oxide layer, for example, but the present invention is not limited thereto.

Next, referring to FIG. 1B , a portion of the insulating layer 104 is removed to form a groove R in the insulating layer 104 , and the remaining insulating layer 104 forms an insulating wall 104a. In this embodiment, the groove R is a region where a memory element is to be formed. That is, the insulating wall 104a is formed on the substrate 100 and surrounds the array region 100a and the step region 100b.

Then, referring to FIG. 1C , an initial stacking structure 106 is conformally formed on the substrate 100 to cover the conductive layer 102 exposed by the groove R and the sidewalls and top surface of the insulating wall 104a. The initial stacking structure 106 includes a plurality of insulating layers 106a and a plurality of sacrificial layers 106b stacked alternately, and the bottommost layer is the insulating layer 106a. In FIG. 1C , the number of the insulating layer 106a and the sacrificial layer 106b is only exemplary, and the present invention is not limited thereto. In this embodiment, the insulating layer 106a is a silicon oxide layer, and the sacrificial layer 106b is a silicon nitride layer, but the present invention is not limited thereto. After the initial stacking structure 106 is formed, an insulating layer 108 is formed on the initial stacking structure 106 to fill the groove R. In this embodiment, the insulating layer 108 is a silicon oxide layer.

Next, referring to FIG. 1D , the initial stacking structure 106 and the insulating layer 108 outside the groove R are removed. At this time, the top surface of the remaining insulating layer 106a, the top surface of the remaining sacrificial layer 106b, the top surface of the remaining insulating layer 108, and the top surface of the insulating wall 104a in the groove R are coplanar. In the present embodiment, the method of removing the initial stacking structure 106 and the insulating layer 108 outside the groove R is, for example, an etching back process, but the present invention is not limited thereto. In addition, in the process of removing the initial stacking structure 106 and the insulating layer 108 outside the groove R, a portion of the insulating wall 104a may be slightly removed, so that the insulating wall 104a has a reduced height.

Afterwards, please refer to FIG. 1E , a replacement process is performed to replace the sacrificial layer 106b with a conductive layer 110. The conductive layer 110 includes a metal layer, such as a tungsten layer. The above replacement process is well known to those skilled in the art and will not be described in detail here. In this embodiment, the stacked insulating layer 106a, the conductive layer 110, and the insulating layer 108 form a stacked structure 112 in the groove R. In other words, the stacked structure 112 is formed in the array region 100a and the step region 100b, and conformally extends to the sidewall of the insulating wall 104a. At this time, the end of each conductive layer 110 is exposed. In this way, the semiconductor structure 10 of this embodiment is formed.

In addition, after forming the semiconductor structure 10, a contact window CT connected to the end of each conductive layer 110 may be formed.

The semiconductor structure 10 of this embodiment can be applied to a three-dimensional AND flash memory. When the semiconductor structure 10 of this embodiment is applied to a three-dimensional AND flash memory, a process of forming a channel structure, supporting pillars, supporting walls, etc. can be performed, which is well known to those skilled in the art and will not be further described here.

When the semiconductor structure 10 of the present embodiment is applied to a memory element, the conductive layer 110 in the stacked structure 112 can be used as a word line and a contact window connected to the word line at the same time. In detail, as shown in FIG. 1E , in the stacked structure 112, each insulating layer 106a includes a main body P1 extending in the plane direction of the substrate 100 and an extension P2 connected to the end of the main body P1 and extending in a direction perpendicular to the plane direction of the substrate 100. The extension P2 extends from the main body P1 to the side wall of the insulating wall 104a. In addition, the uppermost insulating layer 108 in the stacked structure 112 includes a main body P5 without an extension.

In addition, in the stacked structure 112, each conductive layer 110 includes a main body P3 disposed in parallel with the main body P1 and an extension P4 connected to the end of the main body P3 and disposed in parallel with the extension P2. The main body P3 can be used as a word line, and the extension P4 can be used as a contact window connected to the word line. That is, in the semiconductor structure 10, the word line and the contact window are formed in one piece, and there is no interface between the two. Therefore, the alignment offset problem between the word line and the contact window is effectively solved. In addition, since the word line and the contact window are formed in one piece, it is not necessary to form contact window holes of different depths to form contact windows connected to word lines of different layers, thereby avoiding the problem of word line damage caused by over-etching in the etching process of forming contact window holes of different depths. In other words, in this embodiment, as shown in FIG. 1E, the connection area (landing area) for connecting to the contact window CT can be located at the same horizontal height.

In the stacked structure 112, the end of the extension portion P4 of each conductive layer 110 is exposed by the extension portion P2 of the insulating layer 106a and the main portion P5 of the insulating layer 108, so that the word line (main portion P3) can be electrically connected to other components (such as the contact window CT) through the extension portion P4.

In this embodiment, the insulating wall 104a has a vertical side wall, so that the extension P4 of the conductive layer 110 can extend vertically upward corresponding to the side wall of the insulating wall 104a, but the present invention is not limited to this. In another embodiment, the insulating wall 104a can have an inclined side wall. In other embodiments, the insulating wall can have a stepped profile, so that the extension of the conductive layer 110 can extend upward corresponding to the side wall and top of the step of the insulating wall. This will be described in detail below.

FIG3 is a cross-sectional schematic diagram of the semiconductor structure of the second embodiment of the present invention. In this embodiment, the same components as those of the first embodiment are represented by the same component symbols and will not be described again. In addition, the manufacturing method of the semiconductor structure of the second embodiment is similar to that of the first embodiment, and the difference is only that the profile of the insulating wall is different, so the manufacturing method of the semiconductor structure of the second embodiment will not be described separately.

Referring to FIG. 3 , in the semiconductor structure 30 of the present embodiment, like the insulating wall 104a, the insulating wall 300 is formed on the substrate 100 and surrounds the array region 100a and the step region 100b. The insulating wall 300 has a step profile and includes a plurality of steps 300a. Each step 300a has a top surface TF and a side wall SW, and the top surface TF has a depth d. In FIG. 3 , the number of steps 300a is only exemplary, and the present invention is not limited thereto.

The stacking structure 302 is formed in the array region 100a and the step region 100b, and conformally extends to the step 300a of the insulating wall 300. In this embodiment, the stacking structure 302 includes a stacked insulating layer 106a and a conductive layer 110 and an insulating layer 108.

In the stacked structure 302, in addition to the insulating layer 108 at the top, the insulating layer 106a includes a main body P1 and an extension P2' connected to the main body P1, the conductive layer 110 includes a main body P3 and an extension P4' connected to the main body P3, and the insulating layer 108 at the top includes a main body P5. The end of the extension P2' is connected to the end of the main body P1, and the end of the extension P4' is connected to the end of the main body P3. In addition, in addition to the topmost insulating layer 108 and the topmost conductive layer 110, the extension P2' of the insulating layer 106a includes at least one first portion E1 disposed on the top surface TF of the step 300a and at least one second portion E2 disposed on the side wall SW of the step 300a, the extension P4' of the conductive layer 110 includes at least one first portion E3 disposed on the top surface TF of the step 300a and at least one second portion E4 disposed on the side wall SW of the step 300a, and the extension P4' of the topmost conductive layer 110 includes a second portion E4.

In this embodiment, in the stacked structure 302, the second portion E4 of the topmost conductive layer 110 and the topmost second portions E4 of the remaining conductive layers 110 are exposed by the topmost first portion E1 of the insulating layer 106a and the main body P5 of the topmost insulating layer 108. That is, the top surface of the second portion E4 of the topmost conductive layer 110 and the top surface of the topmost second portion E4 of the remaining conductive layers 110 are coplanar with the top surface of the topmost first portion E1 of the insulating layer 106a and the top surface of the main body P5 of the topmost insulating layer 108, but the present invention is not limited thereto.

In other embodiments, depending on the actual situation, the topmost conductive layer may only include the main body P3 without the extension part, and there is no insulating layer 108, and the main body P3 of the topmost conductive layer 110 and the topmost first part E3 of the remaining conductive layers 110 are exposed by the topmost second part E2 of the insulating layer 106a. In other words, the top surface of the main body P3 of the topmost conductive layer 110 and the top surface of the topmost first part E4 of the remaining conductive layers 110 are coplanar with the top surface of the topmost second part E2 of the insulating layer 106a.

In addition, in the stacked structure 302, the conductive layer 110 has the same thickness t1, and the insulating layer 106a has the same thickness t2. Therefore, the distance between the centers of the second portions E4 of two adjacent conductive layers 110 is the sum of the thickness t1, the thickness t1 and the depth d. In this way, the conductive layers 110 exposed at the top of the stacked structure 302 can have a larger spacing, so that the contact windows CT formed subsequently and connected to the ends of each layer of the conductive layer 110 can have a larger distance, avoiding the bridging problem caused by the distance between the contact windows CT being too close or the position of the contact windows CT being offset.

The semiconductor structure 30 of this embodiment can be applied to a three-dimensional AND flash memory. When the semiconductor structure 30 of this embodiment is applied to a three-dimensional AND flash memory, the required three-dimensional AND flash memory process can be performed to form a channel structure, a support column, a support wall, etc. The semiconductor structure 30 will be used as an example to illustrate these structures.

FIG. 4A and FIG. 4B are respectively top view and cross-sectional schematic diagrams of the semiconductor structure of the third embodiment of the present invention. In this embodiment, the same components as those in the second embodiment will be represented by the same component symbols and will not be described again.

Please refer to FIG. 4A and FIG. 4B at the same time. In the semiconductor structure 40, the support column 400 is disposed on the substrate 100, and penetrates the stacking structure 302 and the conductive layer 102 located below from the insulating layer 108 and the end (the first portion E1 at the top) of the insulating layer 106a. In addition, in addition to penetrating the stacking structure 302 and the conductive layer 102, part of the support column 400 also penetrates the insulating wall 300 below the stacking structure 302. In FIG. 4A, the number and layout of the support column 400 are only exemplary, and the present invention is not limited thereto. The material of the support column 400 includes an insulating material, such as silicon oxide. In addition, depending on actual needs, the support column 400 can also be composed of a conductive column and an insulating material covering the conductive column.

FIG5 is a schematic top view of a semiconductor structure of the fourth embodiment of the present invention. In this embodiment, the same components as those in the third embodiment are represented by the same component symbols and will not be described again.

Please refer to FIG5 , the difference between this embodiment and the third embodiment is that the semiconductor structure 50 further includes a supporting wall 500. The supporting wall 500 is disposed on the substrate 100 and extends in the plane direction of the substrate 100. In addition, the supporting wall 500 penetrates the stacking structure 302, the insulating wall 300 and the conductive layer 102. In FIG5 , the number and layout of the supporting wall 500 are only exemplary, and the present invention is not limited thereto. The material of the supporting wall 500 includes an insulating material, such as silicon oxide. The method for forming the supporting wall 500 is, for example, to form a trench penetrating the initial stacking structure 106 and the insulating wall 300 before the replacement process described in FIG. 1E, and then fill the trench with insulating material.

FIG6 is a schematic top view of a semiconductor structure of the fifth embodiment of the present invention. In this embodiment, the same components as those in the fourth embodiment are represented by the same component symbols and will not be described again.

Please refer to FIG. 6 , the difference between this embodiment and the fourth embodiment is that the semiconductor structure 60 further includes a channel structure 600. The channel structure 600 is disposed in the array region 100a of the substrate 100 and penetrates the stacking structure 302 and the conductive layer 102. In FIG. 6 , the number and layout of the channel structure 600 are only exemplary, and the present invention is not limited thereto. The channel structure 600 may include a channel column, a charge storage layer, a source column, a drain column, etc., which are well known to those skilled in the art and will not be described in detail here.

FIG7 is a schematic top view of a semiconductor structure of the sixth embodiment of the present invention. In this embodiment, the same components as those in the fifth embodiment are represented by the same component symbols and will not be described again.

Please refer to FIG. 7 . The difference between this embodiment and the fifth embodiment is that in the semiconductor structure 60 , the stacking structure 302 has a slit 700 . The slit 700 penetrates the stacking structure 302 and the conductive layer 102 . The slit 700 divides the stacking structure 302 into a plurality of blocks, which is well known to those skilled in the art and will not be described in detail here.

The following describes the circuit structure of the three-dimensional memory array MSC including the semiconductor structure of the present invention.

FIG8 is a circuit diagram of a 3D AND flash memory array including the semiconductor structure of the present embodiment.

8 , two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ of the vertical AND memory array MSC are arranged in columns and rows. Block BLOCK ⁽ⁱ⁾ includes memory array MSC1. One column (e.g., the m+1th column) of memory array MSC1 is a set of AND memory cells MC having a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ). The AND memory cells MC in each column (e.g., the m+1th column) of the memory array MSC1 correspond to a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ) and are coupled to different source pillars (e.g., SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain pillars (e.g., DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cells MC are logically arranged in a row along the common word line (e.g., WL ⁽ⁱ⁾ _m+1 ).

A row (e.g., the nth row) of the memory array MSC1 is a set of AND memory cells MC having a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells MC of each row (e.g., the nth row) of the memory array MSC1 correspond to different word lines (e.g., WL ⁽ⁱ⁾ _m+1 and WL ⁽ⁱ⁾ _m ) and are coupled to a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). Therefore, the AND memory cells MC of the memory array MSC1 are logically arranged in a row along the common source column (e.g., SP ⁽ⁱ⁾ _n ) and the common drain column (e.g., DP ⁽ⁱ⁾ _n ). In the physical layout, depending on the manufacturing method applied, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

In FIG8 , in block BLOCK ⁽ⁱ⁾ , AND memory cells MC in the nth row of memory array MSC1 share a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). AND memory cells MC in the n+1th row share a common source column (e.g., Sp ⁽ⁱ⁾ _n+1 ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n+1 ).

A common source column (e.g., SP ⁽ⁱ⁾ _n ) is coupled to a common source line (e.g., SL _n ); a common drain column (e.g., DP ⁽ⁱ⁾ _n ) is coupled to a common bit line (e.g., BL _n ). A common source column (e.g., SP ⁽ⁱ⁾ _n+1 ) is coupled to a common source line (e.g., SL _n+1 ); a common drain column (e.g., DP ⁽ⁱ⁾ _n+1 ) is coupled to a common bit line (e.g., BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes a memory array MSC2, which is similar to the memory array MSC1 in block BLOCK ⁽ⁱ⁾ . One row (e.g., the m+1th row) of the memory array MSC2 is a set of AND memory cells MC having a common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells MC of each row (e.g., the m+1th row) of the memory array MSC2 correspond to the common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ) and are coupled to different source poles (e.g., SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (e.g., the nth row) of the memory array MSC2 is a set of AND memory cells MC having a common source column (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁺¹⁾ _n ). These AND memory cells MC sets are connected in parallel and are also called memory strings. The AND memory cells MC of each row (e.g., the nth row) of the memory array MSC2 correspond to different word lines (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 and WL ⁽ⁱ⁺¹⁾ _m ) and are coupled to a common source column (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁺¹⁾ _n ). Therefore, the AND memory cells MC of the memory array MSC2 are logically arranged in a row along a common source pole (eg, SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (eg, DP ⁽ⁱ⁺¹⁾ _n ).

Block BLOCK ⁽ⁱ⁺¹⁾ and block BLOCK ⁽ⁱ⁾ share a source line (e.g., SL _n and SL _n+1 ) and a bit line (e.g., BL _n and BL _n+1 ). Therefore, source line SL _n and bit line BL _n are coupled to the n-th row AND memory cell MC in AND memory array MSC1 of block BLOCK ⁽ⁱ⁾ , and are coupled to the n-th row AND memory cell MC in AND memory array MSC2 of block BLOCK ⁽ⁱ⁺¹⁾ . Similarly, source line SLn ₊₁ and bit line BLn ₊₁ are coupled to the n+1th row AND memory cell MC in AND memory array MSC1 of block BLOCK ⁽ⁱ⁾ , and are coupled to the n+1th row AND memory cell MC in AND memory array MSC2 of block BLOCK ⁽ⁱ⁺¹⁾ .

Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

30:Semiconductor structure

100: Base

100a: Array area

100b: Stairway area

102, 110: Conductive layer

106a, 108: Insulating layer

300: Insulation wall

300a:Stairs

302: Stack structure

CT: Contact window

d: depth

E1, E3: Part 1

E2, E4: Part 2

P1, P3, P5: Main body

P2’, P4’: extension part

TF: Top

SW: side wall

t1, t2: thickness

Claims (7)

A semiconductor structure for three-dimensional memory, comprising: a substrate having an array region and a step region surrounding the array region; an insulating wall disposed on the substrate and surrounding the array region and the step region; and a stacking structure disposed on the substrate in the array region and the step region and comprising a plurality of insulating layers and a plurality of conductive layers stacked alternately, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend to the insulating wall, The insulating wall has a stepped profile and includes a plurality of steps, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend onto the plurality of steps, and wherein: each of the plurality of steps includes a top surface and a side wall, each of the plurality of insulating layers and the plurality of conductive layers except the topmost insulating layer includes a main body and an extension connected to the main body, and the topmost insulating layer includes the main body, The extension of each of the plurality of insulating layers and the plurality of conductive layers except the topmost insulating layer and the topmost conductive layer includes at least one first portion and at least one second portion, and the extension of the topmost conductive layer includes one second portion, wherein the first portion is arranged corresponding to the top surface, and the second portion is arranged corresponding to the side wall, and the topmost second portion of each of the conductive layers except the topmost conductive layer and the second portion of the topmost conductive layer are exposed by the topmost first portion of each of the insulating layers except the topmost insulating layer and the main portion of the topmost insulating layer. A semiconductor structure for three-dimensional memory as described in claim 1, wherein: Each of the conductive layers has a first thickness, Each of the insulating layers has a second thickness, The top surface of each of the steps has a depth, and The distance between the centers of the second portions of two adjacent conductive layers is the sum of the first thickness, the second thickness and the depth. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a supporting pillar, which penetrates the stacking structure from the end of the extension portion of the insulating layer and is disposed on the substrate. A semiconductor structure for three-dimensional memory as described in claim 3, wherein the supporting pillar further penetrates the insulating wall. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a supporting wall, which penetrates the stacking structure and the insulating wall and is disposed on the substrate and extends in the plane direction of the substrate. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a plurality of contact windows, each of which is connected to a corresponding end of the conductive layer. A method for manufacturing a semiconductor structure for a three-dimensional memory, comprising: providing a substrate, wherein the substrate has an array region and a step region surrounding the array region; forming an insulating wall surrounding the array region and the step region on the substrate; and forming a stacking structure on the substrate in the array region and the step region, wherein the stacking structure comprises a plurality of insulating layers and a plurality of conductive layers stacked alternately, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend to the insulating wall, The insulating wall has a stepped profile and includes a plurality of steps, wherein the plurality of insulating layers and the plurality of conductive layers conformally extend onto the plurality of steps, and wherein: each of the plurality of steps includes a top surface and a side wall, each of the plurality of insulating layers and the plurality of conductive layers except the topmost insulating layer includes a main body and an extension connected to the main body, and the topmost insulating layer includes the main body, The extension of each of the plurality of insulating layers and the plurality of conductive layers except the topmost insulating layer and the topmost conductive layer includes at least one first portion and at least one second portion, and the extension of the topmost conductive layer includes one second portion, wherein the first portion is arranged corresponding to the top surface, and the second portion is arranged corresponding to the side wall, and the topmost second portion of each of the conductive layers except the topmost conductive layer and the second portion of the topmost conductive layer are exposed by the topmost first portion of each of the insulating layers except the topmost insulating layer and the main portion of the topmost insulating layer.

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