TWI885781B - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes a flexible circuit substrate, a chip and a predetermined sheet attaching area. The flexible circuit substrate includes a flexible base, a patterned metal layer and a solder resist layer. The flexible base has a chip mounting area. The patterned metal layer is disposed on the flexible base and includes a plurality of leads. The leads extend outward from the chip mounting area. The solder resist layer is disposed on the flexible base and has an opening defining the chip mounting area. The solder resist layer partially covers the patterned metal layer and has an alignment slot. The chip is disposed on the flexible circuit substrate and located in the chip mounting area. The chip is electrically connected to the leads. The predetermined sheet attaching area is defined on the flexible circuit substrate, wherein the alignment slot is located within the predetermined sheet attaching area.

Description

Chip-on-film packaging structure

The present invention relates to a packaging structure, and in particular to a chip-on-film packaging structure.

The current chip on film (COF) packaging structure mostly uses the copper foil metal layer used to make the pins to form special identification patterns for alignment during various operations as the basis for alignment. However, as the pin density becomes higher and higher, the space for setting the identification pattern becomes more and more limited, or the flexible circuit substrate uses a dark or opaque (such as black) solder mask to cover the copper foil metal layer covered by the solder mask to meet special needs, making it difficult to clearly identify the copper foil metal layer covered by the solder mask, all of which cause difficulties in alignment identification operations, such as when attaching heat sinks or other patches on the flexible circuit substrate, there is no clearly identifiable identification pattern close to the patch position for alignment.

The present invention provides a film flip chip packaging structure, which is helpful for the alignment identification when the patch is attached, so that the patch can be accurately and quickly attached to the flexible circuit carrier.

The thin film flip chip packaging structure of the present invention includes a flexible circuit carrier, a chip and a patch predetermined attachment area. The flexible circuit carrier includes a flexible substrate, a patterned metal layer and an anti-soldering layer. The flexible substrate has a chip setting area. The patterned metal layer is arranged on the flexible substrate and includes a plurality of pins. These pins extend outward from the chip setting area. The anti-soldering layer is arranged on the flexible substrate and has an opening to define the chip setting area. The anti-soldering layer partially covers the patterned metal layer and has an alignment slot. The chip is arranged on the flexible circuit carrier and is located in the chip setting area. The chip is electrically connected to these pins. The patch predetermined attachment area is defined on the flexible circuit carrier, wherein the alignment slot is located in the patch predetermined attachment area.

Based on the above, in the design of the film flip chip packaging structure of the present invention, the solder mask layer of the flexible circuit carrier has an alignment slot, and the alignment slot is located in the predetermined patch attachment area. When the patch is attached to the flexible circuit carrier, the patch machine can capture the image of the alignment slot as a basis for the patch attachment alignment. Compared with the design of forming the alignment pattern with a patterned metal layer, it is not limited by the layout space, and there is no need to consider whether the alignment pattern can still be clearly identified under the cover of the solder mask layer. In addition, the alignment slot is located in the predetermined patch attachment area, which can reduce the time spent by the patch machine to find the alignment pattern and the actual patch attachment position, so that the patch can be accurately and quickly attached to the flexible circuit carrier.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically described below in detail with reference to the accompanying drawings.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity.

It should be noted that the chip-on-film package structure shown in the following figure is operated in a reel-to-reel transmission manner. Although the heat sink in the following figure is only schematically shown as being applied to a device area on the reel that forms the chip-on-film package structure, the present invention is not limited to this. The heat sink in the following figure can be applied to multiple device areas on the reel at the same time.

FIG. 1 is a schematic top view of a thin film flip chip package structure according to an embodiment of the present invention. Referring to FIG. 1 , in this embodiment, the thin film flip chip package structure 100 includes a flexible circuit carrier 110, a chip 120, and a patch predetermined attachment area 130. The flexible circuit carrier 110 includes a flexible substrate 112, a patterned metal layer 114, and a solder barrier layer 116. The flexible substrate 112 has a chip setting area 113. The patterned metal layer 114 is disposed on the flexible substrate 112 and includes a plurality of pins 115, wherein the pins 115 extend outward from the chip setting area 113. The solder-proof layer 116 is disposed on the flexible substrate 112 and has an opening 117 to define a chip setting area 113. The solder-proof layer 116 partially covers the patterned metal layer 114 and has an alignment slot 119. The chip 120 is disposed on the flexible circuit carrier 110 and is located in the chip setting area 113, and the chip 120 is electrically connected to the pins 115. The chip predetermined attachment area 130 is defined on the flexible circuit carrier 110, wherein the alignment slot 119 is located in the chip predetermined attachment area 130. In other words, the chip predetermined attachment area 130 and the solder-proof layer 116 at least partially overlap. It should be noted that the predetermined patch attachment area 130 is a pre-set attachment area of the FFT chip package structure 100 when a patch is added thereon in response to various needs.

Specifically, in the present embodiment, the material of the flexible substrate 112 is, for example, polyethylene terephthalate, polyimide, polyethersulfone, polycarbonate or other suitable flexible materials. The pins 115 and the solder-proof layer 116 are disposed on the same surface of the flexible substrate 112, wherein the solder-proof layer 116 partially covers the pins 115 to prevent the pins 115 from being damaged or short-circuited by foreign matter. The portions of the pins 115 exposed by the solder-proof layer 116 can be used to electrically connect to the chip 120 or external components. The solder-proof layer 116 is a dark material or an opaque material, such as black solder-proof ink, which is not limited here. The chip 120 may be configured in the chip setting area 113 by flip-chip method, and electrically connected to the pins 115 located in the chip setting area 113 through, for example, bumps (not shown). In addition, the film flip chip package structure 100 of this embodiment may further include a packaging gel 140, which is filled between the chip 120 and the flexible circuit carrier 110, and covers the chip setting area 113 and the four side walls S of the chip 120 to protect the electrical contacts between the chip 120 and the flexible circuit carrier 110. In this embodiment, the packaging gel 140 is, for example, an underfill.

Furthermore, in the present embodiment, the chip setting area 113 is located within the patch predetermined attachment area 130, but not limited thereto. That is to say, the range of the patch predetermined attachment area 130 covers the chip setting area 113, so the patch can cover the chip 120 when it is set on the flexible circuit carrier 110. Here, the alignment slot 119 of the anti-soldering layer 116 is located outside the projection range of the packaging glue 140 on the flexible circuit carrier 110. That is to say, the packaging glue 140 will not cover the alignment slot 119 of the anti-soldering layer 116. In one example, the area of the alignment slot 119 can be, for example, greater than or equal to 1.5 mm x 1.5 mm, which is conducive to the chip placement machine to capture the image of the alignment slot 119.

Furthermore, the flexible substrate 112 of the present embodiment has a circuit blank area A, the patterned metal layer 114 is not disposed in the circuit blank area A, and the alignment slot 119 corresponds to the circuit blank area A. In other words, the flexible circuit carrier 110 of the present embodiment sets the alignment slot 119 at a position where no patterned metal layer 114 is distributed, so as to prevent the patterned metal layer 114 from being damaged or contaminated at the alignment slot 119 due to lack of protection of the solder-proof layer 116. In a top view, the shape of the alignment slot 119 may be, for example, a rectangle, a rhombus, a polygon, a triangle, a circle, or an ellipse, but is not limited thereto.

The film flip chip package structure 100 of the present embodiment forms an alignment slot 119 on the solder mask 116 of the flexible circuit carrier 110 within the range of the predetermined chip attachment area 130, which serves as an alignment reference when the chip is attached to the flexible circuit carrier 110. Therefore, when the patterned metal layer 114 cannot be provided with an alignment pattern due to circuit configuration restrictions, or when the patterned metal layer 114 cannot be clearly identified because the solder mask 116 is a dark material or an opaque material, the chip mounting machine can perform the alignment operation when the chip is attached through the alignment slot 119 of the solder mask 116. In addition, the alignment slot 119 is located in the predetermined patch attachment area 130, which can reduce the time consumed by the image capture device of the patch machine to find the alignment reference pattern and the actual patch attachment position, so that the patch can be accurately and quickly attached to the flexible circuit carrier 110.

FIG2 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. FIG3 is a schematic diagram of an identification pattern connected to a pin according to an embodiment of the present invention. Please refer to FIG1 and FIG2 at the same time. The chip-on-film packaging structure 100a of this embodiment is similar to the aforementioned embodiment. The difference between the two is that the patterned metal layer 114a of the flexible circuit carrier 110a of this embodiment further includes an identification pattern R, wherein the identification pattern R is located in the alignment slot 119a. Furthermore, the alignment slot 119a may be offset from the central position of the patch attachment area 130. For example, the alignment slot 119a of this embodiment is located near a corner of the packaging gel 140, but is not limited thereto. Here, the identification pattern R is separated from the boundary of the alignment slot 119a by a distance D, that is, the identification pattern R is an independent pattern. In this embodiment, the identification pattern R may be a dummy pattern. In another embodiment, please refer to FIG. 3 , the identification pattern R’ may also be connected to the pin 115, that is, the identification pattern R’ may be a specific pattern formed by a part of the pin 115, which still falls within the scope of protection of the present invention. Therefore, in addition to performing the alignment operation during chip attachment through the alignment slot 119a, the patch machine may also achieve the same purpose through the identification patterns R and R’ exposed by the alignment slot 119a.

In addition, the chip-on-film package structure 100a of this embodiment further includes a patch 132, which is disposed in the patch attachment area 130 and can be, for example, a heat sink patch, a structural reinforcement patch, or an electromagnetic shielding patch. In this embodiment, the patch 132 is a heat sink patch, which corresponds to the chip setting area 113 and covers the chip 120 to directly help the chip 120 dissipate heat. Furthermore, the heat sink patch 132 may include a heat sink layer 132a, an insulating protective layer 132b, and an adhesive layer (not shown). The heat dissipation layer 132a is attached to the chip 120 and the flexible circuit carrier 110a through an adhesive layer, and the insulation protection layer 132b is formed on the heat dissipation layer 132a through another adhesive layer or coating to protect the heat dissipation layer 132a from damage. The material of the heat dissipation layer 132a may include metal foil or graphite film, wherein the metal foil is, for example, aluminum foil or copper foil, but the present invention is not limited thereto. The material of the insulation protection layer 132b is, for example, polyimide, but the present invention is not limited thereto.

In summary, in the design of the film flip chip package structure of the present invention, the solder mask layer of the flexible circuit substrate has an alignment slot, and the alignment slot is located in the predetermined patch attachment area. When the patch is attached to the flexible circuit substrate, the patch machine can capture the image of the alignment slot as a basis for the patch attachment alignment. Compared with the design of forming an alignment pattern with a patterned metal layer, it is not limited by the layout space, and there is no need to consider whether the alignment pattern can still be clearly identified under the cover of the solder mask. In addition, the alignment slots are located in the predetermined patch attachment area, which can reduce the time spent by the patch machine to find the alignment pattern and the actual patch attachment position, so that the patch can be accurately and quickly attached to the flexible circuit carrier.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100, 100a: Film flip chip packaging structure 110, 110a: Flexible circuit carrier 112: Flexible substrate 113: Chip setting area 114, 114a: Patterned metal layer 115: Pins 116: Anti-soldering layer 117: Opening 119, 119a: Alignment slot 120: Chip 130: SMD pre-attachment area 132: SMD 132a: Heat dissipation layer 132b: Insulation protection layer 140: Packaging glue A: Circuit blank area D: Distance R, R’: Identification pattern S: Side wall

FIG. 1 is a schematic top view of a thin film chip-on-chip packaging structure according to an embodiment of the present invention. FIG. 2 is a schematic top view of a thin film chip-on-chip packaging structure according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an identification pattern connected to a pin according to an embodiment of the present invention.

100: Thin film chip packaging structure

110: Flexible circuit board

112: Flexible substrate

113: Chip setting area

114: Patterned metal layer

115: Pins

116: Anti-welding layer

117: Open your mouth

119: Alignment slot

120: Chip

130: Patch attachment area

140: Packaging colloid

A: Line blank area

S: side wall

Claims (10)

A film flip chip packaging structure includes: A flexible circuit carrier, including: A flexible substrate having a chip setting area; A patterned metal layer, arranged on the flexible substrate and including a plurality of pins, the pins extending outward from the chip setting area; and A solder-proof layer, arranged on the flexible substrate and having an opening to define the chip setting area, the solder-proof layer partially covering the patterned metal layer and having an alignment slot; A chip, arranged on the flexible circuit carrier and located in the chip setting area, the chip being electrically connected to the pins; and A patch predetermined attachment area, defined on the flexible circuit carrier, wherein the alignment slot is located in the patch predetermined attachment area. The film flip chip packaging structure as described in claim 1 further includes: A packaging colloid filled between the chip and the flexible circuit carrier and covering the chip setting area and the four side walls of the chip. A chip-on-film packaging structure as described in claim 2, wherein the chip setting area is located in the predetermined patch attachment area, and the alignment slot is located outside the projection range of the packaging colloid on the flexible circuit carrier. The chip-on-film package structure as described in claim 1, wherein the flexible substrate has a circuit blank area, the patterned metal layer is not arranged in the circuit blank area, and the alignment slot corresponds to the circuit blank area. The chip-on-film package structure as described in claim 1, wherein the patterned metal layer further includes an identification pattern, and the identification pattern is located in the alignment slot. A chip-on-film package structure as described in claim 5, wherein the identification pattern is spaced a distance from a boundary of the alignment slot. In the chip-on-film package structure as described in claim 1, the alignment slot has a shape including a rectangle, a diamond, a polygon, a triangle, a circle or an ellipse when viewed from above. In the chip-on-film package structure as described in claim 1, the solder mask is made of a dark material or an opaque material. A chip-on-film package structure as described in claim 1, wherein the area of the alignment slot is greater than or equal to 1.5 mm×1.5 mm. The chip-on-film packaging structure as described in claim 1 further includes a patch arranged in the predetermined attachment area of the patch, and the patch includes a heat dissipation patch, a structural reinforcement patch or an electromagnetic shielding patch.

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