200427116 九、發明說明： 【發明所屬之技術領域】 本發明係屬於一種適用於1C積體電路及發光二極體之 封裝方法’尤指一種可降低封裝成本並可廣泛應用於1C積 體電路與發光二極體之封裝方法。 【先前技術】 今曰的半導體技術已廣泛應用於人們生活週遭的各種 電子設備之中’舉凡個人電腦、行動電話及自動提款機等 等’皆包含有以半導體等技術所製造而成的電路板或其他 電子元件。 5月參照弟五及第六圖，係一般傳統的半導體積體電路 (ic，Integrated Circuit )或發光二極體（led，Light200427116 IX. Description of the invention: [Technical field to which the invention belongs] The present invention belongs to a packaging method suitable for 1C integrated circuits and light-emitting diodes', especially a method that can reduce packaging costs and can be widely used in 1C integrated circuits and Packaging method of light emitting diode. [Previous technology] Today ’s semiconductor technology has been widely used in various electronic devices around people ’s lives. “For example, personal computers, mobile phones, ATMs, etc.” all include circuits made with semiconductors and other technologies. Board or other electronic component. In May, referring to the fifth and sixth figures, it is a general traditional semiconductor integrated circuit (ic, Integrated Circuit) or light emitting diode (led, Light)
Em i 11 i ng D i ode )的封裝流程，其係在一金屬導線架（g 〇 ) (6 0 a )(或銅箔基板）上設置一晶片（7 〇 )(俗稱 固晶）或發光二極體晶粒（7 〇 a )，接著在晶片（7 〇 ) 或晶粒（7〇a)與導線架（6◦) (6〇a)上的針腳 (61) (61a)(或是銅箔基板上的銲點）之間打上 =線（2 1 ) ’最後在晶片（7 〇 )或晶粒（7 〇 :)與 銲線（2 1 )的外部封上一層封膠（7 2 ) w J ^ ( c a ) ? 即完成封裝程序。 凊參照第七至第九圖，關於積體電路 々及& , 種封裝万 式係為俗稱的覆晶封裝，其流程係為在一曰 面形成數個金屬凸塊（8 1 ) 晶片（8 Π〉蚀盆a思π % , ;血丄、二，一 日日片(8 〇 )表Em i 11 i ng D i ode) packaging process, which is based on a metal lead frame (g 0) (60a) (or copper foil substrate) set a wafer (70) (commonly known as solid crystal) or light Diode die (70a) followed by pins (61) (61a) on the wafer (70) or die (70a) and leadframe (6◦) (60a) (or A = line (2 1) is marked between the solder joints on the copper foil substrate. 'Finally, a layer of sealant (7 2) is sealed on the outside of the wafer (70) or the die (70 :) and the bonding wire (2 1). ) w J ^ (ca)? The encapsulation process is completed.凊 Refer to the seventh to ninth diagrams, for integrated circuits 々 and &, a package type is commonly known as flip-chip packaging, and the process is to form a number of metal bumps (8 1) chip ( 8 Π> eclipse a think π%,;
下而定位在一導線 (8 0 )使其金屬凸塊（丨 200427116 ::了路基板（9 0 ) / ( 9 〇 a )上相對應的數個針腳 (9 1 ) /銲點上，最後在該晶片（8 〇 )的外部封上一 層封膠（ 9 5 ) ( 9 5 a);前述的覆晶封裝方式可以避 免因打線而造成晶片電感、阻抗或其散熱性的降低，且 對第-種封裝方式可降低成本並提高良率；但覆晶封裝方 式仍具有數項如下的缺點： 1 .金屬凸塊一般係以金或錫鉛合金製造而成，盆形 成於晶片上的製程冗長且複雜，一般為配合此項製程:、廠 商必須額外另料業生產線且購置專用的製程設備。 ^ ·晶片係由矽晶圓切割製造而成，其結構脆弱，故 其上设置金屬凸塊時仍有損毁該晶片的可能性，某些類型 的2片更因為體積過小或厚度過薄而根本無法將金屬凸塊 固疋於其上’故習用覆晶封裝方式的實用性仍有不足。 【發明内容】 、故本發明人根據習用積體電路及發光二極體之封裝方 =的高成本及低應用性等缺m其不足與缺失，進而 t明出一種適用於積體電路及發光二極體之封裝方法。 i月之主要目的係提供一種適用積體電路及發光二 Z等導電主體之封I方法，可免除在積體電路之上形成 龙的複雜製私而達到成本的降低’並可廣泛應用於 種積體電路及發光二極體的封裝而提高封裝製程的實用 性。 托-為達上述目的’本發明係提供-種適用晶片及發光二 組之封裝方法，其包含有以下流程： 200427116 以一金屬基板作為製程基板，並於該基板上設置一線 路； 在金屬基板上線路表面形成數個金屬凸塊； 在各金屬凸塊外塗佈金屬結合劑； 將一導電主體粒設置在金屬凸塊上； 在違導電主體外部密封上一封膠或透明膠,· 姓刻金屬基板底部以形成底部接腳； 於金屬基板底部非接腳部分塗佈防焊油墨； 若需要E S D保護之元件則另加電阻保護； 對線路線進行測試； 藉由上述技術手段，本發明可免除在導電主體之上形 成金屬凸塊的複雜製程而達到成本的降低，並可廣泛應用 於各種導電主體的封裝而提高封裝方法的實用性。 $述在金屬基板上设置線路的方法係為钱刻該金屬基 板頂面，於金屬基板上受蝕刻後的凹陷處以高分子介電材 料填平’非受蝕刻處則形成線路； 前述的導電主體係為一積體電路晶片。 前述的導電主體係為一發光二極體晶粒。 前述導電主體設置於基板上後，在導電主體底部與金 屬基板頂部之間灌一底層封膠（Underfill)。 前述基板底部的接腳形成之後，於接腳上塗佈一鎳/金 層0 '、 ，則述的鎳/金層形成後，於金屬基板上形成有一可避免 逆電流或瞬間靜電的線路保護電阻。 200427116 藉由上述技術手段’本發明的 積體電路或發光二極體的封裴， L 於各類 免逆電流或瞬間靜電而以達 隻軍阻此有效避 之增進。 相積體電路或發光二極體壽命 【實施方式】 請參照第一圖， 法係包含有下列流程 本發明一種適用於積體電路之封裝方 以-銅材料製成的金屬基板（i ◦)作為製程基板（言主 參閱第一圖A所示）； 月 蝕刻該金屬基板（i 〇 )頂部，該金屬基板（工〇 ) 上又蝕刻後的凹陷處以一高分子介電材料（丄丄）填平， 非受蝕刻處則形成線路（請參照第一圖6所示）； 以電鍍或印刷的方式，該金屬基板（i 〇 )上線路表 面形成數個金屬凸塊（12)(請參照第一圖C所示）； 在各金屬凸塊（1 2 )外塗佈一以銀漿或錫膏所製成 的金屬結合劑（1 3 )(請參照第一圖D所示）； 在金屬凸塊（21)上設置一可為晶片（ic)或發 光二極體（L E D )晶粒的導電主體（1 5 )，其中導電 主體（1 5 )上的數個金屬接點（1 5 1 )係分別相對應 於各金屬凸塊（2 1)上，接著於導電主體（1 5)底部 與金屬基板（1 0 )頂部之間填充一底層封膠（；[6 ) (Underfill )以增加導電主體（1 5)及金屬基板（1 〇) 之間結構的穩固性（請參照第二圖E所示）； 在該導電主體（1 5 )外部密封上一封膠（1 7 )，若 200427116 ”亥導電主體（5 1 )為一發光二極體晶粒時，則該封膠（工 7 )頊為透明狀（請參照第二圖F所示）； 餘刻該金屬基板（1 0 )底部以形成數個底部接腳（1 〇 1 )(請參照第三圖G所示）； 於該金屬基板（1 〇)底部的接腳（1 〇 1)上塗佈 一鎳/金層（18)，接著在該金屬基板（1〇)底部的 部y刀接腳（1 0 1 )處形成有一可避免逆電流或瞬間靜電 的線路保護電阻（19)，並接著在該金屬基板（1〇) 的非接腳（1 〇 1 )部分塗佈一防焊油墨（2 〇 )(請參 照第三圖Η所示）； 對線路進行測試。 别述適用積體電路之封裝方法亦可適用於發光二極體 之封裝。 藉由上述技術手段，本發明可增進下列功效： 1 ·免除在積體電路或發光二極體之上形成金屬凸塊 的複雜製程，廠商不須額外開闢生產線或購置專用的製程 設備，如此而達到積體電路或發光二極體封裝成本的降低。 2本叙明的封裝方法因不須直接對積體電路或發光 二極體晶粒等導電主體實施可能傷害該導電主體的措施， 故較脆弱的晶片或晶粒結構也可利用本發明來進行封裝流 私，如此可達到於廣泛應用於各類型積體電路或發光二極 體的封裝而提高封裝方法的實用性。 【圖式簡單說明】 第一圖Α〜D係為本發明之部分流程圖。 200427116It is positioned on a wire (80) with its metal bumps (丨 200427116 :: the circuit board (90) / (90a)) on the corresponding pins (91) / solder joints, and finally Seal a layer of sealant (95) (95a) on the outside of the chip (80); the aforementioned flip-chip packaging method can avoid the reduction of chip inductance, impedance or heat dissipation due to wire bonding, and -A variety of packaging methods can reduce costs and improve yield; however, flip-chip packaging methods still have several disadvantages as follows: 1. Metal bumps are generally made of gold or tin-lead alloy, and the process of forming the basin on the wafer is lengthy. It is complicated. Generally, in order to cooperate with this process: Manufacturers must separately manufacture additional production lines and purchase special process equipment. ^ · Wafers are manufactured by cutting silicon wafers, and their structures are fragile, so when metal bumps are placed on them There is still the possibility of damaging the wafer, and some types of 2 wafers are not able to hold metal bumps at all because they are too small or too thin. Therefore, the practicality of the conventional flip-chip packaging method is still insufficient. Summary of the invention] Therefore, the inventor The encapsulation method of the body circuit and the light-emitting diode = high cost and low applicability; its shortcomings and shortcomings, and furthermore, a packaging method suitable for the integrated circuit and the light-emitting diode is revealed. The main purpose of the month It provides a sealing method suitable for integrated circuits such as integrated circuits and light-emitting diodes Z, which can avoid the complex manufacturing of dragons on integrated circuits and reduce costs. It can be widely used in integrated circuits and light emitting Packaging of diodes improves the practicability of the packaging process. To-in order to achieve the above-mentioned purpose, the present invention provides a packaging method suitable for two sets of wafers and light emitting diodes, which includes the following processes: 200427116 A metal substrate is used as a process substrate And a circuit is provided on the substrate; a plurality of metal bumps are formed on the surface of the circuit on the metal substrate; a metal bonding agent is coated on each metal bump; a conductive body particle is arranged on the metal bump; Seal the outside of the main body with a piece of glue or transparent glue, and the bottom of the metal substrate is engraved to form the bottom pins. Apply the solder mask to the non-pin portion of the bottom of the metal substrate. If ESD protection is required The components are additionally protected by resistance; the line is tested; by the above technical means, the present invention can avoid the complicated process of forming metal bumps on the conductive body and achieve cost reduction, and can be widely used in various conductive bodies Encapsulation improves the practicability of the packaging method. The method for setting a circuit on a metal substrate is to engrav the top surface of the metal substrate, and fill the non-received portion of the metal substrate with the polymer dielectric material after being etched. A line is formed at the etching place; the aforementioned conductive main system is an integrated circuit wafer. The aforementioned conductive main system is a light-emitting diode die. After the conductive body is disposed on the substrate, the conductive body is disposed on the bottom of the conductive body and on the top of the metal substrate. Fill an underfill in between. After the pins at the bottom of the substrate are formed, a nickel / gold layer 0 ′, is coated on the pins. After the nickel / gold layer is formed, a circuit protection can be formed on the metal substrate to prevent reverse current or instantaneous static electricity. resistance. 200427116 By the above technical means, the integrated circuit or light-emitting diode of the present invention, L is free from reverse current or instantaneous static electricity in order to prevent this from being effectively avoided. Phase integrated circuit or light-emitting diode lifetime [Embodiment] Please refer to the first figure. The method includes the following process. A metal substrate (i ◦) made of -copper material suitable for integrated circuit packaging is used in the present invention. As the process substrate (refer to the first picture shown in Figure A); the top of the metal substrate (i 〇) is etched, and a high-molecular dielectric material (（) is etched into the recess on the metal substrate (work 〇). Fill in, and form a circuit in the unetched area (refer to the first figure 6); by plating or printing, a number of metal bumps (12) are formed on the surface of the circuit on the metal substrate (i 〇) (please refer to (Shown in the first figure C); coating a metal bonding agent (1 3) made of silver paste or solder paste on each of the metal bumps (12) (see the first picture D); A conductive body (1 5), which can be a wafer (ic) or a light emitting diode (LED) die, is disposed on the metal bump (21), wherein a plurality of metal contacts (1 5) on the conductive body (1 5) 1) Corresponding to each metal bump (2 1), then the bottom of the conductive body (1 5) and the metal base (1 0) A bottom sealant (; [6) (Underfill) is filled between the tops to increase the structural stability between the conductive body (15) and the metal substrate (10) (please refer to the second figure E) ); A sealant (17) is sealed on the outside of the conductive body (1 5). If 200427116 "Hai conductive body (5 1) is a light-emitting diode grain, the sealant (7)" Is transparent (please refer to the second figure F); at the bottom of the metal substrate (1 0) to form a number of bottom pins (100) (see the third figure G); A nickel / gold layer (18) is coated on the pins (100) at the bottom of the substrate (10), and then a knife blade (1 0 1) at the bottom of the metal substrate (10) is formed. A circuit protection resistor (19) that can avoid reverse current or instantaneous static electricity, and then apply a solder resist ink (20) to the non-pin (100) portion of the metal substrate (10) (refer to the third (Shown in Figure Η); Test the circuit. Not to mention the packaging method applicable to integrated circuits can also be applied to the packaging of light emitting diodes. By the above technical means, the present invention can The following effects are achieved: 1 · Eliminate the complicated process of forming metal bumps on integrated circuits or light-emitting diodes. Manufacturers do not need to open additional production lines or purchase special process equipment to achieve integrated circuits or light-emitting diodes. Reduction in packaging costs. 2 The packaging method described in this chapter does not require direct implementation of measures that may damage the conductive body, such as integrated circuits or light-emitting diode chips, so fragile chips or die structures can also be used. The invention is used for package flow privately, so that it can be widely used in the packaging of various types of integrated circuits or light-emitting diodes to improve the practicability of the packaging method. [Brief description of the drawings] The first drawings A to D are part of the flowchart of the present invention. 200427116
第二圖E F係為本發明接續第 程圖 圖内流程之部分 第三圖g〜h係為本發明接續第二圖㈣程之部八 Ϊ ° 77 第四圖係為本發明完成各流程後的平面剖視圖。 第五圖係為習用積體電路封裝的平面視圖。 第六圖係為習用發光二極體封裝的平面視圖。 第七圖係為習料體電路與金屬凸塊的平面視圖。 第八圓係為習用覆晶型積體電路封裝的平面視圖。 第九圖係4習料晶型積體電路封裝的平φ示意圖。 主 1 ( ( ( ( ( 6 677 8 9 要元件符號說明】 〇)金屬基板 （ιοί)接腳 1 )高分子介電材料（1 2 )金屬凸塊 3 )金屬結合劑 （1 5 )導電主體 5 1 )金屬接點 （1 6 )底層封膠 7 )封膠 （1 8 )鎳/金 線路保護電阻（2 0 )防焊油墨 0 )導線架 1 )針腳 0 ) 2 ) 〇 ) 〇 ) Β曰 片 封膠 晶片t 導線架 (6 0 a )導線架(6 1 a )針腳 (7 〇 a )晶粒(7 2 a )封膠 (8 1 )金屬凸塊 (9◦a)晶片 200427116The second picture EF is a part of the flow chart in the diagram following the second process of the present invention. The third picture g ~ h is the part of the process of the second process following the second diagram of the present invention. ° 77 The fourth picture is after the processes of the present invention are completed. Plan view. The fifth figure is a plan view of a conventional integrated circuit package. The sixth figure is a plan view of a conventional light emitting diode package. The seventh diagram is a plan view of the circuit of the material body and the metal bump. The eighth circle is a plan view of a conventional flip-chip integrated circuit package. The ninth figure is a flat φ schematic diagram of a 4 crystal integrated circuit package. Main 1 (((((6 677 8 9 key component symbol description) 〇) metal substrate (ιοί) pin 1) polymer dielectric material (1 2) metal bump 3) metal bond (1 5) conductive body 5 1) Metal contacts (1 6) Bottom sealant 7) Sealant (1 8) Nickel / gold circuit protection resistor (2 0) Solder masking ink 0) Lead frame 1) Pin 0) 2) 〇) 〇) Β Chip sealant chip t lead frame (6 0 a) lead frame (6 1 a) pins (7 〇a) die (7 2 a) sealant (8 1) metal bump (9a) wafer 200427116