TWI881731B - Substrate package structure - Google Patents

Abstract

A substrate package structure is provided by embodiments of this disclosure, including a first substrate, a metal wiring layer, a solder bump and a second substrate. The metal wiring layer is disposed over the first substrate, and the metal wiring layer includes a dielectric layer over the first substrate, a conductive structure in the dielectric layer, anchoring components in the dielectric layer and surrounding the conductive structure and top pad on the conductive structure. Additionally, a top surface of the first top pad is higher than a top surface of the dielectric layer. The solder bump is disposed on the metal wiring layer. The second substrate is disposed on the solder bump.

Description

Substrate packaging structure

The present disclosure relates to a substrate packaging structure.

As the manufacturing technology of integrated circuits (ICs) continues to improve, the requirements for packaging processes are also increasing. However, during the thermal cycle of the packaging process, the dielectric layer is easily deformed due to thermal expansion and contraction, which in turn causes the circuit layer in the dielectric layer to shift or even break. In view of this, how to improve the problem of dielectric layer deformation and the displacement or breakage of the circuit layer in the dielectric layer has become a development focus in related fields.

The disclosed embodiment provides a substrate packaging structure, including a first substrate, a metal wiring layer, a solder bump and a second substrate. The metal wiring layer is disposed above the first substrate and includes a dielectric layer disposed above the first substrate, a conductive structure disposed in the dielectric layer, an anchoring component disposed in the dielectric layer and located around the conductive structure, and a top solder pad disposed on the conductive structure, and the top surface of the top solder pad is higher than the top surface of the dielectric layer. The solder bump is disposed on the metal wiring layer. The second substrate is disposed on the solder bump.

The disclosed embodiment provides a substrate packaging structure, including a first substrate, a metal wiring layer, a solder bump and a second substrate. The first substrate is defined as a chip area and a non-chip area. The metal wiring layer is disposed above the first substrate and includes a dielectric layer disposed above the first substrate, a conductive structure disposed in the dielectric layer, a first inner filling portion disposed in the dielectric layer and located around the conductive structure, a second inner filling portion disposed in the dielectric layer and located in the non-chip area and adjacent to the conductive structure, and a top solder pad disposed on the dielectric layer and located on the conductive structure. In addition, the distribution density of the first inner filling portion located in the chip area is greater than the distribution density of the second inner filling portion located in the non-chip area. The top surface of the top solder pad is higher than the top surface of the dielectric layer. The welding bumps are respectively arranged on the top welding pads. The second substrate is arranged on the welding bumps and is located in the chip area.

The following will clearly illustrate the spirit of the present invention with drawings and detailed descriptions. After understanding the preferred embodiments of the present invention, any person having ordinary knowledge in the relevant technical field can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

The exemplary terms "below" or "beneath" may include both "above" and "above". The terms "include", "includes", "have", "contain", etc. used in this document are all open terms, which means including but not limited to.

In the redistribution layer (RDL) (or metal wiring layer) formed in the back-end process, since the coefficient of thermal expansion (CTE) of the dielectric layer material of the RDL (e.g., polyimide (PI)) is usually much larger than the CTE of the metal material, the dielectric layer will expand significantly in the process with large temperature changes or extreme temperatures, which will cause uneven stress and metal material fracture, and even damage to the wires or pads. Accordingly, the embodiment of the present disclosure improves the structural stability of the metal wiring layer by providing anchor components.

Please refer to Figures 1 to 3D, Figures 1 and 2 are cross-sectional views of some stages in the manufacturing process of the substrate packaging structure according to some embodiments of the present disclosure, and Figures 3A to 3D are top views of the relative positional relationship between the anchoring component and the conductive structure according to some embodiments of the present disclosure. As shown in Figure 1, the substrate 110 of the substrate packaging structure 100 (such as Figure 6) defines a chip area 102 and a non-chip area 104. An isolation layer 120 is set on the substrate 110. In some embodiments, the material forming the isolation layer 120 includes resin and glue. Then, a dielectric layer 130 is formed on the isolation layer 120. In some embodiments, the material forming the dielectric layer 130 includes polyimide (PI). In some embodiments, the thickness of the dielectric layer 130 is 5 to 200 micrometers (µm). Subsequently, a power layer 140 is formed on the isolation layer 120 and is located in the dielectric layer 130. In some embodiments, a diameter R1 of the power layer 140 is 100 to 1000 µm.

Furthermore, at least one conductive opening 144 and a plurality of anchor openings 146 formed around the conductive opening 144 are formed in the dielectric layer 130 by laser drilling technology, wherein the conductive opening 144 exposes the top surface of the power layer 140, and the anchor opening 146 closest to the conductive opening 144 is separated from the conductive opening 144 by a first distance D1 or a second distance D2. Moreover, the first distance D1, for example, refers to the distance from the center of the first conductive opening 144A to the middle of the first anchor opening 146A closest to the first conductive opening 144A, and the second distance D2, for example, refers to the distance from the center of the first conductive opening 144A to the middle of the first anchor opening 146A of another first conductive opening 144A. In some embodiments, the conductive opening 144 is located in the chip region 102. In some embodiments, the diameter R2 of the conductive opening 144 (such as shown in FIG. 3A) is 10 to 50 μm. In some embodiments, the diameter R3 of the anchoring opening 146 (such as shown in FIG. 3A) is 10 to 50 μm. In some embodiments, the first distance D1 is less than or equal to the second distance D2.

Taking FIG. 1 as an example, a first conductive opening 144A, a second conductive opening 144B, and a third conductive opening 144C (collectively referred to as conductive openings 144) and a plurality of first anchor openings 146A, second anchor openings 146B, and third anchor openings 146C (collectively referred to as anchor openings 146) are formed in the dielectric layer 130. The first conductive opening 144A is located between the second conductive opening 144B and the third conductive opening 144C, and the first conductive opening 144A is separated from the second conductive opening 144B and the third conductive opening 144C by a distance.

The first anchor opening 146A is located around the first conductive opening 144A. The second anchor opening 146B is located around the second conductive opening 144B, and the second anchor opening 146B and the second conductive opening 144B are separated from the first conductive opening 144A. The third anchor opening 146C is located around the third conductive opening 144C. Similarly, the third anchor opening 146C and the third conductive opening 144C are separated from the first conductive opening 144A. In some embodiments, the angle θ is 15 to 30 degrees.

As shown in the dotted enlarged box in FIG. 1 , in some embodiments, after drilling by laser drilling technology, a roughening process is performed on the inner surface of a portion of the second anchor opening 146B and a portion of the third anchor opening 146C, so that a plurality of depressions 147 are generated on the inner surface of a portion of the second anchor opening 146B and a portion of the third anchor opening 146c. In some embodiments, the diameter of the depression 147 is 10 to 200 nanometers (nm). In some embodiments, the depth of the depression 147 is 1 to 50 nm.

As shown in FIG. 2 , a metal material is filled in the conductive opening 144 and the anchor opening 146 (as shown in FIG. 1 ) to form conductive structures 152 (e.g., first conductive structures 152A, second conductive structures 152B, and third conductive structures 152C) and anchoring components 154 (e.g., first anchoring components 154A, second anchoring components 154B, and third anchoring components 154C), respectively. In some embodiments, the metal material is copper (Cu). In addition, as shown in the dotted enlarged box in Figure 2, in an embodiment in which the surface of the second anchor opening 146B and a portion of the third anchor opening 146C has a recess 147 (as shown in Figure 1), after the second anchor opening 146B and a portion of the third anchor opening 146C are filled with metal material, an internal roughening structure 157 is formed in the recess 147, and the internal roughening structure 157 can increase the bonding force of the side of the anchor component 154 in the dielectric layer 130.

Next, a top pad 156 (e.g., a first top pad 156A on the first conductive structure 152A, a second top pad 156B on the second conductive structure 152B, and a third top pad 156C on the third conductive structure 152C) is formed on the conductive structure 152. Moreover, the top surface of the top pad 156 is higher than the top surface of the dielectric layer 130. In this way, a metal wiring layer 150 is formed above the substrate 110. In some embodiments, the diameter R4 of the top pad 156 is 100 to 1000 μm.

Further, please refer to Figures 3A to 3D. Depending on the process requirements, the anchoring component 154 and the conductive structure 152 can be designed into different layouts. For example, as shown in Figure 3A, the anchoring component 154 and the conductive structure 152 can be designed into a cross-shaped layout, wherein the top pad 156 is circular. Or for example, as shown in Figure 3B, the anchoring component 154 and the conductive structure 152 can be designed into a concentric circle layout, wherein the top pad 156 is circular. For another example, as shown in Figure 3C, the anchoring component 154 and the conductive structure 152 can be designed into a matrix layout, wherein the top pad 156 is circular. For another example, as shown in FIG. 3D , the anchoring member 154 and the conductive structure 152 may be designed as a matrix layout, wherein the top pad 156 is rectangular, and the length L of the rectangular top pad 156 is 100 to 1000 μm, and the width W of the rectangular top pad 156 is 100 to 1000 μm. In some embodiments, when the diameter R4, length L, or width W of the top pad is less than 200 μm, a cross layout or a concentric circle layout is used; when the diameter R4, length L, or width W of the top pad 156 is greater than 200 μm, a matrix layout is used. Different numbers of anchoring components 154 are provided according to the size of the top pad 156, thereby adjusting the proportion of metal material and improving the degree to which the conductive structure 152 is affected by stress.

Next, please refer to Figures 4A to 4G, which are cross-sectional views of various embodiments of the anchoring component located on the metal wiring layer according to the present disclosure. It is worth mentioning that the following description uses relative terms, such as "lower" or "bottom" and "upper" or "top", to describe the relationship between one element and another element shown in the accompanying drawings. It is understandable that relative terms are used to describe different orientations of the device other than those described in the accompanying drawings, and are not used to limit the present disclosure. That is, if the device in the accompanying drawings is turned over, the element that will be described as being located on the "lower" side of other elements will be oriented to be located on the "upper" side of other elements, and so on. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations according to the specific orientation of the accompanying drawings.

As shown in the embodiment of FIG. 4A , the metal wiring layer 150 includes a dielectric layer 130, and includes a power layer 140 located in the dielectric layer 130, a conductive structure 152 located on the power layer 140, an anchor pad 158 located on the conductive structure 152, and a top pad 156 located on the anchor pad 158. In this embodiment, the anchor pad 158 completely covers the upper portion of the conductive structure 152, and the top surface of the anchor pad 158 is coplanar with the top surface of the dielectric layer 130. Furthermore, the bottom surface of the top pad 156 contacts the top surface of the anchor pad 158, and the top surface of the top pad 156 is higher than the top surface of the dielectric layer 130. In some embodiments, the diameter R4 of the top pad is smaller than the diameter R5 of the anchor pad. Through this embodiment, the contact area of the anchor pad 158 on the dielectric layer 130 can be increased, thereby improving the structural stability.

As shown in the embodiment of FIG. 4B , the metal wiring layer 150 includes a dielectric layer 130, and includes a power layer 140 located in the dielectric layer 130, a conductive structure 152 located on the power layer 140, an anchoring component 154 located around the conductive structure 152 and spaced apart from each other, an anchoring pad 158 located on the anchoring component 154 and the conductive structure 152, and a top pad 156 located on the anchoring pad 158. In some embodiments, the diameter R5 of the anchoring pad 158 is greater than the diameter R1 of the power layer 140, and the diameter R5 of the anchoring pad 158 is greater than the diameter R4 of the top pad 156.

As shown in FIG. 4C , the metal wiring layer 150 includes a first dielectric layer 130A and a second dielectric layer 130B located on the first dielectric layer 130A, and includes a first power layer 140A located in the first dielectric layer 130A and a circuit structure 162 located in the first power layer 140A, a second power layer 140B located in the second dielectric layer 130B and located on the circuit structure 162, a conductive structure 152 located on the second power layer 140B, and a plurality of anchoring components 154 located around the conductive structure 152. In addition, a top pad 156 is located on the second dielectric layer 130B. In this embodiment, the bottom of the anchoring member 154 contacts the top surface of the second power layer 140B, but in other embodiments, the bottom of the anchoring member 154 may not contact the top surface of the second power layer 140B, that is, the height of the anchoring member 154 is different from the height of the conductive structure 152.

As shown in the embodiment of FIG. 4D , the metal wiring layer 150 includes a first dielectric layer 130A and a second dielectric layer 130B located on the first dielectric layer 130A, and includes a power layer 140 located in the first dielectric layer 130A, a lower conductive structure 152L located on the power layer 140, a plurality of lower anchoring components 154L surrounding the lower conductive structure 152L, a lower top pad 156L located in the second dielectric layer 130B and located on the lower conductive structure 152L, an upper conductive structure 152U located on the lower top pad 156L, and an upper anchoring component 154U located around the upper conductive structure 152U. Furthermore, the upper top pad 156U is disposed on the second dielectric layer 130B. In this embodiment, the bottom of the lower anchoring member 154L does not contact the top surface of the power layer 140, that is, the height of the lower anchoring member 154L is different from the height of the lower conductive structure 152L. In this embodiment, the bottom of the upper anchoring member 154U contacts the top surface of the lower top pad 156L. However, in other embodiments, the bottom of the upper anchoring member 154U may not contact the top surface of the lower top pad 156L.

As shown in FIG. 4E , the metal wiring layer 150 includes a first dielectric layer 130A and a second dielectric layer 130B located on the first dielectric layer 130A, and includes a power layer 140 located on the first dielectric layer 130A, a conductive structure 152 located on the power layer 140, and an anchoring component 154 located around the conductive structure 152. In addition, a top pad 156 is disposed on the second dielectric layer 130B. In this embodiment, there is an angle θ between the anchoring component 154 and the conductive structure 152. In some embodiments, the angle θ is 15 to 30 degrees. In this embodiment, the bottom of the anchoring member 154 contacts the top surface of the power layer 140, but in other embodiments, the bottom of the anchoring member 154 may not contact the top surface of the power layer 140.

As shown in the embodiment of FIG. 4F , the metal wiring layer 150 includes a first dielectric layer 130A and a second dielectric layer 130B located on the first dielectric layer 130A, and includes a power layer 140 located in the first dielectric layer 130A, a lower conductive structure 152L located on the power layer 140, a lower anchoring component 154L located around the lower conductive structure 152L, a lower top pad 156L located in the second dielectric layer 130B and located on the lower conductive structure 152L, an upper conductive structure 152U disposed on the lower top pad 156L, and an upper anchoring component 154U located around the upper conductive structure 152U. Furthermore, the upper top pad 156U is disposed on the second dielectric layer 130B. In this embodiment, the bottom of the lower anchoring member 154L does not contact the top surface of the power layer 140, but in other embodiments, the bottom of the lower anchoring member 154L may contact the top surface of the power layer 140. In this embodiment, the upper anchoring member 154U has an angle θ with the upper conductive structure 152U. In some embodiments, the angle θ is 15 to 30 degrees. In some embodiments, the bottom of the upper anchoring member 154U contacts the top surface of the lower top pad 156L. In some embodiments, the bottom of the upper anchoring member 154U does not contact the top surface of the lower top pad 156L.

As shown in FIG. 4G , in an embodiment of a ground layer, the metal wiring layer 150 includes a first dielectric layer 130A, a second dielectric layer 130B located on the first dielectric layer 130A, and a third dielectric layer 130C located on the second dielectric layer 130B, and includes a lower anchoring member 154L located at an upper portion of the first dielectric layer 130A, a lower anchoring member 154L located at a lower portion of the second dielectric layer 130C, and a lower anchoring member 154L located at a lower portion of the second dielectric layer 130A. 0B and located on the lower anchoring component 154L, the conductive structure 152 disposed on the power layer 140, the middle anchoring component 154M disposed around the conductive structure 152, the middle top pad 156M disposed in the third dielectric layer 130C and located on the conductive structure 152, and the wiring structure 162 disposed on the middle top pad 156M. In addition, the upper top pad 156U is disposed on the third dielectric layer 130C. In this embodiment, the plurality of middle anchoring components 154M are not equidistant from the conductive structure 152, and the bottom of the middle anchoring component 154M contacts the top surface of the power layer 140.

By providing anchoring components 154, anchoring pads 158 or a combination thereof in the metal wiring layer 150, the stability of the substrate package structure 100 (as shown in FIG. 6) is improved. In addition, anchoring components 154 and/or anchoring pads 158 of different structures can be provided in each dielectric layer 130 to increase the proportion of metal material (e.g., Cu) in each dielectric layer 130 (e.g., PI) of the metal wiring layer 150, thereby dispersing the stress effect of the conductive structure 152 caused by excessive difference in coefficient of thermal expansion (CTE).

In addition, in order to solve the problem of uneven stress caused by large differences in the coefficient of thermal expansion (CTE) of components within the metal wiring layer 150, the embodiment of the present disclosure further provides an inner filling portion and a filling layer that can absorb stress.

Please refer to Figures 5 to 7, Figures 5 and 6 are cross-sectional views of various stages of the manufacturing process of the substrate packaging structure according to some embodiments of the present disclosure, and Figure 7 is a top view of the relative position relationship between the welding bump and the internal filling member according to some embodiments of the present disclosure.

As shown in FIG. 5 , a plurality of openings OP are formed in the dielectric layer 130, and the openings OP are basically located around the conductive structure 152. Furthermore, according to requirements (e.g., circuit layout), openings OP may also be formed in the dielectric layer 130 in the non-chip region 104. In some embodiments, the dielectric layer 130 includes a dry film photoresist. In this embodiment, the openings OP are formed in the dielectric layer 130 by a laser drilling process, and the laser axis may be adjusted to change the shape of the drilling hole to form the openings OP, such as forming the openings OP into a cylindrical or conical shape. In other embodiments, the dielectric layer 130 includes a liquid photoresist. In this embodiment, the opening pattern is defined by a photoresist mask, and after the liquid photoresist is cured, an etching process is performed to form the opening OP, and then the photoresist mask is removed. It is worth mentioning that in the embodiment of FIG. 5, the opening OP is first formed in the dielectric layer 130, and then the solder bump 170 is set, but in some other embodiments, the solder bump 170 can also be set on the first top solder pad 156A, the second top solder pad 156B and the third top solder pad 156C, and then the opening OP is formed in the dielectric layer 130, and the present disclosure is not limited to this.

Next, as shown in FIG. 6 , solder bumps 170 are disposed on the top solder pads 156 , that is, solder bumps 170 are disposed on the first top solder pad 156A, the second top solder pad 156B, and the third top solder pad 156C, respectively. In some embodiments, the solder bumps 170 are solder balls. Subsequently, the filling material is filled into the opening OP (as shown in FIG. 5 ) in the dielectric layer 130 to form an inner filling portion 182, and the filling material is filled on the dielectric layer 130 of the chip area 102 and covers the solder bump 170 and the first top solder pad 156A, the second top solder pad 156B and the third top solder pad 156C to form a filling layer 184, wherein the top of the inner filling portion 182 located in the chip area 102 is connected to the bottom surface of the filling layer 184. Then, another substrate 190 is disposed on the solder bump 170. In some embodiments, the substrate 190 includes an integrated circuit element substrate and a chip substrate. In some other embodiments, the substrate 190 includes a substrate including an integrated circuit and a substrate including a chip. In some embodiments, substrate 190 is an integrated circuit or a chip. In some embodiments, the filling material includes a polymer, a liquid epoxy, or a combination thereof.

In some embodiments, the glass transition temperature (Tg) of the filler material is 100°C. In some embodiments, when the operating temperature is lower than the glass transition temperature of the filler material, the coefficient of thermal expansion (CTE) of the filler material is between 20 and 60 ppm. Therefore, when the operating temperature of the inner filler 182 and the filler layer 184 is lower than the glass transition temperature (e.g., 100°C), the coefficient of thermal expansion (CTE) of the inner filler 182 and the filler layer 184 is lower, which can reduce the overall expansion of the metal wiring layer 150, thereby reducing the stress caused by the mismatch of the coefficient of thermal expansion (CTE) of each component in the metal wiring layer 150.

In some embodiments, when the operating temperature is higher than the glass transition temperature of the filling material, the Young's modulus of the filling material is between 0.01 and 1 GPa. Therefore, when the operating temperature of the inner filling part 182 and the filling layer 184 is higher than the glass transition temperature (e.g., 100° C.), the inner filling part 182 and the filling layer 184 have a softer texture and can absorb the stress in the metal wiring layer 150. Accordingly, by providing different numbers and/or shapes of inner filling parts 182 in the dielectric layer 130, and mainly providing the inner filling parts 182 around the conductive structure 152 where stress is concentrated, the stress generated by the excessive difference in the coefficient of thermal expansion (CTE) can be effectively absorbed.

Further, as shown in FIG. 7 , the distribution density of the inner filling portion 182 disposed in the chip region 102 is greater than the distribution density of the inner filling portion 182 disposed in the non-chip region 104, wherein the distribution density of the inner filling portion 182 can be designed according to the coefficient of thermal expansion (CTE) of the dielectric layer 130 and the coefficient of thermal expansion (CTE) of the conductive structure 152 (as shown in FIG. 6 ). As mentioned above, the opening OP in the chip region 102 is substantially disposed around the conductive structure 152 (as shown in FIG. 5 ), and the solder bump 170 is located above the conductive structure 152. Therefore, after the inner filling portion 182 is formed, the inner filling portion 182 in the chip region 102 is substantially located around the solder bump 170.

Next, please refer to FIG. 8A and FIG. 8B, which are cross-sectional views of other embodiments of the inner filling portion of the substrate packaging structure disclosed herein. As previously mentioned, the shape of the drill hole can be changed by adjusting the laser axis to form openings of different shapes. Therefore, the inner filling portion 182 can be formed into a cone as shown in FIG. 8A and FIG. 8B. In addition, in FIG. 8B, the isolation layer 120 also has a pattern, for example, a cone is formed in the direction toward the substrate 190, and the inner filling portion 182 forms a cone in the direction toward the substrate 110, so that the top of the pattern of the isolation layer 120 is in contact with the bottom of the inner filling portion 182.

Please refer to FIG. 9, which is a cross-sectional view of a substrate package structure according to some other embodiments of the present disclosure. The layout of the metal wiring layer 150 of the embodiment of the substrate package structure 200 of FIG. 9 is different from that of the embodiment of FIG. 6. The metal wiring layer 250 of the substrate package structure 200 of FIG. 9 is described in detail below.

Similarly, the metal wiring layer 250 is disposed on the isolation layer 120. The metal wiring layer 250 includes a first dielectric layer 230A and a second dielectric layer 230B. Furthermore, the metal wiring layer 250 includes a first dielectric layer 230A disposed on the isolation layer 120, a first power layer 240A disposed in the first dielectric layer 230A in the chip region 102 and located on the isolation layer 120, a second power layer 240B disposed in the non-chip region 104 and located in the first dielectric layer 230A and located on the isolation layer 120, a first wiring structure 262A disposed in the first dielectric layer 230A and connected to the first power layer 240A, and a second wiring structure 262A disposed in the first dielectric layer 230A and connected to the second power layer 240B. 2B, a plurality of first inner filling portions 182 disposed in the first dielectric layer 230A and located around the first circuit structure 262A and the second circuit structure 262B, a connection layer 244 disposed in the second dielectric layer 230B and located on the first dielectric layer 230A, a plurality of conductive structures 152 disposed in the second dielectric layer 230B and disposed on the connection layer 244 at a distance therefrom, a plurality of anchoring components 154 disposed in the second dielectric layer 230B and located around the conductive structure 152, and a plurality of top solder pads 156 disposed on the conductive structure 152.

Furthermore, the conductive structure 152 includes a second conductive structure 152B, a third conductive structure 152C, and a first conductive structure 152A located between the second conductive structure 152B and the third conductive structure 152C. In some embodiments, the first conductive structure 152A is substantially located in the middle portion of the chip region 102, and the second conductive structure 152B and the third conductive structure 152C are substantially located at the side portion of the chip region 102. Although FIG. 9 shows that the two first conductive structures 152A are located between the second conductive structure 152B and the third conductive structure 152C, this is only exemplary, and the circuit layout design is not limited thereto.

In addition, the anchoring member 154 includes a first anchoring member 154A surrounding the first conductive structure 152A, a second anchoring member 154B surrounding the second conductive structure 152B, and a third anchoring member 154C surrounding the third conductive structure 152C. In some embodiments, the second anchoring member 154B away from the portion of the first conductive structure 152A has an angle θ with the second conductive structure 152B. In some embodiments, the third anchoring member 154C away from the portion of the first conductive structure 152A has an angle θ with the third conductive structure 152C. In some embodiments, the angle θ is 15 to 30 degrees.

In addition, as shown in FIG. 9 , different numbers and/or shapes of inner filling portions 182 are provided between different dielectric layers (e.g., the first dielectric layer 230A and the second dielectric layer 230B), and the inner filling portions 182 are mainly provided around the circuit structures (e.g., the first circuit structure 262A and the second circuit structure 262B) and the conductive structure 152 where stress is concentrated. Furthermore, the distribution density of the inner filling portion 182 disposed in the chip area 102 (i.e., the overall distribution density of the inner filling portion 182 disposed in the first dielectric layer 230A and the second dielectric layer 230B) is greater than the distribution density of the inner filling portion 182 located in the non-chip area 104, so as to effectively absorb the stress generated by the excessive difference in the coefficient of thermal expansion (CTE) and reduce the damage occurrence rate of the substrate packaging structure.

Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100, 200               : Substrate packaging structure 102                     : Chip area 104                     : Non-chip area 110, 190               : Substrate 120                     : Isolation layer 130                     : Dielectric layer 130A, 230A           : First dielectric layer 130B, 230B           : Second dielectric layer 130C                   : Third dielectric layer 140                     : Power layer 140A, 240A           : First power layer 140B, 240B           : Second power layer 144                     : Conductive opening 144A                   : First conductive opening 144B                     : Second conductive opening 144C                   : Third conductive opening 146                     : Anchor opening 146A                   : First anchor opening 146B                     : Second anchor opening 146C                     : Third anchor opening 147                     : Recess 150, 250                 : Metal wiring layer 152                     : Conductive structure 152A                   : First conductive structure 152B                   : Second conductive structure 152C                   : Third conductive structure 152L                   : Lower conductive structure 152U                   : Upper conductive structure 154                     : Anchoring member 154A                   : First anchoring member 154B                   : Second anchoring member 154C                     : Third anchoring member 154L                     : Lower anchoring member 154M                     : Middle anchoring member 154U                     : Upper anchoring member 156                     : Top solder pad 156A                   : First top solder pad 156B                   : Second top pad 156C                   : Third top pad 156L                     : Lower top pad 156M                   : Middle top pad 156U                   : Upper top pad 157                     : Internal roughening structure 158                     : Anchor pad 162                     : Circuit structure 170                     : Solder bump 182                     : Internal filling part 184                     : Filling layer 244                         : Connection layer 262A                       : First line structure 262B                       : Second line structure D1                         : First distance D2                          : Second distance OP                          : Opening L                            : Length R1, R2, R3, R4, R5  : Diameter W                         : Width θ                            : Angle

In order to make the purpose, features, advantages and embodiments of the present invention more clearly understandable, the detailed description of the attached figures is as follows: Figures 1 and 2 are cross-sectional views of some stages in the manufacturing process of the substrate packaging structure according to some embodiments of the present disclosure; Figures 3A to 3D are top views of the relative position relationship between the anchoring component and the conductive structure according to some embodiments of the present disclosure; Figures 4A to 4G are cross-sectional views of the anchoring component according to various embodiments of the present disclosure; Figures 5 and 6 are cross-sectional views of some stages in the manufacturing process of the substrate packaging structure according to some embodiments of the present disclosure; Figure 7 is a top view of the relative position relationship between the welding bump and the internal filling member according to some embodiments of the present disclosure; Figures 8A and 8B are cross-sectional views of the inner filling portion of the substrate packaging structure according to some other embodiments of the present disclosure; and Figure 9 is a cross-sectional view of the substrate packaging structure according to some other embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Substrate packaging structure

102: Chip area

104: Non-chip area

110,190: Substrate

120: Isolation layer

130: Dielectric layer

140: Power layer

150: Metal wiring layer

152: Conductive structure

152A: First conductive structure

152B: Second conductive structure

152C: The third conductive structure

154: Anchoring parts

154A: First anchoring component

154B: Second anchoring component

154C: Third anchoring component

156: Top welding pad

156A: First top pad

156B: Second top pad

156C: Third top pad

170: Welding bumps

182: Internal filling part

184: Filling layer

Claims (11)

A substrate packaging structure includes: a first substrate; a metal wiring layer disposed above the first substrate and including; a dielectric layer disposed on the first substrate; a first conductive structure disposed in the dielectric layer; a plurality of first anchoring components disposed in the dielectric layer and located around the first conductive structure; and a first top solder pad disposed on the first conductive structure, wherein the top surface of the first top solder pad is higher than the top surface of the dielectric layer; a solder bump disposed on the metal wiring layer; and a second substrate disposed on the solder bump. The substrate packaging structure as described in claim 1 further includes: an inner filling portion disposed in the dielectric layer and around the first conductive structure; and a filling layer disposed between the metal wiring layer and the second substrate and covering the solder bump and the first top solder pad. The substrate packaging structure as described in claim 1, wherein the metal wiring layer includes: a second conductive structure disposed in the dielectric layer and separated from the first conductive structure by a distance; a plurality of second anchoring components disposed in the dielectric layer and located around the second conductive structure, wherein the second anchoring components away from the first conductive structure have an angle with the second conductive structure; and a second top solder pad disposed on the second conductive structure, wherein the top surface of the second top solder pad is higher than the top surface of the dielectric layer. A substrate packaging structure as described in claim 1, wherein the first anchoring components include a plurality of internal roughening structures. A substrate packaging structure as described in claim 3, wherein the angle is 15 to 30 degrees. The substrate packaging structure as described in claim 1, wherein the metal wiring layer includes: A power layer located in the dielectric layer and connected to the first anchoring components. The substrate packaging structure as described in claim 1 further includes: An anchor pad disposed between the first conductive structure and the top pad. A substrate packaging structure as described in claim 7, wherein the top surface of the anchor pad is coplanar with the top surface of the dielectric layer. A substrate packaging structure, comprising: A first substrate, defining a chip area and a non-chip area; A metal wiring layer, disposed above the first substrate, and comprising: A dielectric layer, disposed above the first substrate; A plurality of conductive structures, disposed in the dielectric layer; A plurality of anchoring components, disposed in the dielectric layer and located around each of the conductive structures; A plurality of first inner filling parts, disposed in the dielectric layer and located around each of the conductive structures; A second inner filling part, disposed in the dielectric layer and located in the non-chip area and adjacent to each of the conductive structures, wherein the distribution density of the first inner filling parts located in the chip area is greater than the distribution density of the second inner filling parts located in the non-chip area; and A plurality of top solder pads are disposed on the dielectric layer and located on each of the conductive structures, wherein the top surface of each of the top solder pads is higher than the top surface of the dielectric layer; A plurality of solder bumps are respectively disposed on the top solder pads; and A second substrate is disposed on the solder bumps and located in the chip area. The substrate packaging structure as described in claim 9 further includes: An isolation layer disposed above the first substrate and between the metal wiring layer. A substrate packaging structure as described in claim 10, wherein the isolation layer has a pattern and contacts the bottom of each of the first inner filling part and the second inner filling part located in the dielectric layer through the top of the pattern.

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