TWI418007B - Flip chip package substrate - Google Patents

Description

Flip chip package substrate

The present invention relates to a package substrate, and more particularly to a flip chip package substrate having a three-dimensional solder resist structure and a package member using the flip chip package substrate.

In today's packaging technology, high-efficiency electronic components typically use solder balls or solder bumps to achieve electrical and mechanical connections between each other. For example, very large scale integration (VLSI) is a solder bump that is connected to a package substrate. This connection technique is called flip-chip (FC). Flip chip bonding is an area array bonding and can therefore be applied to very high density package wiring processes.

To put it simply, the concept of flip-chip bonding is to first form solder bumps on the pads of the IC wafer, then place the IC wafer on the package substrate and complete the bonding of the pads, and then heat-treat the reflow. In combination with the surface tension effect of solder melting, the solder is balled, thereby completing the bonding of the IC chip and the package substrate. This method not only breaks through the limitation of the number of traditional wire bonding technologies, but also is suitable for multi-pin component packaging, and the electrical performance is greatly improved by having a short interconnect.

In detail, in addition to bonding the IC wafer to the package substrate by solder bump heat treatment, the IC wafer and the package substrate are further filled with a filler to make the bonding stronger, wherein the filler material can be dioxide. A composite material such as tantalum or epoxy resin is filled between the IC wafer and the package substrate by the principle of capillary phenomenon. However, the above prior art has a drawback in that the filler often cannot maintain a sufficient bonding force with the package substrate, resulting in a problem of reliability such as delamination or gap between the IC wafer and the package substrate.

In the related prior art, Taiwan Patent No. I309467 "Base strip and substrate structure and method of manufacturing the same" proposes a method of fabricating a substrate structure having an identification mark, mainly forming a hole in the solder resist layer as an identification substrate. In addition, a vacant pattern or a protective metal layer is required under the hole. However, for identification by personnel, the identification mark formed by such a hole must be provided with the area around the substrate, and thus does not contribute to solving the problems of the prior art described above.

The invention provides a flip chip package substrate and a package member formed by using the flip chip package substrate. The solder resist layer having a three-dimensional structure can increase the contact area between the filler and the solder resist layer, thereby making the flip chip package substrate and the wafer close. Engage.

The invention provides a flip chip package substrate comprising at least one patterned circuit layer and a solder resist layer. The patterned circuit layer is located at one end surface of the flip chip package substrate, and the solder resist layer covers the patterned circuit layer, wherein the solder resist layer is provided with a plurality of recessed trenches, thereby increasing the solder resist layer and a primer The binding force of the filler.

The invention provides a package member, comprising a flip chip package substrate, comprising at least one patterned circuit layer, located at an end surface of the flip chip package substrate: a solder resist layer covering the patterned circuit layer; and a plurality of recesses a trench disposed on an upper surface of the solder resist layer; a wafer disposed on the end surface; and a primer filler between the wafer and the solder resist layer, wherein the underfill filler contacts the plurality of recessed trenches .

Based on the above, the present invention provides a flip chip package substrate and a package member using the flip chip package substrate, wherein the flip chip package substrate has a recessed trench on the upper surface of the solder resist layer to increase the underfill filler and the solder resist layer. The contact area is such that the underfill filler and the solder resist layer are sufficiently bonded, so that the wafer and the flip chip package substrate can be tightly bonded.

1 is a schematic cross-sectional view of a flip chip package substrate (taking a four-layer board as an example) according to a preferred embodiment of the present invention. As shown in FIG. 1 , the flip chip package substrate 100 includes a core substrate 110 , a first inner patterned circuit layer 120 a , a second inner patterned circuit layer 120 b , and a first dielectric . a layer 130a, a second dielectric layer 130b, a first surface patterned circuit layer 140a, a second surface patterned circuit layer 140b, a first solder resist layer 150a, a second solder resist layer 150b, The first solder resist layer 150a has at least one three-dimensional structure 160 of the upper surface S3 and at least one recessed trench 170. In detail, the first inner layer patterned circuit layer 120a and the second inner layer patterned circuit layer 120b are respectively located on opposite surfaces of the core substrate 110, and the core substrate 110 has at least one conductive via 110a to be electrically The first inner layer wiring pattern 120a and the second inner layer wiring pattern 120b are connected, wherein the core substrate 110 may be a glass fiber prepreg insulating material, but is not limited thereto. The first inner layer wiring pattern 120a and the second inner layer wiring pattern 120b may include a conductive material such as copper. The conductive vias 110a can be formed by various methods such as laser drilling, mechanical drilling, or lithography.

The first dielectric layer 130a and the second dielectric layer 130b cover the first inner layer wiring pattern 120a and the second inner layer wiring pattern 120b, respectively. According to a preferred embodiment of the present invention, the material of the first dielectric layer 130a and the second dielectric layer 130b may be, for example, Ajinomoto Bond Film (ABF), but may be other insulating materials. The first surface patterned wiring layer 140a and the second surface patterned wiring layer 140b are respectively located on the surfaces of the first dielectric layer 130a and the second dielectric layer 130b.

On one end surface S1 of the flip chip package substrate 100, the first solder resist layer 150a covers the first dielectric layer 130a and the first surface patterned circuit layer 140a, and is formed on one end surface S2 of the flip chip substrate 100. The solder layer 150b covers the second dielectric layer 130b and the second surface patterned circuit pattern layer 140b, wherein, in the packaging process, the end surface S1 is used to connect a wafer, and the end surface S2 is used to connect a printed circuit board ( PCB). The first solder resist layer 150a has at least one first solder resist opening 180a to expose a first solder pad pattern 190a of the first surface patterned wiring layer 140a, so that the first solder pad pattern 190a can be combined with the bump by the bump Wafers (not shown) are bonded. The second solder resist layer 150b has at least one second solder resist opening 180b to expose a second solder pad pattern 190b of the second surface patterned wiring layer 140b, so that the second solder pad pattern 190b can be coupled with the solder ball by a solder ball PCB (not shown) is bonded.

In the present embodiment, the first solder resist layer 150a and the second solder resist layer 150b are formed of an epoxy resin, wherein the epoxy resin may contain a photosensitive resin component, so that the first solder resist layer 150a and the first The two solder resist layers 150b are exposed and developed, and the first solder resist opening 180a and the second solder resist opening 180b are etched. In other embodiments, the first solder resist layer 150a and the second solder resist layer 150b may also be formed of ABF resin or fiber prepreg, but the invention is not limited thereto. In addition, in the embodiment, only the four-layer board is taken as an example, the first inner layer patterned circuit layer 120a and the second inner layer patterned circuit layer 120b and the first dielectric included on opposite surfaces of the core substrate 110. The layer 130a and the second dielectric layer 130b and the first surface patterned wiring layer 140a and the second surface patterned wiring layer 140b. In other embodiments, the substrate structure of the circuit pattern and the dielectric layer of two or more layers (for example, a six-layer board or an eight-layer board, etc.) may be included, and the invention is not limited thereto.

The main technical feature of the present invention is that the upper surface S3 of the first solder resist layer 150a has a plurality of three-dimensional structures 160 and a plurality of recessed trenches 170, wherein the three-dimensional structure 160 is defined by the recessed trenches 170. These three-dimensional structures 160 and recessed trenches 170 can increase the surface area of the upper surface S3, thereby improving the bonding force between the solder resist layer and the underfill filler. The end face S1 of the flip chip package substrate 100 includes a die bond region A1 and a peripheral region A2, and the die bond region A1 serves as a region bonded to a wafer (not shown), which is located below the wafer, and the peripheral region A2 is It is a region other than the wafer bonding region A1 and can be used as a region where other electronic components (for example, capacitors or the like) are bonded. In accordance with a preferred embodiment of the present invention, the relief structure 160 is disposed only within the wafer bond area A1. The purpose of the three-dimensional structure 160 is to increase the contact area of the underfill filler with the first solder resist 150a, thereby improving the bonding force of the underfill to the first solder resist 150a, thereby enabling the wafer and the A solder resist layer 150a can be closely bonded, so that the three-dimensional structure 160 of the present invention only needs to be disposed in the wafer bonding region A1. Of course, in addition to the three-dimensional structure 160 disposed in the wafer bonding area A1, the present invention does not exclude the simultaneous arrangement of the three-dimensional structure 160 in a region other than the wafer bonding area A1, for example, the wafer bonding area A1 and the peripheral area A2 have a three-dimensional structure. 160.

As shown in FIG. 2A and FIG. 2B , the recessed trench 170 may be a rectangular grooved trench having a rectangular cross section and parallel to each other, so that the three-dimensional structure 160 is a plurality of island-shaped structures having a rectangular cross section ( FIG. 2A ). . Alternatively, the recessed trench 170 may be a plurality of linear recessed trenches having a rectangular cross section that are staggered in a longitudinal direction and a lateral direction, so that the three-dimensional structure 160 is formed as a plurality of square bump structures independent of each other (FIG. 2B), but the present invention does not This is limited to this. Of course, the cross section of the recessed trench 170 is not necessarily rectangular. As shown in FIG. 3A-3C and referring to FIG. 1 at the same time, the recessed trench 170 can be a wedge-shaped recessed trench 170a (FIG. 3A) and an arcuate recess. Ditch 170b (Fig. 3B) or a stepped groove ditch 170c (Fig. 3C). The groove trench 170 can be formed, for example, by mechanical drilling, lithography, laser drilling, or the like. In detail, the wedge groove trench 170a may be formed by mechanical or laser drilling, the stepped groove trench 170c may be formed by lithography or etching, and the curved groove trench 170b may be formed, for example, by laser drilling.

For example, the first solder resist opening 180a may be ablated with a laser beam to expose the first solder pad pattern 190a, and then the laser beam of a smaller energy density is applied to the first solder resist layer 150a. The upper surface S3 ablate the groove trench 170b to define the three-dimensional structure 160, but the invention is not limited thereto. In one embodiment, the recessed trenches 170 have a depth between 0.5 and 15 microns and a width between 5 and 200 microns. Preferably, the recessed trenches 170 have a depth between 1 and 5 microns. Between, and the width is between 10 and 80 microns.

Of course, if the first solder resist layer 150a includes a photosensitive resin component, the first solder resist opening 180a and the recess trench 130 may be simultaneously defined by an exposure and development method, but it should be noted that the recessed trench 170 can be smaller than The first solder resist opening 180a is limited to a depth of between 1 and 5 micrometers, wherein the corresponding mask opening of the recessed trench 170 is smaller than the exposure capability limit of the lithography machine. For example, in the case where the size of the solder resist opening of the exposure limit is 80 micrometers, the width of the recessed trench 170 is usually 40 micrometers or less.

4 is a cross-sectional view of a package member in accordance with a preferred embodiment of the present invention. The package member 200 includes a wafer 210, the above-mentioned flip chip package substrate 100, and a primer filler 220. The base filler 220 may be made of a composite material such as ruthenium dioxide or epoxy resin. It is fixed to the flip chip package substrate 100. The wafer 210 has a plurality of first solder balls 220a for alignment bonding with the corresponding first solder pad patterns 190a on the flip chip substrate 100 to electrically connect the wafer 210 and the flip chip substrate 100, but to make the wafer The 210 and the flip chip package substrate 100 can be closely bonded, and the underfill filler 220 needs to be filled into the gap between the wafer 210 and the flip chip package substrate 100. In detail, the end surface S1 of the flip chip package substrate 100 includes a wafer bonding region A1 and a peripheral region A2, and the wafer bonding region A1 serves as a region bonded to the wafer 210, which is directly under the wafer 210, and the peripheral region A2 is It is a region other than the wafer bonding region A1 and can be used as a region where other electronic components (for example, capacitors or the like) are bonded. The underfill filler 220 is located between the wafer 210 and the first solder resist layer 150a, and the underfill filler 220 directly contacts the solid structure 160. Further, in the present embodiment, the three-dimensional structure 160 is provided only in the wafer bonding region A1. Because the purpose of the three-dimensional structure 160 is to increase the contact area between the underfill filler 220 and the first solder resist layer 150a, the bonding force of the underfill filler 220 to the first solder resist layer 150a can be improved, thereby enabling the wafer. The 210 is in close contact with the first solder resist layer 150a, so that the three-dimensional structure 160 of the present invention only needs to be disposed in the wafer bonding region A1. Of course, in addition to the three-dimensional structure 160 disposed in the wafer bonding area A1, the present invention does not exclude the simultaneous arrangement of the three-dimensional structure 160 in a region other than the wafer bonding area A1, for example, the wafer bonding area A1 and the peripheral area A2 have a three-dimensional structure. 160.

In addition, the underfill filler 220 fills the recessed trench 170 to maximize the contact area of the underfill filler 220 with the first solder resist layer 150a, and the underfill filler 220 is closely attached to the first solder resist 150a. Hehe. In a preferred embodiment, the primer filler 220 fills the recessed trench 170 to the recessed trench 170 without bubbles or holes (not shown) to avoid reliability problems, so that the present invention can be most effectively achieved. The purpose of the wafer 210 and the flip chip package substrate 100 are tightly bonded. In addition, the flip chip package substrate 100 further includes a plurality of second solder balls 220b on the circuit board (PCB) end surface S2 to electrically connect the PCB (not shown). The detailed components and their processes are known in the art, so they are not in the field. This statement.

In order to more clearly disclose the structure of the present invention, FIG. 5 is a top view of the package member according to a preferred embodiment of the present invention, and FIG. 6 is a partially enlarged view of the package member of FIG. Referring to Fig. 5, the package member 200' includes a package substrate 100' having a wafer bonding area A1' and a peripheral peripheral area A2' of its periphery, and a wafer 210' is located on the wafer bonding area A1'. The package substrate 100' includes a plurality of recessed trenches 170' and a plurality of first solder pad patterns 190a', and the arrangement of the recessed trenches 170' and the first solder pad patterns 190a' is in the embodiment, as shown in FIG. 6A. The recessed trench 170' and the first solder pad pattern 190a' are, for example, concentric circular cross-sectional structures, and the recessed trenches 170 vertically correspond to the periphery of the first solder pad pattern 190a'. However, in another embodiment, the recessed trench and the first solder pad pattern may be arranged in a manner as shown in FIG. 6B, the first solder pad pattern 190a' has a circular cross-sectional structure, and the recessed trench 170' is interlaced with a plurality of The long groove is formed, and the first pad pattern 190a' is disposed in the square defined by the recessed trench 170'. Of course, in other embodiments, the package substrate, the wafer, the recessed trench, and the first solder pad pattern may be configured in other manners, and the invention is not limited thereto. For example, in Fig. 6A, the recessed trench 170' surrounding the first solder pad pattern 190a' is not limited to a single turn but may have a plurality of turns.

In the above, the present invention provides a flip chip package substrate and a package member using the flip chip package substrate, wherein the flip chip package substrate has a plurality of recessed trenches and a three-dimensional structure on the upper surface of the first solder resist layer. The underfill filler filled between the wafer and the flip chip substrate can have a larger contact area with the first solder resist layer to increase the bonding force of the underfill to the first solder resist layer, thereby enabling the wafer to The flip chip package substrate can be tightly bonded.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Flip chip package substrate

110. . . Core substrate

110a. . . Conductive through hole

120a. . . First inner patterned circuit layer

120b. . . Second inner patterned circuit layer

130a. . . First dielectric layer

130b. . . Second dielectric layer

140a. . . First surface patterned circuit layer

140b. . . Second surface patterned circuit layer

150a. . . First solder mask

150b. . . Second solder mask

160. . . Three-dimensional structure

170, 170’. . . Depressed trench

170a. . . Wedge groove

170b. . . Curved groove ditches

170c. . . Stepped groove trench

180a. . . First solder mask opening

180b. . . Second solder mask opening

190a, 190a’. . . First solder pad pattern

190b. . . Second solder pad pattern

200, 200’. . . Package member

210, 210’. . . Wafer

220. . . Primer filler

220a. . . First solder ball

220b. . . Second solder ball

S1. . . End face

S2. . . End face

S3. . . Upper surface

A1, A1’. . . Wafer bonding area

A2, A2’. . . Surrounding area

P. . . region

1 is a schematic cross-sectional view of a flip chip package substrate according to a preferred embodiment of the present invention.

2A-2B illustrates a schematic view of a three-dimensional structure on the surface of the solder resist layer and a recessed trench.

3A-3C illustrate a three-dimensional structure on the surface of the solder resist layer and a schematic cross-sectional view of the recessed trench.

4 is a cross-sectional view of a package member in accordance with a preferred embodiment of the present invention.

Figure 5 is a top plan view of a package member in accordance with a preferred embodiment of the present invention.

Fig. 6 is a partially enlarged view of the package member of Fig. 5.

100. . . Flip chip package substrate

110. . . Core substrate

110a. . . Conductive through hole

120a. . . First inner patterned circuit layer

120b. . . Second inner patterned circuit layer

130a. . . First dielectric layer

130b. . . Second dielectric layer

140a. . . First surface patterned circuit layer

140b. . . Second surface patterned circuit layer

150a. . . First solder mask

150b. . . Second solder mask

160. . . Three-dimensional structure

170. . . Depressed trench

180a. . . First solder mask opening

180b. . . Second solder mask opening

190a. . . First solder pad pattern

190b. . . Second solder pad pattern

S1. . . End face

S2. . . End face

S3. . . Upper surface

Claims (11)

A flip chip package substrate comprising: at least one patterned circuit layer on one end surface of the flip chip package substrate; and a solder resist layer covering the patterned circuit layer, wherein one surface of the solder resist layer is provided A plurality of depressed trenches are used to increase the bonding force between the solder resist layer and a primer filler. The flip chip package substrate of claim 1, wherein the plurality of recessed trenches define at least one solid structure. The flip-chip package substrate of claim 1, wherein the end surface comprises a wafer bonding region and a peripheral region, and the plurality of recessed trenches are disposed in the wafer bonding region. The flip chip package substrate of claim 3, wherein the plurality of recessed trenches are disposed only in the die bond region. The flip chip package substrate of claim 1, wherein the circuit pattern comprises at least one solder pad pattern, and the solder resist layer has at least one solder mask opening to expose the solder pad pattern. The flip chip package substrate of claim 1, wherein the solder resist layer comprises an ABF resin. A package member comprising: a flip chip package substrate, comprising at least one patterned circuit layer on an end surface of the flip chip package substrate; a solder resist layer covering the patterned circuit pattern; and a plurality of recessed trenches, An upper surface of the solder resist layer; a wafer disposed on the end surface; and a primer filler between the wafer and the solder resist layer, wherein the underfill is in contact with the plurality of recessed trenches. The package member of claim 7, wherein the plurality of recessed trenches define at least one solid structure. The package member according to claim 7, wherein each of the plurality of recessed trenches has a depth of between 1 and 5 micrometers and a width of between 10 and 80 micrometers. The package member of claim 7, wherein the primer filler fills the plurality of recessed trenches. The package member of claim 7, wherein the plurality of recessed trenches are disposed only below the wafer.