TWI879599B - Semiconductor structure - Google Patents

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a gate structure, a conductive contact, and a semiconductor material layer. The semiconductor substrate includes a doped region. The gate structure is disposed on the semiconductor substrate. The conductive contact is disposed on the doped region of the semiconductor substrate. The semiconductor material layer is disposed on sidewalls of the conductive contact and in contact with the sidewalls of the conductive contact.

Description

Semiconductor structure

The present disclosure relates to a semiconductor structure.

In the semiconductor industry, technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation.

However, existing semiconductor structures still face many problems. For example, the contact resistance of the conductive contacts of the semiconductor structure is large, which makes the on/off ratio of the device poor, such as the on current is not enough to meet the operating frequency requirements. Therefore, it is expected to improve the semiconductor structure and develop a semiconductor structure with higher performance.

The technical aspect disclosed herein is a semiconductor structure.

According to some embodiments of the present disclosure, a semiconductor structure includes a semiconductor substrate, a gate structure, a conductive contact, and a semiconductor material layer. The semiconductor substrate includes a doped region. The gate structure is disposed on the semiconductor substrate. The conductive contact is disposed on the doped region of the semiconductor substrate. A plurality of semiconductor material layers are disposed on a plurality of sidewalls of the conductive contact, wherein the top surface of each of the semiconductor material layers is substantially flush with the top surface of the conductive contact.

In some embodiments of the present disclosure, the semiconductor material layer contacts the sidewalls of the conductive contact.

In some embodiments of the present disclosure, the bottom surface of the conductive contact is separated from the semiconductor material layer.

In some embodiments of the present disclosure, a bottom surface of the conductive contact is below a bottom surface of the gate structure.

In some embodiments of the present disclosure, the semiconductor structure further includes a dielectric layer disposed on the semiconductor substrate and surrounding the gate structure and the conductive contact.

In some embodiments of the present disclosure, the conductive contacts are separated from the dielectric layer.

Another technical aspect of the present disclosure is a semiconductor structure.

According to some embodiments of the present disclosure, a semiconductor structure includes a semiconductor substrate, a gate structure, a conductive contact, and a semiconductor material layer. The semiconductor substrate includes a doped region. The gate structure is disposed on the semiconductor substrate. The conductive contact is disposed on the doped region of the semiconductor substrate. A plurality of semiconductor material layers are disposed on a plurality of sidewalls of the conductive contact, wherein the thickness of the conductive contact between the semiconductor material layers is greater than the thickness of each of the semiconductor material layers.

In some embodiments of the present disclosure, a ratio of the thickness of each of the semiconductor material layers to the thickness of the conductive contacts between the semiconductor material layers is in a range of 0.1 to 0.5.

In some embodiments of the present disclosure, a gate structure includes a gate dielectric, a first gate electrode, a second gate electrode, and a capping layer. The gate dielectric contacts the semiconductor substrate. The first gate electrode is disposed on the gate dielectric. The second gate electrode is disposed on the first gate electrode. The capping layer surrounds the gate dielectric, the first gate electrode, and the second gate electrode.

In some embodiments of the present disclosure, the conductive contact contacts the sidewall of the doped region.

According to the above-mentioned implementation method of the present disclosure, since the semiconductor material layer is disposed on a plurality of side walls of the conductive contact and contacts the side walls of the conductive contact, the contact resistance of the conductive contact can be reduced and the on-current can be increased, thereby improving the switching ratio of the device to meet the operating frequency requirement.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary and therefore should not be used to limit the present disclosure. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. In addition, in order to facilitate the reader's viewing, the size of each component in the drawings is not drawn according to the actual scale.

The terms "about", "approximately" or "substantially" as used in this disclosure shall generally refer to within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the meaning of the terms "about", "approximately" or "substantially" can be inferred.

FIG. 1 is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present disclosure. Referring to FIG. 1 , the semiconductor structure 10 includes a semiconductor substrate 100, a gate structure 120, a semiconductor material layer 130, and a conductive contact 140. The semiconductor substrate 100 includes a doped region 110. The gate structure 120 is disposed on the semiconductor substrate 100. The conductive contact 140 is disposed on the doped region 110 of the semiconductor substrate 100. The semiconductor material layer 130 is disposed on a plurality of sidewalls 143 of the conductive contact 140, and the semiconductor material layer 130 contacts the sidewalls 143 of the conductive contact 140. In this way, the contact area of the conductive contact 140 can be increased (for example, the semiconductor material layer 130 electrically connects the conductive contact 140 and the doped region 110, so that the conductive current can flow through the semiconductor material layer 130, thereby increasing the contact/conduction area of the conductive contact 140), reducing the contact resistance of the conductive contact 140 and increasing the on current, thereby improving the on/off ratio of the component to meet the operating frequency requirements.

The doped region 110 is disposed on the top portion of the semiconductor substrate 100. The doped region 110 can be formed in the semiconductor substrate 100 by performing an implantation process on the top portion of the semiconductor substrate 100. In some embodiments, a top surface 111 of the doped region 110 is substantially flush with the top surface 101 of the semiconductor substrate 100.

The gate structure 120 is disposed on the semiconductor substrate 100 and contacts the semiconductor substrate 100. The gate structure 120 includes a gate dielectric 121, a first gate electrode 122, a second gate electrode 124 and a capping layer 126. The gate dielectric 121 is disposed on the semiconductor substrate 100 and contacts the semiconductor substrate 100 , the first gate electrode 122 is disposed on the gate dielectric 121 and contacts the gate dielectric 121 , the second gate electrode 124 is disposed on the first gate electrode 122 and contacts the first gate electrode 122 , and the capping layer 126 is disposed on the second gate electrode 124 and contacts the second gate electrode 124 . In some embodiments, the capping layer 126 surrounds and contacts the gate dielectric 121 , the first gate electrode 122 , and the second gate electrode 124 .

It should be understood that the doped regions 110 located on both sides of the gate structure 120 can be regarded as source/drain regions, that is, the doped regions 110 in the following paragraphs can be interchangeably referred to as source/drain regions. The source/drain regions and the gate structure 120 constitute a transistor. In other words, the semiconductor structure 10 includes a transistor and two conductive contacts 140, wherein the transistor includes the gate structure 120 and the source/drain regions (i.e., the doped regions 110 located on both sides of the gate structure 120), and the two conductive contacts 140 are electrically connected and contact the two source/drain regions, respectively.

The semiconductor material layer 130 vertically extends upward from the doped region 110 and is disposed on the sidewall 143 of the conductive contact 140. The semiconductor material layer 130 is disposed between the sidewall 143 of the conductive contact 140 and the gate structure 120. In some embodiments, the semiconductor material layer 130 further includes a portion that contacts the doped region 110. That is, the doped region 110 has a surface 113 and a sidewall 115 connected to the surface 113, and the sidewall 115 of the doped region 110 contacts the semiconductor material layer 130 and the conductive contact 140.

In some embodiments, the semiconductor material layer 130 includes a doped polysilicon material to increase the contact area with the conductive contact 140 (for example, the semiconductor material layer 130 electrically connects the conductive contact 140 and the doped region 110, so that the conductive current can flow through the semiconductor material layer 130, thereby increasing the contact/conduction area of the conductive contact 140), thereby reducing the contact resistance of the conductive contact 140. In this way, the on-current can be increased and the switching ratio of the device can be improved. Refer to FIG. 8, which is a voltage-current relationship diagram according to an embodiment of the present disclosure. Specifically, FIG. 8 shows a voltage-current relationship diagram of the semiconductor structure 10 of FIG. 1 when the gate structure 120 is pressurized. If the semiconductor structure 10 includes a semiconductor material layer 130, the conductive contact 140 may have a larger contact area, thereby increasing the on-current (for example, increasing the on-current by about 30%), as shown by curve C1. In contrast, if the semiconductor structure 10 does not include the semiconductor material layer 130, as shown by curve C2, the on-current is lower at the same voltage. Therefore, the semiconductor material layer 130 disclosed in the present invention can achieve the technical effect of increasing the on-current and improving the switching ratio of the component.

In some embodiments, the semiconductor material layer 130 includes a P-type dopant, such as boron (B), BF ₂ , BF ₃ , or a combination thereof. In some other embodiments, the semiconductor material layer 130 includes an N-type dopant, such as phosphorus (P), arsenic (As), or a combination thereof. The semiconductor material layer 130 may be a highly doped (or interchangeably referred to as heavily doped) semiconductor material layer. For example, the semiconductor material layer 130 includes highly doped polysilicon.

The conductive contact 140 includes a bottom portion 142 and a top portion 144, wherein the bottom portion 142 is located in the semiconductor substrate 100 and the top portion 144 is located above the semiconductor substrate 100. The bottom portion 142 of the conductive contact 140 has a bottom surface 145 and a side wall 147 extending continuously upward from the bottom surface 145. In other words, the conductive contact 140 includes the bottom surface 145, the inclined side wall 147 extending continuously upward from the bottom surface 145, and the vertical side wall 143 extending continuously upward from the inclined side wall 147, wherein the vertical side wall 143 is substantially perpendicular to the bottom surface 145 and separated from the bottom surface 145. In some embodiments, the bottom portion 142 of the conductive contact 140 is in the shape of an inverted trapezoid, and the top portion 144 of the conductive contact 140 is in the shape of a rectangle.

In some embodiments, the semiconductor material layer 130 is disposed on the sidewall 143 of the top portion 144 of the conductive contact 140, but is not disposed on the bottom surface 145 of the bottom portion 142 of the conductive contact 140. In other words, the bottom surface 145 of the conductive contact 140 is separated from the semiconductor material layer 130. In some embodiments, the semiconductor material layer 130 contacts the sidewall 147 of the conductive contact 140. In other words, a portion of the sidewall 147 of the conductive contact 140 contacts the semiconductor material layer 130, while the remaining portion of the sidewall 147 of the conductive contact 140 does not contact (is separated from) the semiconductor material layer 130. In some embodiments, the (lowest) bottom surface 145 of the conductive contact 140 is below the (lowest) bottom surface 125 of the gate structure 120 .

In some embodiments, the semiconductor material layer 130 includes a dopant, while the conductive contact 140 does not include a dopant. When performing an implantation process to dope the conductive contact 140, the dopant may be implanted into the channel region (i.e., the semiconductor substrate 100 below the gate structure 120), which will affect the short channel effect. Therefore, in some embodiments of the present disclosure, the conductive contact 140 does not include a dopant to avoid the above-mentioned short channel effect.

In some embodiments, the semiconductor structure 10 is a complementary metal oxide semiconductor (CMOS), which includes an N-type transistor and a P-type transistor. The N-type transistor (or P-type transistor) may include a gate structure 120, a doped region 110 (i.e., a source/drain region), and a spacer structure 150. In other words, the gate structure 120, the doped region 110 (i.e., a source/drain region), and the spacer structure 150 of the present disclosure may constitute a P-type transistor and/or an N-type transistor. In the embodiment where the semiconductor structure 10 includes an N-type transistor, the doping concentration of the semiconductor material layer 130 may be in a range of about 1E19 atoms/cm 3 to about 3E20 atoms/cm ³ . When the doping concentration of the semiconductor material layer 130 is within the above range, a lower Schottky barrier height, a lower contact resistance with the conductive contact 140 and a higher current may be formed. If the doping concentration of the semiconductor material layer 130 is less than 1E19 atoms/cm3, the contact resistance between the semiconductor material layer 130 and the conductive contact 140 may be too large. If the doping concentration of the semiconductor material layer 130 is greater than 3E20 atoms/cm3, it may be limited by process limitations and cannot be activated (for example, the doping concentration is too large to be activated). In addition, the doping concentration of the doped region 110 is about 3E20 atoms/cm3. The doping concentration of the semiconductor material layer 130 is less than or equal to the doping concentration of the doping region 110, and the conductivity type of the dopant of the semiconductor material layer 130 is the same as the conductivity type of the dopant of the doping region 110, for example, both are N-type. In an embodiment in which the semiconductor structure 10 includes a P-type transistor, the doping concentration of the semiconductor material layer 130 may be in a range of about 1E19 atoms/cm3 to about 1E20 atoms/cm3. When the doping concentration of the semiconductor material layer 130 is within the above range, a lower Schottky barrier height, a lower contact resistance with the conductive contact 140, and a higher current can be formed. If the doping concentration of the semiconductor material layer 130 is less than 1E19 atoms/cm3, the contact resistance between the semiconductor material layer 130 and the conductive contact 140 may be too large; if the doping concentration of the semiconductor material layer 130 is greater than 1E20 atoms/cm3, it may be limited by process limitations and cannot be activated (for example, the doping concentration is too high to be activated). In addition, the doping concentration of the doping region 110 is about 1E20 atoms/cm3. The doping concentration of the semiconductor material layer 130 is less than or equal to the doping concentration of the doping region 110, and the conductivity type of the dopant in the semiconductor material layer 130 is the same as the conductivity type of the dopant in the doping region 110, for example, both are P-type.

In some embodiments, the conductive contact 140 has a (maximum) thickness T1 between the semiconductor material layers 130, and each of the semiconductor material layers 130 has a thickness T2, wherein the thickness T1 of the conductive contact 140 is greater than the thickness T2 of the semiconductor material layer 130. The ratio of the thickness T2 of the semiconductor material layer 130 to the thickness T1 of the conductive contact 140 (i.e., T2/T1) may be in the range of about 0.1 to about 0.5 (e.g., 0.1, 0.2, 0.3, 0.4, or 0.5). If the ratio of the thickness T2 of the semiconductor material layer 130 to the thickness T1 of the conductive contact 140 is less than 0.1, the current may be excessively concentrated in the semiconductor material layer 130, thereby causing a reliability problem of excessive current; if the ratio of the thickness T2 of the semiconductor material layer 130 to the thickness T1 of the conductive contact 140 is greater than 0.5, the process of the conductive contact 140 is too difficult (for example, the gap between the semiconductor material layers 130 is too small to fill the conductive material to form the conductive contact 140).

In some embodiments, the semiconductor structure 10 further includes a spacer structure 150, an etch stop layer 160, and a dielectric layer 170. The spacer structure 150 is disposed on a plurality of (opposite) sidewalls 123 of the gate structure 120. Specifically, the spacer structure 150 is located on opposite sidewalls of the capping layer 126 of the gate structure 120, and the spacer structure 150 contacts the capping layer 126 of the gate structure 120. In some embodiments, the etch stop layer 160 is disposed on the doped region 110, the spacer structure 150, and the gate structure 120, and the etch stop layer 160 contacts the doped region 110, the spacer structure 150, and the gate structure 120. In some embodiments, the etch stop layer 160 is a contact etch stop layer (CESL). The etch stop layer 160 can be one or more stress layers. In some embodiments, the dielectric layer 170 is disposed on the semiconductor substrate 100 and surrounds the gate structure 120 and the conductive contact 140. In some embodiments, the semiconductor material layer 130 is disposed on the sidewall 173 of the dielectric layer 170, and the semiconductor material layer 130 contacts the dielectric layer 170, the etch stop layer 160, and the conductive contact 140. In some embodiments, the conductive contact 140 is separated from the dielectric layer 170 by the semiconductor material layer 130.

FIG. 2 to FIG. 7 are cross-sectional views of a method of forming the semiconductor structure 10 of FIG. 1 at different stages according to some embodiments of the present disclosure.

Referring to FIG. 2 , a semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 includes silicon. In some other embodiments, the semiconductor substrate 100 includes other elemental semiconductors, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or combinations thereof.

The doped region 110 is formed on the semiconductor substrate 100. In detail, an implantation process is performed on the top portion of the semiconductor substrate 100 to form the doped region 110 in the semiconductor substrate 100. The doped region 110 may be formed by an N-type or P-type dopant ion implantation process. Then, an annealing process may be performed to activate the implanted dopant of the doped region 110. In some embodiments, the doped region 110 is highly doped silicon (or heavily doped silicon). That is, in FIG. 1 and FIG. 2 , in an embodiment in which the semiconductor structure 10 includes an N-type transistor, the doping region 110 includes a high concentration of an N-type dopant; in an embodiment in which the semiconductor structure 10 includes a P-type transistor, the doping region 110 includes a high concentration of a P-type dopant.

The gate structure 120 is formed on the semiconductor substrate 100. In some embodiments, a gate dielectric layer, a first gate electrode layer, and a second gate electrode layer are sequentially formed on the semiconductor substrate 100, and then the gate dielectric layer, the first gate electrode layer, and the second gate electrode layer are patterned to form a gate dielectric 121, a first gate electrode 122, and a second gate electrode 124. Then, a capping layer 126 is formed on the second gate electrode 124 and surrounds the gate dielectric 121, the first gate electrode 122 and the second gate electrode 124. Thus, a gate structure 120 including the gate dielectric 121, the first gate electrode 122, the second gate electrode 124 and the capping layer 126 is formed.

The gate dielectric 121 is on the semiconductor substrate 100 and includes a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the gate dielectric 121 includes a high dielectric constant (k) dielectric material having a dielectric constant greater than that of silicon oxide. Exemplary high-k dielectric materials include, but are not limited to, helium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), chromium oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), chromium aluminum oxide (LaAlO ₃ ), and yttrium oxide (Y ₂ O ₃ ). In some embodiments, the gate dielectric layer is formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition methods. In some embodiments, the gate dielectric layer is formed by converting a surface portion of the semiconductor substrate 100 using thermal oxidation.

The first gate electrode 122 is located on the gate dielectric 121, and the second gate electrode 124 is located on the first gate electrode 122. In some embodiments, the first gate electrode 122 and the second gate electrode 124 include different materials. The first gate electrode 122 includes polysilicon, other suitable semiconductor materials, or other suitable conductive materials. The second gate electrode 124 includes tungsten (W), titanium nitride (TiN), other suitable metals, other suitable metal nitrides, or other suitable conductive materials. In some embodiments, the first gate electrode layer and the second gate electrode layer are formed using, for example, ALD, CVD, PVD or other suitable deposition methods.

The capping layer 126 is located on the second gate electrode 124, and the capping layer 126 surrounds the second gate electrode 124, the first gate electrode 122, and the gate dielectric 121. In some embodiments, the capping layer 126 includes a nitride (e.g., silicon nitride) or other suitable dielectric materials. In some embodiments, the capping layer 126 is formed using, for example, ALD, CVD, PVD, or other suitable deposition methods.

After forming the gate structure 120, the spacer structure 150 is formed on the opposite sidewalls 123 of the gate structure 120. In some embodiments, the spacer structure 150 includes an oxide (e.g., silicon dioxide) or other suitable dielectric materials. In some embodiments, the method of forming the spacer structure 150 includes first depositing a spacer layer on the gate structure 120 and the exposed surface of the semiconductor substrate 100, and then etching the spacer layer to remove the horizontal portion of the spacer layer to form the spacer structure 150. In some embodiments, the spacer layer is formed using, for example, ALD, CVD, PVD or other suitable deposition methods. The etching of the spacer layer can use a dry etching process such as reactive ion etching (RIE). The remaining vertical portion of the spacer layer on the sidewall 123 of the gate structure 120 constitutes a spacer structure 150 .

In some embodiments, the doped region 110 is formed in the semiconductor substrate 100 before the gate structure 120 is formed. In some other embodiments, the doped region 110 is formed in the semiconductor substrate 100 after the gate structure 120 is formed. In detail, after the gate structure 120 is formed on the semiconductor substrate 100, the spacer structure 150 is formed on the opposite sidewalls of the gate structure 120. After the spacer structure 150 is formed, the doped region 110 is formed in the semiconductor substrate 100.

2 and 3, an etch stop layer 160 is conformally formed on the structure of FIG. 2. In some embodiments, the etch stop layer 160 is conformally formed on the doped region 110, the gate structure 120, and the spacer structure 150. The etch stop layer 160 covers and contacts the doped region 110, the gate structure 120, and the spacer structure 150. In some embodiments, the etch stop layer 160 includes a nitride (e.g., silicon nitride) or other suitable dielectric material. The etch stop layer 160 and the capping layer 126 of the gate structure 120 may include the same material, such as nitride (or silicon nitride). In some embodiments, the etch stop layer 160 is formed using ALD, CVD, PVD or other suitable deposition methods.

Referring to FIG. 4 , after the etch stop layer 160 is formed, a dielectric layer 170 is formed on the etch stop layer 160. In detail, the dielectric layer 170 is formed on the semiconductor substrate 100 and surrounds the gate structure 120. The dielectric layer 170 contacts the etch stop layer 160. The dielectric layer 170 may be considered an interlayer dielectric (ILD) layer. The dielectric layer 170 may be formed using CVD, high density plasma CVD, spin coating, sputtering, or other appropriate methods. In some embodiments, the dielectric layer 170 includes an oxide (e.g., silicon dioxide) or other appropriate dielectric materials. In some embodiments, the dielectric layer 170 and the spacer structure 150 include the same material, such as oxide (or silicon dioxide).

5 , after the dielectric layer 170 is formed, an etching process E1 is performed to form at least one contact via 180 in the dielectric layer 170, wherein the contact via 180 exposes the doped region 110. In detail, the etching process E1 is performed to form at least one contact via 180 between the gate structure 120 and the dielectric layer 170, thereby removing a portion of the dielectric layer 170 and a portion of the etch stop layer 160. In other words, the contact via 180 further penetrates the etch stop layer 160 to expose the doped region 110. In some embodiments, the etching process E1 further includes removing a portion of the doped region 110 such that the doped region 110 has an exposed surface 113 lower than the top surface 111.

In some embodiments, the etching process E1 includes multiple etching processes. For example, the etching process E1 includes three etching processes performed sequentially, namely, an etching process for etching the dielectric layer 170 , an etching process for etching the etch stop layer 160 , and an etching process for etching the doped region 110 .

In some embodiments, the etching process E1 may use a dry etching process or a wet etching process. When the dry etching process is used, the process gas may include CF ₄ , CHF ₃ , NF ₃ , SF ₆ , Br ₂ , HBr, Cl ₂ , or a combination thereof. A diluent gas such as N ₂ , O ₂ or Ar may be selectively used. When the wet etching process is used, the etching solution (etchant) may include NH ₄ OH:H ₂ O ₂ :H ₂ O (APM), NH ₂ OH, KOH, HNO ₃ :NH ₄ F:H ₂ O or other appropriate etching solutions.

5 and 6 , a semiconductor material layer 130 is formed on the structure of FIG 5 . In detail, the semiconductor material layer 130 is conformally formed on the top surface 171 of the dielectric layer 170 and on the contact via 180. That is, the semiconductor material layer 130 is formed on the sidewall 173 of the dielectric layer 170, on the sidewall of the etch stop layer 160, and on the exposed surface 113 and the sidewall 115 of the doped region 110. The semiconductor material layer 130 contacts the top surface 171 and the sidewalls 173 of the dielectric layer 170, the sidewalls of the etch stop layer 160, and the exposed surface 113 and the sidewalls 115 of the doped region 110. In some embodiments, as shown in FIG. 6 , after the contact via 180 is conformally covered with the semiconductor material layer 130, it is still not filled, and the semiconductor material layer 130 is only attached to the contact via 180 along the sidewalls and the bottom surface of the contact via 180. In some embodiments, the semiconductor material layer 130 includes polysilicon or other suitable semiconductor materials. The semiconductor material layer 130 can be formed using CVD, ALD, PVD or other suitable deposition methods. In some implementations, the semiconductor material layer 130 may be doped in-situ during the formation of the semiconductor material layer 130 .

6 and 7 , an etching process is performed to remove a portion of the semiconductor material layer 130 so that the semiconductor material layer 130 is separated from the surface 113 of the doped region 110. In detail, the etching process is performed to remove a portion of the semiconductor material layer 130 located above the top surface 171 of the dielectric layer 170 and a portion of the semiconductor material layer 130 located above the surface 113 of the doped region 110 so that the top surface 171 of the dielectric layer 170 and the surface 113 of the doped region 110 are exposed. In some embodiments, the etching process is performed so that a portion of the semiconductor material layer 130 located on the sidewall 115 of the doped region 110 is removed, and the remaining semiconductor material layer 130 contacts the sidewall 115 of the doped region 110. In some other embodiments, the etching process is performed so that the portion of the semiconductor material layer 130 located on the sidewall 115 of the doped region 110 is completely removed, so that the semiconductor material layer 130 does not contact (is separated from) the sidewall 115 of the doped region 110.

In some embodiments, the etching process for etching the semiconductor material layer 130 includes a dry etching process, such as a plasma etching process. In some embodiments, the etching process includes an anisotropic etching process, and the aforementioned anisotropic etching process removes the horizontal portion of the semiconductor material layer 130 (i.e., the portion located on the top surface 171 of the dielectric layer 170 and the portion on the surface 113 of the doped region 110) and does not remove the vertical portion of the semiconductor material layer 130 (i.e., the portion located on the sidewall 173 of the dielectric layer 170). In this way, the conductive contact 140 formed subsequently can directly contact the doped region 110.

Returning to FIG. 1 (also see FIG. 7 ), after removing part of the semiconductor material layer 130 , a conductive material is filled into the contact via 180 to form a conductive contact 140 . Thus, the semiconductor structure 10 shown in FIG. 1 can be obtained.

In some embodiments, a portion of the semiconductor material layer 130 is removed before forming the conductive contact 140, so that the semiconductor material layer 130 is separated from the bottom surface 145 of the conductive contact 140 (or the surface 113 of the doped region 110). In other words, the conductive contact 140 contacts the semiconductor material layer 130, the surface 113 of the doped region 110, and the sidewall 115. In some embodiments, the conductive contact 140 is separated from the dielectric layer 170 by the semiconductor material layer 130. In addition, the conductive contact 140 is separated from the etch stop layer 160 by the semiconductor material layer 130. In some embodiments, the conductive contact 140 includes aluminum (Al) or other suitable conductive materials. The conductive contact 140 may be formed using CVD, ALD, PVD or other suitable deposition methods.

In some embodiments, after forming the conductive contact 140, a planarization process is performed to remove excess portions of the conductive contact 140 so that the top surfaces of the dielectric layer 170, the semiconductor material layer 130, and the conductive contact 140 are substantially flush.

In summary, the semiconductor material layer disclosed in the present invention is disposed on a plurality of sidewalls of the conductive contact and contacts the sidewalls of the conductive contact, which can reduce the contact resistance of the conductive contact and increase the on-current, thereby improving the switching ratio of the device to meet the operating frequency requirement.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

10:Semiconductor structure

100:Semiconductor substrate

101,111,171: Top

110: Mixed area

113: Surface

115,123,143,147,173: Side wall

120: Gate structure

121: Gate dielectric

122: First gate electrode

124: Second gate electrode

125,145: Bottom

126: Covering layer

130:Semiconductor material layer

140: Conductive contact

142: Bottom part

144: Top part

150: Interval structure

160: Etch stop layer

170: Dielectric layer

180: Contact through hole

C1,C2: Curve

E1: Etching process

T1, T2: thickness

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. FIG. 2 to FIG. 7 are cross-sectional views of methods of forming a semiconductor structure at different stages according to some embodiments of the present disclosure. FIG. 8 is a diagram showing the relationship between current and voltage according to an embodiment of the present disclosure.

10:Semiconductor structure

100:Semiconductor substrate

101,111: Top

110: Mixed area

113: Surface

115,123,143,147,173: Side wall

120: Gate structure

121: Gate dielectric

122: First gate electrode

124: Second gate electrode

125,145: Bottom

126: Covering layer

130:Semiconductor material layer

140: Conductive contact

142: Bottom part

144: Top part

150: Interval structure

160: Etch stop layer

170: Dielectric layer

T1, T2: thickness

Claims (10)

A semiconductor structure comprises: a semiconductor substrate comprising a doped region; a gate structure disposed on the semiconductor substrate; a conductive contact disposed on the doped region of the semiconductor substrate; and a plurality of semiconductor material layers disposed on a plurality of sidewalls of the conductive contact, wherein a highest top surface of each of the semiconductor material layers away from the semiconductor substrate is substantially flush with a highest top surface of the conductive contact away from the semiconductor substrate. A semiconductor structure as described in claim 1, wherein the semiconductor material layers contact the side walls of the conductive contact. A semiconductor structure as described in claim 1, wherein a bottom surface of the conductive contact is separated from the semiconductor material layers. A semiconductor structure as described in claim 1, wherein a bottom surface of the conductive contact is below a bottom surface of the gate structure. The semiconductor structure as described in claim 1 further comprises: a dielectric layer disposed on the semiconductor substrate and surrounding the gate structure and the conductive contact. A semiconductor structure as described in claim 5, wherein the conductive contact is separated from the dielectric layer. A semiconductor structure comprises: a semiconductor substrate comprising a doped region; a gate structure disposed on the semiconductor substrate; a conductive contact disposed on the doped region of the semiconductor substrate; and a plurality of semiconductor material layers disposed on a plurality of sidewalls of the conductive contact, wherein a thickness of the conductive contact between the semiconductor material layers is greater than a thickness of each of the semiconductor material layers. A semiconductor structure as described in claim 7, wherein the ratio of the thickness of each of the semiconductor material layers to the thickness of the conductive contact between the semiconductor material layers is in the range of 0.1 to 0.5. A semiconductor structure as described in claim 7, wherein the gate structure comprises: a gate dielectric contacting the semiconductor substrate; a first gate electrode disposed on the gate dielectric; a second gate electrode disposed on the first gate electrode; and a capping layer surrounding the gate dielectric, the first gate electrode and the second gate electrode. A semiconductor structure as described in claim 7, wherein the conductive contact contacts a side wall of the doped region.

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