TWI899010B - Semiconductor structure - Google Patents

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a gate structure, a conductive contact, and a plurality of semiconductor material layers. The semiconductor substrate includes a doped region. The gate structure is disposed on the semiconductor substrate. The conductive contact is disposed on the doped region of the semiconductor substrate. The semiconductor material layers are disposed on sidewalls of the conductive contact, in which each of the semiconductor material layers is in contact of the doped region.

Description

semiconductor structure

This disclosure relates to a semiconductor structure.

In the semiconductor industry, technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation.

However, existing semiconductor structures still face numerous challenges. For example, the high contact resistance of the conductive contacts within semiconductor structures results in a poor on/off ratio, such as insufficient on-current to meet operating frequency requirements. Therefore, there is a desire to improve semiconductor structures and develop higher-performance semiconductor structures.

The technical aspect disclosed herein is a semiconductor structure.

According to some embodiments of the present disclosure, a semiconductor structure includes a semiconductor substrate, a gate structure, a conductive contact, and a semiconductor material layer. The semiconductor substrate includes a doped region. The gate structure is disposed on the semiconductor substrate. The conductive contact is disposed on the doped region of the semiconductor substrate. A plurality of semiconductor material layers are disposed on a plurality of sidewalls of the conductive contact, wherein each of the semiconductor material layers contacts the doped region.

In some embodiments of the present disclosure, the layer of semiconductor material contacts the sidewalls of the conductive contact.

In some embodiments of the present disclosure, the bottom surface of the conductive contact is separated from the semiconductor material layer.

In some embodiments of the present disclosure, the bottom surface of the conductive contact is below the bottom surface of the gate structure.

In some embodiments of the present disclosure, the semiconductor structure further includes a dielectric layer disposed on the semiconductor substrate and surrounding the gate structure and the conductive contact.

In some embodiments of the present disclosure, a top surface of each of the semiconductor material layers is substantially flush with a top surface of the conductive contact.

In some embodiments of the present disclosure, the thickness of the conductive contacts between the semiconductor material layers is greater than the thickness of each of the semiconductor material layers.

In some embodiments of the present disclosure, a ratio of the thickness of each semiconductor material layer to the thickness of the conductive contacts between the semiconductor material layers is in a range of 0.1 to 0.5.

In some embodiments of the present disclosure, a gate structure includes a gate dielectric, a first gate electrode, a second gate electrode, and a capping layer. The gate dielectric contacts a semiconductor substrate. The first gate electrode is disposed on the gate dielectric. The second gate electrode is disposed on the first gate electrode. The capping layer surrounds the gate dielectric, the first gate electrode, and the second gate electrode.

In some embodiments of the present disclosure, the conductive contact contacts the sidewalls of the doped region.

According to the above-mentioned embodiment of the present disclosure, since the semiconductor material layer is disposed on multiple sidewalls of the conductive contact and contacts the sidewalls of the conductive contact, the contact resistance of the conductive contact can be reduced and the on-current can be increased, thereby improving the switching ratio of the device to meet the operating frequency requirement.

The following diagrams illustrate various embodiments of the present disclosure. For the sake of clarity, numerous practical details are included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure and, therefore, should not be construed as limiting the present disclosure. Furthermore, to simplify the diagrams, some commonly used structures and components are depicted in simplified schematic form. Furthermore, for ease of viewing, the dimensions of the components in the diagrams are not drawn to scale.

As used herein, "about," "approximately," or "substantially" should generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. The numerical values given herein are approximate, meaning that unless expressly stated, the meaning of the term "about," "approximately," or "substantially" can be inferred.

FIG1 is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present disclosure. Referring to FIG1 , semiconductor structure 10 includes a semiconductor substrate 100, a gate structure 120, a semiconductor material layer 130, and a conductive contact 140. Semiconductor substrate 100 includes a doped region 110. Gate structure 120 is disposed on semiconductor substrate 100. Conductive contact 140 is disposed on doped region 110 of semiconductor substrate 100. Semiconductor material layer 130 is disposed on a plurality of sidewalls 143 of conductive contact 140, and semiconductor material layer 130 contacts the sidewalls 143 of conductive contact 140. In this way, the contact area of the conductive contact 140 can be increased (for example, the semiconductor material layer 130 electrically connects the conductive contact 140 and the doped region 110, allowing the conductive current to flow through the semiconductor material layer 130, thereby increasing the contact/conducting area of the conductive contact 140), reducing the contact resistance of the conductive contact 140 and increasing the on-current, thereby improving the on/off ratio of the device to meet the operating frequency requirements.

The doped region 110 is disposed on the top portion of the semiconductor substrate 100. The doped region 110 can be formed in the semiconductor substrate 100 by performing an implantation process on the top portion of the semiconductor substrate 100. In some embodiments, a top surface 111 of the doped region 110 is substantially flush with the top surface 101 of the semiconductor substrate 100.

The gate structure 120 is disposed on the semiconductor substrate 100 and contacts the semiconductor substrate 100 . The gate structure 120 includes a gate dielectric 121 , a first gate electrode 122 , a second gate electrode 124 , and a capping layer 126 . The gate dielectric 121 is disposed on and contacts the semiconductor substrate 100 . The first gate electrode 122 is disposed on and contacts the gate dielectric 121 . The second gate electrode 124 is disposed on and contacts the first gate electrode 122 . The capping layer 126 is disposed on and contacts the second gate electrode 124 . In some embodiments, the capping layer 126 surrounds and contacts the gate dielectric 121 , the first gate electrode 122 , and the second gate electrode 124 .

It should be understood that the doped regions 110 located on either side of the gate structure 120 can be considered source/drain regions. That is, in the following paragraphs, the doped regions 110 may be interchangeably referred to as source/drain regions. The source/drain regions and the gate structure 120 constitute a transistor. In other words, the semiconductor structure 10 includes a transistor and two conductive contacts 140, wherein the transistor includes the gate structure 120 and the source/drain regions (i.e., the doped regions 110 located on either side of the gate structure 120). The two conductive contacts 140 are electrically connected to and contact the two source/drain regions, respectively.

The semiconductor material layer 130 extends vertically upward from the doped region 110 and is disposed on the sidewalls 143 of the conductive contact 140. The semiconductor material layer 130 is disposed between the sidewalls 143 of the conductive contact 140 and the gate structure 120. In some embodiments, the semiconductor material layer 130 further includes a portion that contacts the doped region 110. In other words, the doped region 110 has a surface 113 and a sidewall 115 connected to the surface 113. The sidewall 115 of the doped region 110 contacts the semiconductor material layer 130 and the conductive contact 140.

In some embodiments, semiconductor material layer 130 includes doped polysilicon material to increase the contact area with conductive contact 140 (for example, semiconductor material layer 130 electrically connects conductive contact 140 and doped region 110, allowing conductive current to flow through semiconductor material layer 130, thereby increasing the contact/conducting area of conductive contact 140). This reduces the contact resistance of conductive contact 140. This increases the on-current and improves the device's on/off ratio. See FIG8 , which is a graph showing the relationship between voltage and current according to one embodiment of the present disclosure. Specifically, FIG8 shows a voltage-current relationship diagram of the semiconductor structure 10 of FIG1 when voltage is applied to the gate structure 120. If the semiconductor structure 10 includes the semiconductor material layer 130, the conductive contact 140 can have a larger contact area, thereby increasing the on-current (for example, increasing the on-current by approximately 30%), as shown by curve C1. In contrast, if the semiconductor structure 10 does not include the semiconductor material layer 130, as shown by curve C2, the on-current is lower at the same voltage. Therefore, the semiconductor material layer 130 disclosed herein can achieve the technical effect of increasing the on-current and improving the switching ratio of the device.

In some embodiments, semiconductor material layer 130 includes a P-type dopant, such as boron (B), BF ₂ , BF ₃ , or a combination thereof. In some other embodiments, semiconductor material layer 130 includes an N-type dopant, such as phosphorus (P), arsenic (As), or a combination thereof. Semiconductor material layer 130 can be a highly doped (or interchangeably referred to as heavily doped) semiconductor material layer. For example, semiconductor material layer 130 includes highly doped polysilicon.

Conductive contact 140 includes a bottom portion 142 and a top portion 144, wherein bottom portion 142 is located in semiconductor substrate 100 and top portion 144 is located above semiconductor substrate 100. Bottom portion 142 of conductive contact 140 has a bottom surface 145 and a sidewall 147 extending continuously upward from bottom surface 145. In other words, conductive contact 140 includes bottom surface 145, an inclined sidewall 147 extending continuously upward from bottom surface 145, and a vertical sidewall 143 extending continuously upward from inclined sidewall 147, wherein vertical sidewall 143 is substantially perpendicular to bottom surface 145 and spaced apart from bottom surface 145. In some embodiments, the bottom portion 142 of the conductive contact 140 is in the shape of an inverted trapezoid, and the top portion 144 of the conductive contact 140 is in the shape of a rectangle.

In some embodiments, the semiconductor material layer 130 is disposed on the sidewall 143 of the top portion 144 of the conductive contact 140, but is not disposed on the bottom surface 145 of the bottom portion 142 of the conductive contact 140. In other words, the bottom surface 145 of the conductive contact 140 is separated from the semiconductor material layer 130. In some embodiments, the semiconductor material layer 130 contacts the sidewall 147 of the conductive contact 140. In other words, a portion of the sidewall 147 of the conductive contact 140 contacts the semiconductor material layer 130, while the remaining portion of the sidewall 147 of the conductive contact 140 does not contact (is separated from) the semiconductor material layer 130. In some embodiments, the (lowest) bottom surface 145 of the conductive contact 140 is below the (lowest) bottom surface 125 of the gate structure 120 .

In some embodiments, the semiconductor material layer 130 contains a dopant, while the conductive contact 140 does not. When performing an implantation process to dope the conductive contact 140, the dopant may also be implanted into the channel region (i.e., the semiconductor substrate 100 below the gate structure 120), which could affect the short channel effect. Therefore, in some embodiments of the present disclosure, the conductive contact 140 does not contain a dopant to avoid the aforementioned short channel effect.

In some embodiments, the semiconductor structure 10 is a complementary metal oxide semiconductor (CMOS) that includes an N-type transistor and a P-type transistor. The N-type transistor (or P-type transistor) may include a gate structure 120, a doped region 110 (i.e., source/drain region), and a spacer structure 150. In other words, the gate structure 120, the doped region 110 (i.e., source/drain region), and the spacer structure 150 of the present disclosure may constitute a P-type transistor and/or an N-type transistor. In embodiments where the semiconductor structure 10 includes an N-type transistor, the doping concentration of the semiconductor material layer 130 may be in a range of approximately 1E19 atoms/cm 3 to approximately 3E20 atoms/cm ³ . When the doping concentration of the semiconductor material layer 130 is within this range, a lower Schottky barrier height, lower contact resistance with the conductive contact 140 , and higher current flow may be achieved. If the doping concentration of the semiconductor material layer 130 is less than 1E19 atoms/cm³, the contact resistance between the semiconductor material layer 130 and the conductive contact 140 may be too large. If the doping concentration of the semiconductor material layer 130 is greater than 3E20 atoms/cm³, activation may be impossible due to process limitations (e.g., the doping concentration is too high to be activated). Furthermore, the doping concentration of the doped region 110 is approximately 3E20 atoms/cm³. The dopant concentration of the semiconductor material layer 130 is less than or equal to the dopant concentration of the dopant region 110, and the conductivity type of the dopant in the semiconductor material layer 130 is the same as the conductivity type of the dopant in the dopant region 110, for example, both are N-type. In embodiments where the semiconductor structure 10 includes a P-type transistor, the dopant concentration of the semiconductor material layer 130 may be in a range from approximately 1E19 atoms/cm 3 to approximately 1E20 atoms/cm 3 . When the doping concentration of the semiconductor material layer 130 is within the above-mentioned range, a lower Schottky barrier height, lower contact resistance with the conductive contact 140, and higher current can be achieved. If the doping concentration of the semiconductor material layer 130 is less than 1E19 atoms/cm 3 , the contact resistance between the semiconductor material layer 130 and the conductive contact 140 may be too large. If the doping concentration of the semiconductor material layer 130 is greater than 1E20 atoms/cm 3 , activation may be impossible due to process limitations (e.g., the doping concentration is too high to be activated). Furthermore, the doping concentration of the doping region 110 is approximately 1E20 atoms/cm3. The doping concentration of the semiconductor material layer 130 is less than or equal to the doping concentration of the doping region 110, and the conductivity type of the dopant in the semiconductor material layer 130 is the same as that of the dopant in the doping region 110, for example, both are P-type.

In some embodiments, the conductive contact 140 has a (maximum) thickness T1 between the semiconductor material layers 130, and each of the semiconductor material layers 130 has a thickness T2, wherein the thickness T1 of the conductive contact 140 is greater than the thickness T2 of the semiconductor material layer 130. The ratio of the thickness T2 of the semiconductor material layer 130 to the thickness T1 of the conductive contact 140 (i.e., T2/T1) can be in a range of about 0.1 to about 0.5 (e.g., 0.1, 0.2, 0.3, 0.4, or 0.5). If the ratio of the thickness T2 of the semiconductor material layer 130 to the thickness T1 of the conductive contact 140 is less than 0.1, the current may be excessively concentrated in the semiconductor material layer 130, thereby causing reliability issues such as excessive current. If the ratio of the thickness T2 of the semiconductor material layer 130 to the thickness T1 of the conductive contact 140 is greater than 0.5, the process of manufacturing the conductive contact 140 is too difficult (for example, the gaps between the semiconductor material layers 130 are too small to be filled with conductive material to form the conductive contact 140).

In some embodiments, the semiconductor structure 10 further includes a spacer structure 150, an etch stop layer 160, and a dielectric layer 170. The spacer structure 150 is disposed on a plurality of (opposite) sidewalls 123 of the gate structure 120. Specifically, the spacer structure 150 is located on opposite sidewalls of the capping layer 126 of the gate structure 120, and the spacer structure 150 contacts the capping layer 126 of the gate structure 120. In some embodiments, an etch stop layer 160 is disposed on the doped region 110, the spacer structure 150, and the gate structure 120, and the etch stop layer 160 contacts the doped region 110, the spacer structure 150, and the gate structure 120. In some embodiments, the etch stop layer 160 is a contact etch stop layer (CESL). The etch stop layer 160 can be one or more stress layers. In some embodiments, a dielectric layer 170 is disposed on the semiconductor substrate 100 and surrounds the gate structure 120 and the conductive contact 140. In some embodiments, the semiconductor material layer 130 is disposed on the sidewalls 173 of the dielectric layer 170 and contacts the dielectric layer 170, the etch stop layer 160, and the conductive contact 140. In some embodiments, the conductive contact 140 is separated from the dielectric layer 170 by the semiconductor material layer 130.

FIG. 2 to FIG. 7 are cross-sectional views of a method of forming the semiconductor structure 10 of FIG. 1 at different stages according to some embodiments of the present disclosure.

Referring to FIG. 2 , a semiconductor substrate 100 is provided. In some embodiments, semiconductor substrate 100 comprises silicon. In other embodiments, semiconductor substrate 100 comprises other elemental semiconductors, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

Doped region 110 is formed on semiconductor substrate 100. Specifically, an implantation process is performed on the top portion of semiconductor substrate 100 to form doped region 110 in semiconductor substrate 100. Doped region 110 can be formed by implanting ions of an N-type or P-type dopant. An annealing process can then be performed to activate the implanted dopant in doped region 110. In some embodiments, doped region 110 is highly doped silicon (or heavily doped silicon). That is, in FIG1 and FIG2, in the embodiment where the semiconductor structure 10 includes an N-type transistor, the doping region 110 includes a high concentration of an N-type dopant; in the embodiment where the semiconductor structure 10 includes a P-type transistor, the doping region 110 includes a high concentration of a P-type dopant.

A gate structure 120 is formed on the semiconductor substrate 100. In some embodiments, a gate dielectric layer, a first gate electrode layer, and a second gate electrode layer are sequentially formed on the semiconductor substrate 100, and then the gate dielectric layer, the first gate electrode layer, and the second gate electrode layer are patterned to form a gate dielectric 121, a first gate electrode 122, and a second gate electrode 124. Then, a capping layer 126 is formed on the second gate electrode 124 and surrounds the gate dielectric 121, the first gate electrode 122, and the second gate electrode 124. In this way, the gate structure 120 including the gate dielectric 121, the first gate electrode 122, the second gate electrode 124, and the capping layer 126 is formed.

The gate dielectric 121 is formed on the semiconductor substrate 100 and comprises a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the gate dielectric 121 comprises a high-k dielectric material having a dielectric constant greater _than that of silicon oxide. Exemplary _high -k dielectric materials include, but are not limited to, helium oxide ( _HfO2 ), zirconium oxide ( _ZrO2 ), lutetium oxide ( _La2O3 ), aluminum oxide ( _Al2O3 ), titanium oxide ( _TiO2 ), strontium titanium oxide ( _SrTiO3 ), lutetium aluminum oxide ( _LaAlO3 ), and yttrium oxide ( _{Y2O3 )} . In some embodiments, the gate dielectric layer is formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition methods. In some embodiments, the gate dielectric layer is formed by converting a surface portion of the semiconductor substrate 100 using thermal oxidation.

A first gate electrode 122 is located on the gate dielectric 121, and a second gate electrode 124 is located on the first gate electrode 122. In some embodiments, the first gate electrode 122 and the second gate electrode 124 comprise different materials. The first gate electrode 122 comprises polysilicon, other suitable semiconductor materials, or other suitable conductive materials. The second gate electrode 124 comprises tungsten (W), titanium nitride (TiN), other suitable metals, other suitable metal nitrides, or other suitable conductive materials. In some embodiments, the first gate electrode layer and the second gate electrode layer are formed using, for example, ALD, CVD, PVD, or other suitable deposition methods.

A capping layer 126 is disposed on the second gate electrode 124 and surrounds the second gate electrode 124, the first gate electrode 122, and the gate dielectric 121. In some embodiments, the capping layer 126 comprises a nitride (e.g., silicon nitride) or other suitable dielectric material. In some embodiments, the capping layer 126 is formed using, for example, ALD, CVD, PVD, or other suitable deposition methods.

After forming the gate structure 120, a spacer structure 150 is formed on the opposite sidewalls 123 of the gate structure 120. In some embodiments, the spacer structure 150 includes an oxide (e.g., silicon dioxide) or other suitable dielectric material. In some embodiments, a method of forming the spacer structure 150 includes first depositing a spacer layer on the gate structure 120 and the exposed surface of the semiconductor substrate 100, and then etching the spacer layer to remove the horizontal portion of the spacer layer to form the spacer structure 150. In some embodiments, the spacer layer is formed using, for example, ALD, CVD, PVD, or other suitable deposition methods. The etching of the spacer layer can use a dry etching process such as reactive ion etching (RIE). The remaining vertical portion of the spacer layer on the sidewall 123 of the gate structure 120 constitutes a spacer structure 150 .

In some embodiments, the doped region 110 is formed in the semiconductor substrate 100 before the gate structure 120 is formed. In other embodiments, the doped region 110 is formed in the semiconductor substrate 100 after the gate structure 120 is formed. Specifically, after the gate structure 120 is formed on the semiconductor substrate 100, the spacer structure 150 is formed on opposite sidewalls of the gate structure 120. After the spacer structure 150 is formed, the doped region 110 is formed in the semiconductor substrate 100.

Referring to FIG. 2 and FIG. 3 , an etch-stop layer 160 is conformally formed over the structure of FIG. 2 . In some embodiments, the etch-stop layer 160 is conformally formed over the doped region 110 , the gate structure 120 , and the spacer structure 150 . The etch-stop layer 160 covers and contacts the doped region 110 , the gate structure 120 , and the spacer structure 150 . In some embodiments, the etch-stop layer 160 comprises a nitride (e.g., silicon nitride) or other suitable dielectric material. The etch-stop layer 160 and the capping layer 126 of the gate structure 120 may comprise the same material, such as a nitride (or silicon nitride). In some embodiments, the etch stop layer 160 is formed using ALD, CVD, PVD, or other suitable deposition methods.

Referring to FIG. 4 , after forming the etch stop layer 160 , a dielectric layer 170 is formed on the etch stop layer 160 . Specifically, the dielectric layer 170 is formed on the semiconductor substrate 100 and surrounds the gate structure 120 . The dielectric layer 170 contacts the etch stop layer 160 . The dielectric layer 170 may be considered an interlayer dielectric (ILD) layer. The dielectric layer 170 may be formed using CVD, high-density plasma chemical vapor deposition (HDPCVD), spin-on coating, sputtering, or other suitable methods. In some embodiments, the dielectric layer 170 includes an oxide (e.g., silicon dioxide) or other suitable dielectric material. In some embodiments, the dielectric layer 170 and the spacer structure 150 include the same material, such as oxide (or silicon dioxide).

Referring to FIG. 5 , after dielectric layer 170 is formed, an etching process E1 is performed to form at least one contact via 180 in dielectric layer 170, wherein contact via 180 exposes doped region 110. Specifically, etching process E1 is performed to form at least one contact via 180 between gate structure 120 and dielectric layer 170, thereby removing a portion of dielectric layer 170 and a portion of etch-stop layer 160. In other words, contact via 180 further penetrates etch-stop layer 160 to expose doped region 110. In some embodiments, the etching process E1 further includes removing a portion of the doped region 110 , such that the doped region 110 has an exposed surface 113 lower than the top surface 111 .

In some embodiments, the etching process E1 includes multiple etching processes. For example, the etching process E1 includes three etching processes performed sequentially, namely, etching the dielectric layer 170 , etching the etch stop layer 160 , and etching the doped region 110 .

In some embodiments, etching process E1 may utilize a dry etching process or a wet etching process. When a dry etching process is used, the process gas may include _CF4 , _CHF3 , _NF3 , SF6, _Br2 , HBr, _Cl2 , or a combination _thereof . A diluent gas such as _N2 , _O2 , or Ar _may optionally be used. When a wet etching process is used, the etching solution (etchant) may include _NH4OH : _H2O2 : _H2O (APM), _NH2OH , KOH, _HNO3 : _NH4F : _H2O , or other suitable etching solutions.

5 and 6 , a semiconductor material layer 130 is formed on the structure of FIG 5 . Specifically, the semiconductor material layer 130 is conformally formed on the top surface 171 of the dielectric layer 170 and on the contact via 180 . Specifically, the semiconductor material layer 130 is formed on the sidewalls 173 of the dielectric layer 170 , on the sidewalls of the etch stop layer 160 , and on the exposed surface 113 and sidewalls 115 of the doped region 110 . The semiconductor material layer 130 contacts the top surface 171 and sidewalls 173 of the dielectric layer 170, the sidewalls of the etch stop layer 160, and the exposed surface 113 and sidewalls 115 of the doped region 110. In some embodiments, as shown in FIG6 , after the contact via 180 is conformally covered with the semiconductor material layer 130, it is still not filled. The semiconductor material layer 130 only conforms to the contact via 180 along the sidewalls and bottom surface of the contact via 180. In some embodiments, the semiconductor material layer 130 includes polysilicon or other suitable semiconductor materials. The semiconductor material layer 130 can be formed using CVD, ALD, PVD, or other suitable deposition methods. In some embodiments, the semiconductor material layer 130 may be doped in-situ during the formation of the semiconductor material layer 130 .

6 and 7 , an etching process is performed to remove a portion of the semiconductor material layer 130, thereby separating the semiconductor material layer 130 from the surface 113 of the doped region 110. Specifically, the etching process is performed to remove a portion of the semiconductor material layer 130 located above the top surface 171 of the dielectric layer 170 and a portion of the semiconductor material layer 130 located above the surface 113 of the doped region 110, thereby exposing the top surface 171 of the dielectric layer 170 and the surface 113 of the doped region 110. In some embodiments, the etching process is performed to remove a portion of the semiconductor material layer 130 located on the sidewalls 115 of the doped region 110, leaving the remaining semiconductor material layer 130 in contact with the sidewalls 115 of the doped region 110. In some other embodiments, the etching process is performed to completely remove the portion of the semiconductor material layer 130 located on the sidewalls 115 of the doped region 110, leaving the semiconductor material layer 130 no longer in contact with (or separated from) the sidewalls 115 of the doped region 110.

In some embodiments, the etching process for etching the semiconductor material layer 130 includes a dry etching process, such as a plasma etching process. In some embodiments, the etching process includes an anisotropic etching process. The anisotropic etching process removes horizontal portions of the semiconductor material layer 130 (i.e., portions located on the top surface 171 of the dielectric layer 170 and the surface 113 of the doped region 110) while leaving vertical portions of the semiconductor material layer 130 (i.e., portions located on the sidewalls 173 of the dielectric layer 170). This allows the subsequently formed conductive contacts 140 to directly contact the doped region 110.

Returning to FIG. 1 (also see FIG. 7 ), after removing a portion of the semiconductor material layer 130 , a conductive material is filled into the contact via 180 to form a conductive contact 140 . Thus, the semiconductor structure 10 shown in FIG. 1 can be obtained.

In some embodiments, a portion of the semiconductor material layer 130 is removed before forming the conductive contact 140, thereby separating the semiconductor material layer 130 from the bottom surface 145 of the conductive contact 140 (or the surface 113 of the doped region 110). In other words, the conductive contact 140 contacts the semiconductor material layer 130, the surface 113 of the doped region 110, and the sidewalls 115. In some embodiments, the conductive contact 140 is separated from the dielectric layer 170 by the semiconductor material layer 130. Furthermore, the conductive contact 140 is separated from the etch stop layer 160 by the semiconductor material layer 130. In some embodiments, the conductive contact 140 comprises aluminum (Al) or other suitable conductive materials. The conductive contact 140 may be formed using CVD, ALD, PVD, or other suitable deposition methods.

In some embodiments, after forming the conductive contact 140 , a planarization process is performed to remove excess portions of the conductive contact 140 , so that the top surfaces of the dielectric layer 170 , the semiconductor material layer 130 , and the conductive contact 140 are substantially flush.

In summary, the semiconductor material layer disclosed herein is disposed on and contacts the sidewalls of the conductive contacts, thereby reducing the contact resistance of the conductive contacts and increasing the on-current, thereby improving the switching ratio of the device to meet the operating frequency requirements.

Although the present disclosure has been disclosed in the form of embodiments as described above, it is not intended to limit the present disclosure. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

10: Semiconductor Structure 100: Semiconductor Substrate 101, 111, 171: Top Surface 110: Doped Region 113: Surface 115, 123, 143, 147, 173: Sidewalls 120: Gate Structure 121: Gate Dielectric 122: First Gate Electrode 124: Second Gate Electrode 125, 145: Bottom Surface 126: Capping Layer 130: Semiconductor Material Layer 140: Conductive Contact 142: Bottom Section 144: Top Section 150: Spacer Structure 160: Etch Stop Layer 170: Dielectric layer 180: Contact via C1, C2: Curves E1: Etching process T1, T2: Thickness

To facilitate understanding of the above and other objects, features, advantages, and embodiments of the present disclosure, the accompanying drawings are described as follows: Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. Figures 2 through 7 are cross-sectional views of methods for forming a semiconductor structure at different stages according to some embodiments of the present disclosure. Figure 8 is a graph showing the relationship between current and voltage according to one embodiment of the present disclosure.

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10: Semiconductor Structure 100: Semiconductor Substrate 101, 111: Top Surface 110: Doped Region 113: Surface 115, 123, 143, 147, 173: Sidewalls 120: Gate Structure 121: Gate Dielectric 122: First Gate Electrode 124: Second Gate Electrode 125, 145: Bottom Surface 126: Capping Layer 130: Semiconductor Material Layer 140: Conductive Contact 142: Bottom Section 144: Top Section 150: Spacer Structure 160: Etch Stop Layer 170: Dielectric Layer T1, T2: Thickness

Claims (9)

A semiconductor structure includes: a semiconductor substrate including a doped region; a gate structure disposed on the semiconductor substrate; a conductive contact disposed on the doped region of the semiconductor substrate, wherein a bottom surface of the conductive contact is below a bottom surface of the gate structure; and a plurality of semiconductor material layers disposed on a plurality of sidewalls of the conductive contact, wherein each of the semiconductor material layers contacts the doped region. The semiconductor structure of claim 1, wherein the semiconductor material layers contact the sidewalls of the conductive contact. The semiconductor structure of claim 1, wherein the bottom surface of the conductive contact is separated from the semiconductor material layers. The semiconductor structure of claim 1 further comprises: a dielectric layer disposed on the semiconductor substrate and surrounding the gate structure and the conductive contact. The semiconductor structure of claim 1, wherein a top surface of each of the semiconductor material layers is substantially flush with a top surface of the conductive contact. The semiconductor structure of claim 1, wherein a thickness of the conductive contact between the semiconductor material layers is greater than a thickness of each of the semiconductor material layers. The semiconductor structure of claim 6, wherein a ratio of the thickness of each of the semiconductor material layers to the thickness of the conductive contact between the semiconductor material layers is in a range of 0.1 to 0.5. The semiconductor structure of claim 1, wherein the gate structure comprises: a gate dielectric contacting the semiconductor substrate; a first gate electrode disposed on the gate dielectric; a second gate electrode disposed on the first gate electrode; and a capping layer surrounding the gate dielectric, the first gate electrode, and the second gate electrode. The semiconductor structure of claim 1, wherein the conductive contact contacts a sidewall of the doped region.