[go: up one dir, main page]

TWI878725B - Plating system and method thereof - Google Patents

Plating system and method thereof Download PDF

Info

Publication number
TWI878725B
TWI878725B TW111135986A TW111135986A TWI878725B TW I878725 B TWI878725 B TW I878725B TW 111135986 A TW111135986 A TW 111135986A TW 111135986 A TW111135986 A TW 111135986A TW I878725 B TWI878725 B TW I878725B
Authority
TW
Taiwan
Prior art keywords
electroplating
current density
layer
plating
stage
Prior art date
Application number
TW111135986A
Other languages
Chinese (zh)
Other versions
TW202413737A (en
Inventor
何政恩
陳昱璉
王程麒
張又仁
呂勇聖
李承宇
林鈺銘
Original Assignee
元智大學
群創光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 元智大學, 群創光電股份有限公司 filed Critical 元智大學
Priority to TW111135986A priority Critical patent/TWI878725B/en
Priority to US18/231,099 priority patent/US20240102194A1/en
Publication of TW202413737A publication Critical patent/TW202413737A/en
Application granted granted Critical
Publication of TWI878725B publication Critical patent/TWI878725B/en

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/02Tanks; Installations therefor
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/12Process control or regulation
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/16Electroplating with layers of varying thickness
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48After-treatment of electroplated surfaces
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Automation & Control Theory (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A plating system and a method thereof are provided. The Mth plating layer is plated in the Nth stage to form on electrolyzation layer sequentially at drilling of substrate with the Mth current density during the Mth plating time, wherein N is a positive integer greater than or equal to 3, M is a positive integer from 1 to N. Therefore, the improving efficiency of filling rate at fixed total thickness of plating layer compared with prior art of plating filling may be achieved.

Description

電鍍系統及其方法Electroplating system and method thereof

一種電鍍系統及其方法,尤其是指一種透過不同電流密度進行多階段孔洞填補的電鍍系統及其方法。An electroplating system and method thereof, in particular, an electroplating system and method thereof for performing multi-stage hole filling by using different current densities.

為了滿足電子工業對元件更快速及小封裝體積的追求,三維積體電路(three-dimensional integrated circuits,3D IC)和多層印刷電路板(printed circuit boards,PCB)上的高密度互連(high density interconnection,HDI)技術在近年來受到電子工業高度關注。使用電鍍技術對孔洞填充(drilling filling),以形成貫穿各導線層的垂直線路即是其中的關鍵步驟。In order to meet the electronics industry's pursuit of faster components and smaller packaging volume, three-dimensional integrated circuits (3D IC) and high-density interconnection (HDI) technology on multi-layer printed circuit boards (PCB) have received great attention in the electronics industry in recent years. Using electroplating technology to fill holes (drilling filling) to form vertical lines that penetrate each conductor layer is a key step.

在孔洞的特殊形狀(近似U型)結構下,電鍍填孔製程在孔洞的孔口端的電流密度將高於底部區域,因此電鍍於孔洞的電鍍層高機率發生凹陷的不平整現象(即填孔率降低),電鍍層的平整度問題將影響後續製程(例如:疊孔)的良率。Due to the special shape of the hole (approximately U-shaped), the current density at the hole mouth of the electroplating hole filling process will be higher than that at the bottom area. Therefore, the electroplated layer electroplated in the hole is likely to be concave and uneven (i.e., the hole filling rate is reduced). The flatness of the electroplated layer will affect the yield of subsequent processes (such as stacking holes).

現有技術為了克服上述問題,即將電鍍時間特意延長以提高電鍍層的平整度(即提高填孔率),但隨著電鍍時間延長,電鍍層的總厚度會大幅增厚(大於15μm),以致無法符合高密度互連板(HDI-PCB)的現行產品規格(約12μm),故需要輔以蝕刻製程以減少電鍍層的總厚度。In order to overcome the above problems, the existing technology intentionally prolongs the electroplating time to improve the flatness of the electroplated layer (i.e., improve the hole filling rate). However, as the electroplating time is prolonged, the total thickness of the electroplated layer will be greatly increased (greater than 15μm), making it impossible to meet the current product specifications of high-density interconnect boards (HDI-PCB) (about 12μm). Therefore, an etching process is required to reduce the total thickness of the electroplated layer.

然而,利用蝕刻製程以減少電鍍層的總厚度卻也會在電鍍層的表面上蝕刻產生許多針孔(pin holes),針孔的產生會造成線路阻抗上升並且會破壞線路的機械特性。在極端的情況,若是許多針孔同時產生於相同的線路上時,則會導致細線路發生斷路的情況。However, using the etching process to reduce the total thickness of the electroplated layer will also produce many pin holes on the surface of the electroplated layer. The generation of pin holes will cause the line impedance to increase and destroy the mechanical properties of the line. In extreme cases, if many pin holes are generated on the same line at the same time, it will cause the thin line to be broken.

綜上所述,可知先前技術中長期以來一直存在考量填孔率導致電鍍層的電鍍厚度過厚,輔以蝕刻製程使電鍍層的表面產生針孔,造成線路阻抗上升並且會破壞線路的機械特性的問題,因此有必要提出改進的技術手段,來解決此一問題。In summary, it can be seen that the previous technology has long had the problem that the thickness of the electroplated layer is too thick due to the consideration of the hole filling rate, and the etching process causes pinholes on the surface of the electroplated layer, resulting in an increase in line impedance and damage to the mechanical properties of the line. Therefore, it is necessary to propose improved technical means to solve this problem.

有鑒於先前技術存在考量填孔率導致電鍍層的電鍍厚度過厚,輔以蝕刻製程使電鍍層的表面產生針孔,造成線路阻抗上升並且會破壞線路的機械特性的問題,本發明遂揭露一種電鍍系統及其方法,其中:In view of the fact that the prior art has the problem that the electroplating thickness of the electroplating layer is too thick due to the consideration of the hole filling rate, and the etching process causes pinholes to be generated on the surface of the electroplating layer, resulting in an increase in line impedance and damage to the mechanical properties of the line, the present invention discloses a plating system and method, wherein:

本發明所揭露的電鍍系統,其包含:基板、電源供應裝置以及電鍍槽。The electroplating system disclosed in the present invention includes: a substrate, a power supply device and an electroplating tank.

基板具有至少一孔洞,並於基板表面形成待鍍層,基板被以預處理程序進行清洗;電源供應裝置具有陰極與陽極,基板配置於陰極,電源供應裝置提供電鍍時的電源供應以及電流密度的調整;電鍍槽內放置具有金屬離子的電鍍液,基板以及陽極置入於電鍍槽中的電鍍液。The substrate has at least one hole, and a layer to be plated is formed on the surface of the substrate. The substrate is cleaned by a pre-treatment procedure. The power supply device has a cathode and an anode. The substrate is arranged on the cathode. The power supply device provides power supply and current density adjustment during electroplating. The electroplating tank is filled with a plating solution containing metal ions, and the substrate and the anode are placed in the electroplating solution in the electroplating tank.

其中,當電源供應裝置啟動並被設定以第M電流密度持續第M電鍍時間進行第M階段電鍍使至少一孔洞內的待鍍層上依序形成的第M電鍍層的N階段電鍍填孔製程,其中,N為大於等於3的正整數,M為1至N的正整數;及終止電源供應裝置的電源供應並將基板自電鍍液中取出進行清洗與乾燥製程。When the power supply device is started and set to perform the Mth stage electroplating at the Mth current density for the Mth electroplating time, an N-stage electroplating hole filling process of the Mth electroplating layer is sequentially formed on the layer to be plated in at least one hole, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N; and the power supply of the power supply device is terminated and the substrate is taken out of the electroplating solution for cleaning and drying processes.

本發明所揭露的電鍍方法,其包含下列步驟:The electroplating method disclosed in the present invention comprises the following steps:

首先,基板具有至少一孔洞,基板表面形成待鍍層;接著,對基板以預處理程序進行清洗;接著,電源供應裝置具有陰極與陽極,基板配置於陰極,電源供應裝置提供電鍍時的電源供應,且電源供應裝置提供電流密度的調整;接著,電鍍槽內放置具有金屬離子的電鍍液,基板以及陽極置入於電鍍槽中的電鍍液;接著,電源供應裝置啟動並被設定以第M電流密度持續第M電鍍時間進行第M階段電鍍使至少一孔洞內的待鍍層上依序形成的第M電鍍層的N階段電鍍填孔製程,其中,N為大於等於3的正整數,M為1至N的正整數;最後,終止電源供應裝置的電源供應並將基板自電鍍液中取出進行清洗與乾燥製程。First, the substrate has at least one hole, and a layer to be plated is formed on the surface of the substrate; then, the substrate is cleaned by a pre-treatment procedure; then, a power supply device has a cathode and an anode, the substrate is arranged on the cathode, the power supply device provides power supply during electroplating, and the power supply device provides adjustment of current density; then, a plating solution containing metal ions is placed in the electroplating tank, and the substrate and the anode are placed in the electroplating tank. liquid; then, the power supply device is started and set to perform the Mth stage electroplating at the Mth current density for the Mth electroplating time so that the Nth stage electroplating hole filling process of the Mth electroplating layer is sequentially formed on the layer to be plated in at least one hole, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N; finally, the power supply of the power supply device is terminated and the substrate is taken out of the electroplating solution for cleaning and drying processes.

本發明所揭露的系統及方法如上,與先前技術之間的差異在於基板的孔洞以第M電流密度持續第M電鍍時間進行第M階段電鍍於待鍍層上依序形成的第M電鍍層的N階段電鍍填孔製程,其中,N為大於等於3的正整數,M為1至N的正整數。The system and method disclosed in the present invention are as described above, and the difference between them and the prior art is that the hole of the substrate is subjected to an N-stage electroplating hole filling process in which the M-stage electroplating is performed on the layer to be plated by sequentially forming the M-stage electroplating layer on the layer to be plated at the M-stage current density for the M-stage electroplating time, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N.

透過上述的技術手段,本發明可以達成在電鍍層總厚度固定情況下相對於習知電鍍填孔技術能提高填孔率的技術功效。Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the hole filling rate compared to the conventional electroplating hole filling technology when the total thickness of the electroplated layer is fixed.

以下將配合圖式及實施例來詳細說明本發明的實施方式,藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施,並且本發明為了清楚的示意出各技術特徵,故而圖式中所示意的技術特徵部分將以較為誇示的示意作為呈現。The following will be used in conjunction with drawings and embodiments to explain the implementation of the present invention in detail, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. In order to clearly illustrate various technical features of the present invention, the technical features shown in the drawings will be presented in a more exaggerated manner.

以下首先要說明本發明所揭露的電鍍系統,並請參考「第1圖」以及「第2圖」所示,「第1圖」繪示為本發明電鍍系統的架構示意圖;「第2圖」繪示為本發明的基板剖視圖。The following first describes the electroplating system disclosed in the present invention, and please refer to "Figure 1" and "Figure 2". "Figure 1" is a schematic diagram of the structure of the electroplating system of the present invention; "Figure 2" is a cross-sectional view of the substrate of the present invention.

本發明所揭露的電鍍系統,其包含:基板10、電源供應裝置20以及電鍍槽30。The electroplating system disclosed in the present invention includes a substrate 10, a power supply device 20 and an electroplating tank 30.

基板10的厚度D可為但不限於0.2至3毫米(millimeter,mm),基板10可為BT基板、FR4基板、銅基板或ABF基板,基板10的材質可為但不限於玻璃纖維、環氧樹脂、聚苯醚樹脂(Polyphenylene Oxide,PPO)、聚醯亞胺(Polyimide,PI)、聚丙烯(Polypropylene,PP)的其中一種或多種混合。值得注意的是,基板10可為但不限於印刷電路板,透過雷射孔洞製程或機械孔洞製程於基板10形成至少一個孔洞11(圖式中僅以單一一個孔洞作為示意,並不以此侷限本發明的應用範疇),孔洞11的數量與位置可依據實際需求進行調整。當孔洞11為圓形孔洞(即其俯視圖為圓形)時,其孔徑(直徑)可為50μm至200μm,AR值(即縱橫比,基板10的厚度和孔徑的比值)可為0.5至4.0,在此僅為舉例說明之,並不以此侷限本發明的應用範疇。The thickness D of the substrate 10 may be, but not limited to, 0.2 to 3 millimeters (mm). The substrate 10 may be a BT substrate, a FR4 substrate, a copper substrate or an ABF substrate. The material of the substrate 10 may be, but not limited to, one or a mixture of glass fiber, epoxy resin, polyphenylene oxide resin (Polyphenylene Oxide, PPO), polyimide (Polyimide, PI), polypropylene (Polypropylene, PP). It is worth noting that the substrate 10 may be, but not limited to, a printed circuit board. At least one hole 11 is formed in the substrate 10 by a laser hole process or a mechanical hole process (only a single hole is used as an illustration in the figure, and the scope of application of the present invention is not limited thereto). The number and position of the hole 11 can be adjusted according to actual needs. When the hole 11 is a circular hole (i.e., its top view is circular), its pore size (diameter) can be 50 μm to 200 μm, and the AR value (i.e., the aspect ratio, the ratio of the thickness of the substrate 10 to the pore size) can be 0.5 to 4.0. This is only used as an example to illustrate, and the scope of application of the present invention is not limited thereto.

基板10可於雙面表面上形成待鍍層12,但本實施例並非用以限定本發明,可依據實際需求進行調整。舉例而言,基板10可僅於具有孔洞11的表面上形成待鍍層12。由於基板10為非導體,因此需要在其表面進行無電鍍製程、物理氣相沉積製程或化學氣相沉積製程,使基板10的表面具有導電層(即待鍍層12)。其中,待鍍層12的材質可選自於由銀、金、鎳、鈷、鈀與銅所構成的群組,可依據實際需求進行調整。The substrate 10 can form a layer 12 to be plated on both surfaces, but this embodiment is not intended to limit the present invention and can be adjusted according to actual needs. For example, the substrate 10 can form a layer 12 to be plated only on the surface having the hole 11. Since the substrate 10 is a non-conductor, it is necessary to perform an electroless plating process, a physical vapor deposition process or a chemical vapor deposition process on its surface so that the surface of the substrate 10 has a conductive layer (i.e., the layer 12 to be plated). Among them, the material of the layer 12 to be plated can be selected from the group consisting of silver, gold, nickel, cobalt, palladium and copper, and can be adjusted according to actual needs.

對基板10以預處理程序進行清洗,前述的預處理程序進行清洗可包含:依序以水、清潔劑與酸洗液清洗基板10與孔洞11所形成的待鍍層12,更詳細地說,預處理程序可清除待鍍層12上的污漬以及去除其表面的氧化層,且為避免清潔過程中有氣泡殘留於待鍍層12上。前述的水可為但不限於去離子水。需注意的是,由於後續進行電鍍,因此,當用以酸洗清潔的酸洗液不包含電鍍液所具有的離子時,為避免影響後續電鍍金屬的品質,可再次以水進行清洗。The substrate 10 is cleaned by a pre-treatment process. The pre-treatment process may include: sequentially cleaning the substrate 10 and the layer 12 to be deposited formed by the hole 11 with water, a cleaning agent and an acid cleaning solution. More specifically, the pre-treatment process can remove the stains on the layer 12 to be deposited and remove the oxide layer on its surface, and avoid bubbles remaining on the layer 12 to be deposited during the cleaning process. The water may be, but is not limited to, deionized water. It should be noted that, since electroplating is performed subsequently, when the acid cleaning solution used for pickling does not contain ions contained in the electroplating solution, in order to avoid affecting the quality of the subsequent electroplated metal, it may be cleaned again with water.

電源供應裝置20具有陰極21與陽極22,需將具有待鍍層12的基板10配置於陰極21的位置,而陽極22的位置可配置有溶解性陽極(即用於補充電鍍液中所消耗的金屬離子)或不溶性陽極(例如:鈦網、銥/鉭氧化物複合陽極…等,在此僅為舉例說明之,並不以此侷限本發明的應用範疇),在本實施例中,陽極22的材質可為但不限於銥/鉭氧化物複合不溶性陽極。The power supply device 20 has a cathode 21 and an anode 22. The substrate 10 with the layer 12 to be plated needs to be arranged at the position of the cathode 21, and the position of the anode 22 can be configured with a soluble anode (i.e., used to replenish the metal ions consumed in the plating solution) or an insoluble anode (for example: titanium mesh, iridium/titanium oxide composite anode...etc., which is only used as an example here and does not limit the scope of application of the present invention). In this embodiment, the material of the anode 22 can be but is not limited to an iridium/titanium oxide composite insoluble anode.

電源供應裝置20是提供基板10進行電鍍填孔製程時的電源供應以及電流密度的調整,具有金屬離子的電鍍液31被容置於電鍍槽30內,基板10以及電源供應裝置20的陽極22置入於電鍍槽30中的電鍍液31中,並當電源供應裝置20提供電源供應時,使基板10進行電鍍填孔製程,前述的金屬離子為銅離子以外的其他金屬離子,例如:銀離子、金離子、鎳離子、鈷離子以及鈀離子…等,在此僅為舉例說明之,並不以此侷限本發明的應用範疇,可依據預計生成的第M電鍍層的材質進行調整。The power supply device 20 is used to supply power and adjust the current density when the substrate 10 is subjected to the electroplating hole filling process. The electroplating solution 31 containing metal ions is contained in the electroplating tank 30. The substrate 10 and the anode 22 of the power supply device 20 are placed in the electroplating solution 31 in the electroplating tank 30. When the power supply device 20 provides power, the current density is adjusted. When the source is supplied, the substrate 10 is subjected to an electroplating hole filling process. The aforementioned metal ions are other metal ions other than copper ions, such as silver ions, gold ions, nickel ions, cobalt ions, and palladium ions, etc. This is only used as an example to illustrate the invention, and the scope of application of the invention is not limited thereto. The method can be adjusted according to the material of the Mth electroplating layer to be generated.

請參考「第3圖」所示,「第3圖」繪示為本發明多階段形成多層電鍍層示意圖,在圖式中雖以三層電鍍層(即三階段電鍍填孔製程作為示意),圖式中的示意並不以此侷限本發明的應用範疇。Please refer to "FIG. 3", which is a schematic diagram of the multi-stage formation of multiple electroplating layers of the present invention. Although three electroplating layers (i.e., a three-stage electroplating hole filling process) are used as an illustration in the figure, the illustration in the figure does not limit the scope of application of the present invention.

當電源供應裝置20啟動並被設定以第M電流密度持續第M電鍍時間進行第M階段電鍍使孔洞11內的待鍍層12上依序形成的第M電鍍層的N階段電鍍填孔製程,其中,N為大於等於3的正整數,M為1至N的正整數,以下將說明N為3以及M為1至3的實施例,在此僅為舉例說明之,並不以此侷限本發明的應用範疇。When the power supply device 20 is started and set to perform the Mth stage plating at the Mth current density for the Mth plating time, the Nth stage plating hole filling process of the Mth plating layer is sequentially formed on the layer to be plated 12 in the hole 11, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N. The following will describe an embodiment in which N is 3 and M is 1 to 3. This is only an example for illustration and is not intended to limit the scope of application of the present invention.

將電源供應裝置20調整電流密度為第一電流密度持續第一電鍍時間以對基板10的待鍍層12進行第一階段電鍍填孔製程,藉以使得孔洞11內的待鍍層12上形成第一電鍍層131。The power supply device 20 adjusts the current density to the first current density for the first electroplating time to perform the first stage electroplating hole filling process on the to-be-plated layer 12 of the substrate 10, so as to form a first electroplating layer 131 on the to-be-plated layer 12 in the hole 11.

接著,將電源供應裝置20調整電流密度為第二電流密度持續第二電鍍時間以在第一電鍍層131持續進行第二階段電鍍填孔製程,藉以使得孔洞11內的第一電鍍層131上形成第二電鍍層132。Next, the power supply device 20 adjusts the current density to the second current density and continues the second electroplating time to continue the second stage electroplating hole filling process on the first electroplating layer 131, so as to form the second electroplating layer 132 on the first electroplating layer 131 in the hole 11.

接著,將電源供應裝置20調整電流密度為第三電流密度持續第三電鍍時間以在第二電鍍層132持續進行第三階段電鍍填孔製程,藉以使得孔洞11內的第二電鍍層132上形成第三電鍍層133。Next, the power supply device 20 adjusts the current density to a third current density for a third plating time to continue the third stage of the plating hole filling process on the second plating layer 132, so as to form a third plating layer 133 on the second plating layer 132 in the hole 11.

本發明是先設定第M電流密度與對應的第M電鍍層預計的第M電鍍層的電鍍厚度THK,透過法拉第定律以分別計算出第M電流密度進行相對應階段的電鍍填孔製程時所需的第M電鍍時間,法拉第定律公式如下:The present invention first sets the Mth current density and the Mth electroplating thickness THK of the corresponding Mth electroplating layer, and calculates the Mth electroplating time required for the electroplating hole filling process at the corresponding stage at the Mth current density by using Faraday's law. The Faraday's law formula is as follows:

其中, t為第M電鍍時間(單位:分鐘), 為第M電鍍層的電鍍厚度(單位:μm), j為第M電流密度(單位:A/dm 2或ASD)。 Where, t is the Mth electroplating time (unit: minute), is the electroplating thickness of the Mth electroplating layer (unit: μm), j is the Mth current density (unit: A/ dm2 or ASD).

值得注意的是,每一階段電鍍填孔製程所使用的電流密度(即第一電流密度、第二電流密度以及第三電流密度)皆介於0.5至100ASD,且每一階段電鍍填孔製程所使用的電流密度為相同或是不相同。It is worth noting that the current density used in each stage of the electroplating hole filling process (i.e., the first current density, the second current density, and the third current density) is between 0.5 and 100 ASD, and the current density used in each stage of the electroplating hole filling process is the same or different.

在N為3以及M為1至3的實施例中,第二階段電鍍被設定的第二電流密度為第一階段電鍍被設定的第一電流密度增加 ,第三階段電鍍被設定的第三電流密度為第二階段電鍍被設定的第二電流密度的 ,具體而言,假設第一階段電鍍被設定的第一電流密度為1ASD時,第二階段電鍍被設定的第二電流密度可以是介於1.9至2.1ASD的範圍;假設第二階段電鍍被設定的第二電流密度為2ASD時,第三階段電鍍被設定的第三電流密度可以是0.4至0.6 ASD的範圍,在此僅為舉例說明之,並不以此侷限本發明的應用範疇。 In the embodiment where N is 3 and M is 1 to 3, the second current density set in the second stage electroplating is the first current density set in the first stage electroplating increased by The third current density set in the third stage of electroplating is equal to the second current density set in the second stage of electroplating. Specifically, assuming that the first current density of the first stage electroplating is set to 1ASD, the second current density of the second stage electroplating can be set to a range of 1.9 to 2.1ASD; assuming that the second current density of the second stage electroplating is set to 2ASD, the third current density of the third stage electroplating can be set to a range of 0.4 to 0.6 ASD. This is only used as an example to illustrate this, and the scope of application of the present invention is not limited thereto.

接著,以下將利用COMSOL-Multiphysics(version:6.0)進行電鍍填孔製程的電鍍模擬,請參考「第4圖」以及「第5A圖」至「第5E圖」所示,「第4圖」繪示為本發明填孔率示意圖;「第5A圖」至「第5E圖」繪示為使用不同電流密度進行單一階段電鍍填孔製程模擬結果圖。Next, COMSOL-Multiphysics (version: 6.0) will be used to perform electroplating simulation of the electroplating hole filling process. Please refer to "Figure 4" and "Figure 5A" to "Figure 5E". "Figure 4" is a schematic diagram of the hole filling rate of the present invention; "Figure 5A" to "Figure 5E" are simulation results of a single-stage electroplating hole filling process using different current densities.

本發明所述的填孔率為電鍍層表面最低位置至孔洞底部的距離b除以電鍍層表面最高位置至孔洞底部的距離a再乘以100%,即填孔率= ,如「第4圖」所示,值得注意的是,由於待鍍層12在實際上的厚度占比不高,故而在距離a以及距離b的計算過程可以忽略不計,距離a以及距離b也可以包含待鍍層12的厚度。 The filling rate of the present invention is the distance b from the lowest position of the electroplated layer surface to the bottom of the hole divided by the distance a from the highest position of the electroplated layer surface to the bottom of the hole multiplied by 100%, that is, the filling rate = As shown in "Figure 4", it is worth noting that since the actual thickness of the layer 12 to be deposited is not high, the calculation process of distance a and distance b can be ignored, and distance a and distance b can also include the thickness of the layer 12 to be deposited.

在「第5A圖」中使用單一電流密度為0.5ASD進行固定電鍍層的電鍍厚度為15μm的單一階段電鍍填孔製程,使用電流密度為0.5ASD電鍍填孔製程的電鍍時間模擬結果為136.36分鐘以及填孔率模擬結果為66.8%,填孔率66.8%即是由 計算得到。 In Figure 5A, a single-stage electroplating hole filling process with a fixed electroplating layer thickness of 15μm is performed using a single current density of 0.5ASD. The electroplating time simulation result of the electroplating hole filling process with a current density of 0.5ASD is 136.36 minutes and the hole filling rate simulation result is 66.8%. The hole filling rate of 66.8% is due to Calculated.

在「第5B圖」中使用單一電流密度為1ASD進行固定電鍍層的電鍍厚度為15μm的單一階段電鍍填孔製程,使用電流密度為1ASD電鍍填孔製程的電鍍時間模擬結果為68.18分鐘以及填孔率模擬結果為66.7%,填孔率66.7%即是由 計算得到。 In Figure 5B, a single-stage electroplating hole filling process with a fixed electroplating layer thickness of 15μm is performed using a single current density of 1ASD. The electroplating time simulation result of the electroplating hole filling process with a current density of 1ASD is 68.18 minutes and the hole filling rate simulation result is 66.7%. The hole filling rate of 66.7% is due to Calculated.

在「第5C圖」中使用單一電流密度為2ASD進行固定電鍍層的電鍍厚度為15μm的單一階段電鍍填孔製程,使用電流密度為2ASD電鍍填孔製程的電鍍時間模擬結果為34.09分鐘以及填孔率模擬結果為66.5%,填孔率66.5%即是由 計算得到。 In Figure 5C, a single-stage electroplating via filling process with a fixed electroplating layer thickness of 15μm is performed using a single current density of 2ASD. The electroplating time simulation result of the electroplating via filling process with a current density of 2ASD is 34.09 minutes and the via filling rate simulation result is 66.5%. The via filling rate of 66.5% is obtained by Calculated.

在「第5D圖」中使用單一電流密度為5ASD進行固定電鍍層的電鍍厚度為15μm的單一階段電鍍填孔製程,使用電流密度為5ASD電鍍填孔製程的電鍍時間模擬結果為13.63分鐘以及填孔率模擬結果為66%,填孔率66%即是由 計算得到。 In Figure 5D, a single-stage electroplating via filling process with a fixed electroplating layer thickness of 15μm is performed using a single current density of 5ASD. The simulation result of the electroplating time of the via filling process with a current density of 5ASD is 13.63 minutes and the simulation result of the via filling rate is 66%. The via filling rate of 66% is obtained by Calculated.

在「第5E圖」中使用單一電流密度為10ASD進行固定電鍍層的電鍍厚度為15μm的單一階段電鍍填孔製程,使用電流密度為10ASD電鍍填孔製程的電鍍時間模擬結果為6.81分鐘以及填孔率模擬結果為64.5%,填孔率64.5%即是由 計算得到。 In Figure 5E, a single-stage electroplating via filling process with a fixed electroplating layer thickness of 15μm is performed using a single current density of 10ASD. The electroplating time simulation result of the electroplating via filling process with a current density of 10ASD is 6.81 minutes and the via filling rate simulation result is 64.5%. The via filling rate of 64.5% is obtained by Calculated.

由上述模擬結果可以得到,使用高電流密度(例如:10ASD)進行電鍍填孔製程相比使用低電流密度(例如:1ASD)進行電鍍填孔製程形成固定電鍍層的電鍍厚度15μm所需要的電鍍時間減少許多,但使用高電流密度(例如:10ASD)進行電鍍填孔製程相比使用低電流密度(例如:1ASD)進行電鍍填孔製程形成固定電鍍層的電鍍厚度15μm的填孔率則下降許多,故而使用高電流密度(例如:5ASD、10ASD…等)將不利於孔洞填孔率的改善。From the above simulation results, it can be concluded that the electroplating time required to form a fixed electroplating layer with an electroplating thickness of 15μm using a high current density (e.g. 10ASD) is much shorter than that using a low current density (e.g. 1ASD) for the electroplating hole filling process. However, the filling rate of the hole filling process using a high current density (e.g. 10ASD) is much lower than that using a low current density (e.g. 1ASD) for the electroplating hole filling process to form a fixed electroplating layer with an electroplating thickness of 15μm. Therefore, using a high current density (e.g. 5ASD, 10ASD, etc.) will not be conducive to the improvement of the hole filling rate.

請參考「第6A圖」以及「第6B圖」所示,「第6A圖」繪示為使用單一電流密度進行單一階段電鍍填孔製程模擬結果圖;「第6B圖」繪示為本發明使用不同電流密度進行填孔製程且各階段電鍍層的電鍍厚度相同的模擬結果圖。Please refer to "Figure 6A" and "Figure 6B", "Figure 6A" shows the simulation result of a single-stage electroplating hole filling process using a single current density; "Figure 6B" shows the simulation result of the present invention using different current densities to perform the hole filling process and the electroplating thickness of each stage of the electroplating layer is the same.

在「第6A圖」中使用單一電流密度為2ASD進行固定電鍍層的電鍍厚度為8μm的單一階段電鍍填孔製程,使用電流密度為2ASD電鍍填孔製程的電鍍時間模擬結果為18.2分鐘以及填孔率模擬結果為51%。In FIG. 6A , a single-stage electroplating hole filling process with a fixed electroplating layer thickness of 8 μm is performed using a single current density of 2ASD. The simulation result of the electroplating time for the electroplating hole filling process with a current density of 2ASD is 18.2 minutes and the simulation result of the hole filling rate is 51%.

在「第6B圖」中先使用第一電流密度為0.5ASD進行第一電鍍層的電鍍厚度為2.6μm的第一階段電鍍填孔製程,再使用第二電流密度為2ASD進行第二電鍍層的電鍍厚度為2.6μm的第二階段電鍍填孔製程,再使用第三電流密度為1ASD進行第三電鍍層的電鍍厚度為2.6μm的第三階段電鍍填孔製程,經過三階段電鍍填孔製程的電鍍時間模擬結果為42.42分鐘以及填孔率模擬結果為51.97%,值得注意的是,第一電鍍層的電鍍厚度、第二電鍍層的電鍍厚度以及第三電鍍層的電鍍厚度為相同,在此僅為舉例說明之,並不以此侷限本發明的應用範疇,事實上,第一電鍍層的電鍍厚度、第二電鍍層的電鍍厚度以及第三電鍍層的電鍍厚度也可以是各不相同,第一電鍍層的電鍍厚度、第二電鍍層的電鍍厚度以及第三電鍍層的電鍍厚度亦可以是部分相同部分不相同。In "Figure 6B", the first current density of 0.5ASD is used to perform the first stage electroplating hole filling process with a first electroplating layer thickness of 2.6μm, and then the second current density of 2ASD is used to perform the second stage electroplating hole filling process with a second electroplating layer thickness of 2.6μm, and then the third current density of 1ASD is used to perform the third stage electroplating hole filling process with a third electroplating layer thickness of 2.6μm. After the three-stage electroplating hole filling process, the electroplating time simulation result is 42.42 minutes and the hole filling time is 42.42 minutes. The rate simulation result is 51.97%. It is worth noting that the plating thickness of the first plating layer, the plating thickness of the second plating layer and the plating thickness of the third plating layer are the same. This is only used as an example to illustrate, and the application scope of the present invention is not limited to this. In fact, the plating thickness of the first plating layer, the plating thickness of the second plating layer and the plating thickness of the third plating layer may also be different, and the plating thickness of the first plating layer, the plating thickness of the second plating layer and the plating thickness of the third plating layer may also be partially the same and partially different.

請參考「第7A圖」以及「第7B圖」所示,「第7A圖」繪示為使用單一電流密度進行單一階段電鍍填孔製程模擬結果圖;「第7B圖」繪示為本發明使用不同電流密度進行填孔製程且各階段電鍍層的電鍍厚度相同的模擬結果圖。Please refer to "Figure 7A" and "Figure 7B", "Figure 7A" shows the simulation result of a single-stage electroplating hole filling process using a single current density; "Figure 7B" shows the simulation result of the present invention using different current densities to perform the hole filling process and the electroplating thickness of each stage of the electroplating layer is the same.

在「第7A圖」中使用單一電流密度為2ASD進行固定電鍍層的電鍍厚度為20μm的單一階段電鍍填孔製程,使用電流密度為2ASD電鍍填孔製程的電鍍時間模擬結果為45.45分鐘以及填孔率模擬結果為74%。In FIG. 7A , a single-stage electroplating via filling process with a fixed electroplating layer thickness of 20 μm is performed using a single current density of 2ASD. The simulation result of the electroplating time for the electroplating via filling process with a current density of 2ASD is 45.45 minutes and the simulation result of the via filling rate is 74%.

在「第7B圖」中先使用第一電流密度為0.5ASD進行第一電鍍層的電鍍厚度為6.7μm的第一階段電鍍填孔製程,再使用第二電流密度為2ASD進行第二電鍍層的電鍍厚度為6.7μm的第二階段電鍍填孔製程,再使用第三電流密度為1ASD進行第三電鍍層的電鍍厚度為6.7μm的第三階段電鍍填孔製程,經過三階段電鍍填孔製程的電鍍時間模擬結果為106.1分鐘以及填孔率模擬結果為77.07%,值得注意的是,第一電鍍層的電鍍厚度、第二電鍍層的電鍍厚度以及第三電鍍層的電鍍厚度相同,在此僅為舉例說明之,並不以此侷限本發明的應用範疇,事實上,第一電鍍層的電鍍厚度、第二電鍍層的電鍍厚度以及第三電鍍層的電鍍厚度也可以是各不相同,第一電鍍層的電鍍厚度、第二電鍍層的電鍍厚度以及第三電鍍層的電鍍厚度亦可以是部分相同部分不相同。In "Figure 7B", the first current density of 0.5ASD is used to perform the first stage electroplating hole filling process with a first electroplating layer thickness of 6.7μm, and then the second current density of 2ASD is used to perform the second stage electroplating hole filling process with a second electroplating layer thickness of 6.7μm, and then the third current density of 1ASD is used to perform the third stage electroplating hole filling process with a third electroplating layer thickness of 6.7μm. After the three-stage electroplating hole filling process, the plating time simulation result is 106.1 minutes and the hole filling time is 106.1 minutes. The rate simulation result is 77.07%. It is worth noting that the plating thickness of the first plating layer, the plating thickness of the second plating layer and the plating thickness of the third plating layer are the same. This is only used as an example to illustrate, and the application scope of the present invention is not limited to this. In fact, the plating thickness of the first plating layer, the plating thickness of the second plating layer and the plating thickness of the third plating layer may also be different, and the plating thickness of the first plating layer, the plating thickness of the second plating layer and the plating thickness of the third plating layer may also be partially the same and partially different.

接著,以下將說明本發明的電鍍方法,並請同時參考「第8圖」所示,「第8圖」繪示為本發明電鍍方法的方法流程圖。Next, the electroplating method of the present invention will be described below, and please refer to "Figure 8" at the same time, which is a method flow chart of the electroplating method of the present invention.

本發明電鍍方法,其包含下列步驟:The electroplating method of the present invention comprises the following steps:

首先,基板具有至少一孔洞,基板表面形成待鍍層(步驟101);接著,電源供應裝置具有陰極與陽極,基板配置於陰極,電源供應裝置提供電鍍時的電源供應,且電源供應裝置提供電流密度的調整(步驟102);接著,電鍍槽內放置有具有金屬離子的電鍍液,基板以及陽極置入於電鍍槽中的電鍍液(步驟103);接著,電源供應裝置啟動並被設定以第M電流密度持續第M電鍍時間進行第M階段電鍍使至少一孔洞內的待鍍層上依序形成的第M電鍍層,其中,N為大於等於3的正整數,M為1至N的正整數(步驟104);最後,終止電源供應裝置的電源供應並將基板自電鍍液中取出進行清洗與乾燥製程(步驟105)。First, a substrate has at least one hole, and a layer to be plated is formed on the surface of the substrate (step 101). Next, a power supply device has a cathode and an anode, and the substrate is disposed on the cathode. The power supply device provides power supply during electroplating, and the power supply device provides adjustment of current density (step 102). Next, a plating solution containing metal ions is placed in a plating tank, and the substrate and the anode are placed in the plating solution in the plating tank (step 10 3); then, the power supply device is started and set to perform the Mth stage electroplating with the Mth current density for the Mth electroplating time so that the Mth electroplating layer is sequentially formed on the layer to be plated in at least one hole, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N (step 104); finally, the power supply of the power supply device is terminated and the substrate is taken out of the electroplating solution for cleaning and drying processes (step 105).

綜上所述,可知本發明與先前技術之間的差異在於基板的孔洞以第M電流密度持續第M電鍍時間進行第M階段電鍍於待鍍層上依序形成的第M電鍍層的N階段電鍍填孔製程,其中,N為大於等於3的正整數,M為1至N的正整數。In summary, the difference between the present invention and the prior art is that the hole of the substrate is subjected to an N-stage electroplating hole filling process in which the M-th electroplating layer is sequentially formed on the layer to be plated by performing the M-th stage electroplating at the M-th current density for the M-th electroplating time, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N.

藉由此一技術手段可以來解決先前技術所存在考量填孔率導致電鍍層的電鍍厚度過厚,輔以蝕刻製程使電鍍層的表面產生針孔,造成線路阻抗上升並且會破壞線路的機械特性的問題,進而達成在電鍍層總厚度固定情況下相對於習知電鍍填孔技術能提高填孔率的技術功效。This technical means can be used to solve the problem of the previous technology that the electroplating thickness of the electroplated layer is too thick due to the consideration of the filling rate, and the etching process causes pinholes on the surface of the electroplated layer, resulting in an increase in line impedance and damage to the mechanical properties of the line. In addition, the technical effect of improving the filling rate compared to the conventional electroplating filling technology can be achieved when the total thickness of the electroplated layer is fixed.

雖然本發明所揭露的實施方式如上,惟所述的內容並非用以直接限定本發明的專利保護範圍。任何本發明所屬技術領域中具有通常知識者,在不脫離本發明所揭露的精神和範圍的前提下,可以在實施的形式上及細節上作些許的更動。本發明的專利保護範圍,仍須以所附的申請專利範圍所界定者為準。Although the implementation methods disclosed in the present invention are as above, the above contents are not used to directly limit the scope of patent protection of the present invention. Any person with ordinary knowledge in the technical field to which the present invention belongs can make some changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention. The scope of patent protection of the present invention shall still be defined by the scope of the attached patent application.

10:基板 11:孔洞 12:待鍍層 131:第一電鍍層 132:第二電鍍層 133:第三電鍍層 20:電源供應裝置 21:陰極 22:陽極 30:電鍍槽 31:電鍍液 a:距離 b:距離 D:厚度 THK:電鍍厚度 步驟 101:基板具有至少一孔洞,基板表面形成待鍍層 步驟 102:電源供應裝置具有陰極與陽極,基板配置於陰極,電源供應裝置提供電鍍時的電源供應,且電源供應裝置提供電流密度的調整 步驟 103:電鍍槽內放置有具有金屬離子的電鍍液,基板以及陽極置入於電鍍槽中的電鍍液 步驟 104:電源供應裝置啟動並被設定以第M電流密度持續第M電鍍時間進行第M階段電鍍使至少一孔洞內的待鍍層上依序形成的第M電鍍層,其中,N為大於等於3的正整數,M為1至N的正整數 步驟 105:終止電源供應裝置的電源供應並將基板自電鍍液中取出進行清洗與乾燥製程 10: substrate 11: hole 12: layer to be plated 131: first electroplating layer 132: second electroplating layer 133: third electroplating layer 20: power supply device 21: cathode 22: anode 30: electroplating tank 31: electroplating solution a: distance b: distance D: thickness THK: electroplating thickness Step 101: the substrate has at least one hole, and the layer to be plated is formed on the surface of the substrate Step 102: the power supply device has a cathode and an anode, the substrate is arranged on the cathode, the power supply device provides power supply during electroplating, and the power supply device provides adjustment of current density Step 103: Plating solution containing metal ions is placed in the plating tank, and the substrate and the anode are placed in the plating solution in the plating tank. Step 104: The power supply device is started and set to perform the Mth stage plating at the Mth current density for the Mth plating time so that the Mth plating layer is sequentially formed on the layer to be plated in at least one hole, wherein N is a positive integer greater than or equal to 3, and M is a positive integer from 1 to N. Step 105: Terminate the power supply of the power supply device and take the substrate out of the plating solution for cleaning and drying processes.

第1圖繪示為本發明電鍍系統的架構示意圖。 第2圖繪示為本發明的基板剖視圖。 第3圖繪示為本發明多階段形成多層電鍍層示意圖。 第4圖繪示為本發明填孔率示意圖。 第5A圖至第5E圖繪示為使用不同電流密度進行單一階段電鍍填孔製程模擬結果圖。 第6A圖繪示為使用單一電流密度進行單一階段電鍍填孔製程模擬結果圖。 第6B圖繪示為本發明使用不同電流密度進行填孔製程且各階段電鍍層的電鍍厚度相同的模擬結果圖。 第7A圖繪示為使用單一電流密度進行單一階段電鍍填孔製程模擬結果圖。 第7B圖繪示為本發明使用不同電流密度進行填孔製程且各階段電鍍層的電鍍厚度相同的模擬結果圖。 第8圖繪示為本發明電鍍方法的方法流程圖。 FIG. 1 is a schematic diagram of the structure of the electroplating system of the present invention. FIG. 2 is a cross-sectional view of the substrate of the present invention. FIG. 3 is a schematic diagram of the multi-stage electroplating layer formed in the present invention. FIG. 4 is a schematic diagram of the hole filling rate of the present invention. FIG. 5A to FIG. 5E are simulation results of a single-stage electroplating hole filling process using different current densities. FIG. 6A is a simulation result of a single-stage electroplating hole filling process using a single current density. FIG. 6B is a simulation result of a hole filling process using different current densities and the electroplating thickness of the electroplating layer in each stage is the same. FIG. 7A shows the simulation result of a single-stage electroplating hole filling process using a single current density. FIG. 7B shows the simulation result of the present invention using different current densities to perform the hole filling process and the electroplating thickness of each stage of the electroplating layer is the same. FIG. 8 shows a method flow chart of the electroplating method of the present invention.

10:基板 10: Substrate

11:孔洞 11: Holes

12:待鍍層 12: Waiting for coating

20:電源供應裝置 20: Power supply device

21:陰極 21: cathode

22:陽極 22: Yang pole

30:電鍍槽 30: Electroplating tank

31:電鍍液 31: Plating solution

Claims (4)

一種電鍍方法,其包含下列步驟:一基板具有至少一孔洞,所述基板表面形成一待鍍層;一電源供應裝置具有一陰極與一陽極,所述基板配置於所述陰極,所述電源供應裝置提供電鍍時的電源供應,且所述電源供應裝置提供電流密度的調整;一電鍍槽內放置具有金屬離子的一電鍍液,所述基板以及所述陽極置入於所述電鍍槽中的電鍍液;所述電源供應裝置啟動並被設定以一第M電流密度持續一第M電鍍時間進行第M階段電鍍使所述至少一孔洞內的所述待鍍層上依序形成的一第M電鍍層,所述第M電鍍時間是以設定的所述第M電鍍層的電鍍厚度除以(0.22乘以所述第M電流密度)計算得到,其中,N為大於等於3的正整數,M為1至N的正整數,第二階段電鍍被設定的第二電流密度為第一階段電鍍被設定的第一電流密度增加100±10%,第三階段電鍍被設定的第三電流密度為第二階段電鍍被設定的第二電流密度的25±5%;及終止所述電源供應裝置的電源供應並將所述基板自所述電鍍液中取出進行清洗與乾燥製程。 A plating method comprises the following steps: a substrate having at least one hole, a layer to be plated is formed on the surface of the substrate; a power supply device having a cathode and an anode, the substrate being arranged on the cathode, the power supply device providing power supply during plating, and the power supply device providing adjustment of current density; a plating solution containing metal ions is placed in a plating tank, the substrate and the anode are placed in the plating solution in the plating tank; the power supply device is started and set to perform an Mth stage of plating with an Mth current density for an Mth plating time so that the layer to be plated in the at least one hole is sequentially plated. The Mth electroplating layer is formed, and the Mth electroplating time is calculated by dividing the set electroplating thickness of the Mth electroplating layer by (0.22 multiplied by the Mth current density), wherein N is a positive integer greater than or equal to 3, M is a positive integer from 1 to N, the second current density set for the second stage electroplating is 100±10% higher than the first current density set for the first stage electroplating, and the third current density set for the third stage electroplating is 25±5% of the second current density set for the second stage electroplating; and the power supply of the power supply device is terminated and the substrate is taken out of the electroplating solution for cleaning and drying processes. 如請求項1所述的電鍍方法,其中每一階段電鍍填孔製程的電流密度皆介於0.5至100A/dm2(ASD),且每一階段電鍍填孔製程的電流密度為不相同。 The electroplating method as claimed in claim 1, wherein the current density of each stage of the electroplating via filling process is between 0.5 and 100 A/dm 2 (ASD), and the current density of each stage of the electroplating via filling process is different. 如請求項1所述的電鍍方法,其中每一層電鍍層的電鍍厚度為相同或是不相同。 The electroplating method as described in claim 1, wherein the electroplating thickness of each electroplating layer is the same or different. 如請求項1所述的電鍍方法,其中所述金屬離子為銅離子以外的其他金屬離子。 The electroplating method as described in claim 1, wherein the metal ions are other metal ions other than copper ions.
TW111135986A 2022-09-22 2022-09-22 Plating system and method thereof TWI878725B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW111135986A TWI878725B (en) 2022-09-22 2022-09-22 Plating system and method thereof
US18/231,099 US20240102194A1 (en) 2022-09-22 2023-08-07 Plating system and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111135986A TWI878725B (en) 2022-09-22 2022-09-22 Plating system and method thereof

Publications (2)

Publication Number Publication Date
TW202413737A TW202413737A (en) 2024-04-01
TWI878725B true TWI878725B (en) 2025-04-01

Family

ID=90360005

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111135986A TWI878725B (en) 2022-09-22 2022-09-22 Plating system and method thereof

Country Status (2)

Country Link
US (1) US20240102194A1 (en)
TW (1) TWI878725B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102647862A (en) * 2012-04-25 2012-08-22 博敏电子股份有限公司 Blind via filling plating method using different current parameter combinations
CN104532318A (en) * 2014-12-31 2015-04-22 广州兴森快捷电路科技有限公司 Method for filling through hole by electroplating
TW202010370A (en) * 2018-08-09 2020-03-01 元智大學 High-speed electroplating method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102647862A (en) * 2012-04-25 2012-08-22 博敏电子股份有限公司 Blind via filling plating method using different current parameter combinations
CN104532318A (en) * 2014-12-31 2015-04-22 广州兴森快捷电路科技有限公司 Method for filling through hole by electroplating
TW202010370A (en) * 2018-08-09 2020-03-01 元智大學 High-speed electroplating method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
期刊 張劍如, 〝不同電流密度對直流電鍍填盲孔的影響研究〞, 印製電路資訊, 2013 No.4, p38~41. *

Also Published As

Publication number Publication date
TW202413737A (en) 2024-04-01
US20240102194A1 (en) 2024-03-28

Similar Documents

Publication Publication Date Title
TWI627886B (en) Preparation method of printed circuit board with ultra-thin metal layer
US10455704B2 (en) Method for copper filling of a hole in a component carrier
JP4477098B2 (en) Metal-coated polyimide composite, method for producing the composite, and apparatus for producing the composite
TWI697265B (en) High-speed electroplating method
KR20100024449A (en) Wiring substrate manufacturing method
JPH07336017A (en) Method of manufacturing thin film circuit by current reversal electrolysis method, thin film circuit board using the same, thin film multilayer circuit board and electronic circuit device
CN115369460B (en) Copper electroplating solution for filling micro blind holes
CN114928945B (en) Manufacturing process of superfine circuit printed circuit board
JP2005256159A (en) Method for forming copper plating film, continuous copper plating apparatus for resin film substrate for semiconductor package, and flexible copper-clad laminate
TWI878725B (en) Plating system and method thereof
JP4148477B2 (en) Sheet used for manufacturing multilayer wiring board, and plating method and plating apparatus used for manufacturing the sheet
JP4457843B2 (en) Circuit board manufacturing method
TWI877801B (en) Galvanic plating apparatus and method for galvanically plating a component carrier structure
JPH1143797A (en) Via filling method
CN117888154A (en) Ultrathin copper foil with carrier and manufacturing method for reducing pinholes of ultrathin copper foil
CN105862097B (en) HDI plate through-holes based on pulse technique fill out copper system system
JP2008218540A (en) Wiring board manufacturing method
KR102686710B1 (en) Method for fabricating circuit pattern of substrate using metal foil having low surface roughness
CN106416439B (en) Manufacturing method of substrate for wiring
CN119922832B (en) HDI circuit board manufacturing method, device and printed circuit board
JP2014027288A (en) Substrate for mounting semiconductor chip and method for manufacturing the same
KR20090123759A (en) Manufacturing method of flexible film
CN118829076A (en) A high frequency circuit board structure and manufacturing method thereof
JPH118469A (en) Via filling method
US20200006135A1 (en) Method and Plater Arrangement for Failure-Free Copper Filling of a Hole in a Component Carrier