TWI866669B - Photosensitive device and manufacturing method thereof - Google Patents

Abstract

A photosensitive device includes a first semiconductor layer, a first gate dielectric layer, a first gate electrode, an isolation structure, a first electrode, a second electrode, a second semiconductor layer, a third semiconductor layer, a second gate dielectric layer, a second gate, a third gate and a photosensitive element. The first gate dielectric layer is located on the first semiconductor layer. The first gate is located on the first gate dielectric layer. The isolation structure is located on the first gate and includes first, second and third through holes. The first and second electrodes are located on the isolation structure. The second semiconductor layer extends from the first electrode into the first through hole. The third semiconductor layer extends from the second electrode into the third through hole. The second gate dielectric layer covers the second and third semiconductor layers. The second and third gate electrodes are located on the second gate dielectric layer. The photosensitive element is electrically connected to the first gate.

Description

Photosensitive device and manufacturing method thereof

The present invention relates to a photosensitive device and a manufacturing method thereof.

X-ray detectors are often used to observe the interior of an object. They can measure the amount of X-rays that penetrate the object and display the internal conditions of the object through a display device. Common X-ray detectors can be divided into indirect energy conversion type and direct energy conversion type. Among them, the indirect energy conversion type has advantages such as high conversion efficiency, so it is the mainstream on the market. Indirect energy conversion type X-ray detectors use a scintillator to convert X-rays into light with other wavelengths (such as visible light), and then use a photosensitive device to convert the light signal into an electrical signal. With the increase in the demand for image resolution, how to improve the fill factor of the photosensitive device has become a problem that many researchers are committed to solving.

The present invention provides a photosensitive device and a manufacturing method thereof, wherein the photosensitive device has the advantage of a high filling factor.

At least one embodiment of the present invention provides a photosensitive device, comprising a first semiconductor layer, a first gate dielectric layer, a first gate electrode, an isolation structure, a first electrode, a second electrode, a second semiconductor layer, a third semiconductor layer, a second gate dielectric layer, a second gate electrode, a third gate electrode and a photosensitive element. The first semiconductor layer is located on a substrate. The first gate dielectric layer is located on the first semiconductor layer. The first gate electrode is located on the first gate dielectric layer. The isolation structure is located on the first gate electrode and comprises a first through hole, a second through hole and a third through hole. The first through hole and the second through hole overlap the first gate in the normal direction of the top surface of the substrate, and the third through hole overlaps the first semiconductor layer in the normal direction. The first electrode and the second electrode are located on the isolation structure. The second semiconductor layer extends from the first electrode into the first through hole and is electrically connected to the first gate and the first electrode. The third semiconductor layer extends from the second electrode into the third through hole and is electrically connected to the first semiconductor layer and the second electrode. The second gate dielectric layer covers the second semiconductor layer and the third semiconductor layer. The second gate and the third gate are located on the second gate dielectric layer and are filled in the first through hole and the third through hole respectively. The photosensitive element is electrically connected to the first gate.

At least one embodiment of the present invention provides a method for manufacturing a photosensitive device, comprising the following steps: forming a first semiconductor layer on a substrate; forming a first gate dielectric layer and a first gate electrode on the first semiconductor layer, wherein the first gate electrode is located on the first gate dielectric layer; forming an isolation material layer on the first gate electrode and the first semiconductor layer; forming a first conductive layer on the isolation material layer; and patterning the first conductive layer to form a first electrode and a second electrode. Patterning an isolation material layer to form an isolation structure, wherein a first electrode and a second electrode are located on the isolation structure, and the isolation structure includes a first through hole, a second through hole, and a third through hole, wherein the first through hole and the second through hole overlap the first gate electrode in the normal direction of the top surface of the substrate, and the third through hole overlaps the first semiconductor layer in the normal direction. Forming a second semiconductor layer in the first through hole, and the second semiconductor layer is electrically connected to the first gate electrode and the first electrode. Forming a third semiconductor layer in the third through hole, and the third semiconductor layer is electrically connected to the first semiconductor layer and the second electrode. Forming a second gate dielectric layer on the second semiconductor layer and the third semiconductor layer. A second gate and a third gate are formed on the second gate dielectric layer, wherein the second gate and the third gate are respectively filled into the first through hole and the third through hole. A photosensitive element is formed, and the photosensitive element is electrically connected to the first gate.

FIG1A is a schematic top view of a photosensitive device 10A according to an embodiment of the present invention. FIG1B is a schematic cross-sectional view along line A-A' of FIG1A. Referring to FIG1A and FIG1B, the photosensitive device 10A includes a first semiconductor layer 110, a first gate dielectric layer 120, a first gate 130, an isolation structure 140, a first electrode 152, a second electrode 154, a second semiconductor layer 162, a third semiconductor layer 164, a second gate dielectric layer 170, a second gate 182, a third gate 184, and a photosensitive element PD.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The first semiconductor layer 110 is located on the substrate 100. In the present embodiment, the first semiconductor layer 110 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not released) may be additionally included between the first semiconductor layer 110 and the substrate 100. The buffer layer may include, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, organic insulating material or other suitable materials or a combination of the foregoing materials or a stack of the foregoing materials. In some embodiments, the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer.

The first semiconductor layer 110 may be a single-layer or multi-layer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example, indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination thereof) or other suitable materials.

The first semiconductor layer 110 includes a first conductive region 112, a channel region 114, and a second conductive region 116. The channel region 114 is located between the first conductive region 112 and the second conductive region 116 and overlaps the first gate dielectric layer 120 in the normal direction ND of the top surface of the substrate 100. The resistivity of the first conductive region 112 and the second conductive region 116 is lower than the resistivity of the channel region 114. In some embodiments, the first conductive region 112 and the second conductive region 116 contain dopants, and the first conductive region 112 and the second conductive region 116 are doped regions.

The first gate dielectric layer 120 is located on the first semiconductor layer 110. In some embodiments, the first gate dielectric layer 120 is aligned with the channel region 114 of the first semiconductor layer 110. In some embodiments, the material of the first gate dielectric layer 120 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide, organic insulating material or other suitable materials or a combination of the foregoing materials.

The first gate 130 is located on the first gate dielectric layer 120 and overlaps the channel region 114 in the normal direction ND. In some embodiments, the first gate 130 is aligned with the first gate dielectric layer 120. In some embodiments, the material of the first gate 130 includes, for example, chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel and other metals, the above alloys, the above metal oxides, the above metal nitrides or the above combinations or other conductive materials. The first gate 130 may have a single-layer structure or a multi-layer structure.

The isolation structure 140 is located on the first gate 130 and the first semiconductor layer 110. The isolation structure 140 includes a first through hole TH1, a second through hole TH2, and a third through hole TH3. The first through hole TH1 and the second through hole TH2 overlap the first gate 130 in the normal direction ND, and the third through hole TH3 overlaps the second conductive region 116 of the first semiconductor layer 110 in the normal direction ND.

In this embodiment, the isolation structure 140 includes a first isolation portion 142 and a second isolation portion 144. The first through hole TH1 and the second through hole TH2 are located in the first isolation portion 142 and are completely surrounded laterally by the first isolation portion 142. The third through hole TH3 is located in the second isolation portion 144 and is completely surrounded laterally by the second isolation portion 144. In some embodiments, the first isolation portion 142 contacts and covers at least a portion of the side surface of the first gate 130 and at least a portion of the side surface of the first gate dielectric layer 120.

In some embodiments, the first isolation portion 142 and the second isolation portion 144 are separated from each other. For example, the fourth through hole TH4 of the isolation structure 140 separates the first isolation portion 142 and the second isolation portion 144 from each other, and separates the first electrode 152 and the second electrode 154 from each other. In some embodiments, the fourth through hole TH4 is sandwiched between the first isolation portion 142 and the second isolation portion 144, but is not completely surrounded by the isolation structure 140 laterally.

In some embodiments, the material of the isolation structure 140 includes, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide, organic insulating materials or other suitable materials or combinations of the foregoing materials. In some embodiments, the material of the isolation structure 140 includes oxide (e.g., silicon oxide) and can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration in the second semiconductor layer 162 and the third semiconductor layer 164 during the manufacturing process. In some embodiments, the isolation structure 140 can have a single-layer structure or a multi-layer structure. When the isolation structure 140 has a multi-layer structure, an oxide layer (such as a silicon oxide layer) and a nitride layer (such as a silicon nitride layer) can be used in combination to optimize the performance of the photosensitive device 10A. For example, the oxide layer can be used as an oxygen storage/oxygen replenishment layer, and the nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

The first electrode 152 and the second electrode 154 are located on the isolation structure 140. In the present embodiment, the first electrode 152 and the second electrode 154 are located on the first isolation portion 142 and the second isolation portion 144, respectively, and are aligned with the first isolation portion 142 and the second isolation portion 144, respectively. In the present embodiment, the first electrode 152 has a plurality of through holes aligned with the first through hole TH1 and the second through hole TH2, respectively, and the second electrode 154 has a through hole aligned with the third through hole TH3. The gap between the first electrode 152 and the second electrode 154 is aligned with the fourth through hole TH4.

In some embodiments, the materials of the first electrode 152 and the second electrode 154 include, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The first electrode 152 and the second electrode 154 can each have a single-layer structure or a multi-layer structure.

The second semiconductor layer 162 is located on the first electrode 152, extends from the first electrode 152 into the first through hole TH1, and electrically connects the first gate 130 and the first electrode 152. In the present embodiment, the second semiconductor layer 162 contacts the top and side surfaces of the first electrode 152, the side surfaces of the first through hole TH1, and the top surface of the first gate 130. In the present embodiment, the second semiconductor layer 162 overlaps the first gate 130, the first gate dielectric layer 120, and the channel region 114 of the first semiconductor layer 110 in the normal direction ND. In some embodiments, the channel length (or effective channel length) of the second semiconductor layer 162 is substantially equal to the depth of the first through hole TH1, and the channel width is substantially equal to the perimeter of the first through hole TH1.

The third semiconductor layer 164 is located on the second electrode 154 and extends from the second electrode 154 into the third through hole TH3, and is electrically connected to the second conductive region 116 of the first semiconductor layer 110 and the second electrode 154. In the present embodiment, the third semiconductor layer 164 contacts the top and side surfaces of the second electrode 154, the side surfaces of the third through hole TH3, and the top surface of the second conductive region 116. In the present embodiment, the third semiconductor layer 164 overlaps the second conductive region 116 of the first semiconductor layer 110 in the normal direction ND. In some embodiments, the channel length (or effective channel length) of the third semiconductor layer 164 is substantially equal to the depth of the third through hole TH3, and the channel width is substantially equal to the perimeter of the third through hole TH3.

In this embodiment, in the top view, the second semiconductor layer 162 and the third semiconductor layer 164 are rectangular in shape, but the present invention is not limited thereto. In other embodiments, the second semiconductor layer 162 and the third semiconductor layer 164 are circular, elliptical, polygonal or other suitable geometric shapes.

In some embodiments, the material of the second semiconductor layer 162 and the third semiconductor layer 164 includes oxides of three or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (for example, metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), indium gallium oxide (InGO), and indium tungsten oxide (InWO)) or tungsten-based rare earth doped metal oxides (for example, Ln-IZO) or other suitable metal oxides or combinations of the above materials. The second semiconductor layer 162 and the third semiconductor layer 164 each have a single-layer structure or a multi-layer structure.

In this embodiment, the second semiconductor layer 162 and the third semiconductor layer 164 include the same material. The material of the second semiconductor layer 162 and the third semiconductor layer 164 may be the same as or different from the material of the first semiconductor layer 110.

The second gate dielectric layer 170 covers the second semiconductor layer 162 and the third semiconductor layer 164. The second gate dielectric layer 170 is filled in the fourth through hole TH4 of the isolation structure 140. In the present embodiment, the second gate dielectric layer 170 contacts the top and side surfaces of the first electrode 152, the top and side surfaces of the second electrode 154, the side surface of the second through hole TH2, the side surface of the fourth through hole TH4, and a portion of the top surface of the first semiconductor layer 110. In the present embodiment, the second gate dielectric layer 170 has a first opening O1 and a second opening O2. The first opening O1 is located in the second through hole TH2 and overlaps the first gate 130. The second opening O2 overlaps the first conductive region 112 of the first semiconductor layer 110.

In some embodiments, the material of the second gate dielectric layer 170 includes, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide, organic insulating materials, or other suitable materials or combinations of the foregoing materials. In some embodiments, the thickness of the second gate dielectric layer 170 is less than the thickness of the isolation structure 140, but the present invention is not limited thereto. In other embodiments, the thickness of the isolation structure 140 is less than or equal to the thickness of the second gate dielectric layer 170.

The second gate 182 and the third gate 184 are located on the second gate dielectric layer 170 and are filled in the first through hole TH1 and the third through hole TH3, respectively. The second semiconductor layer 162 is located between the sidewall of the first through hole TH1 and the second gate 182, and the third semiconductor layer 164 is located between the sidewall of the third through hole TH3 and the third gate 184. In this embodiment, in the normal direction ND, the second gate 182 and the third gate 184 overlap the channel region 114 and the second conductive region 116 of the first semiconductor layer 110, respectively.

The first transfer structure 185 and the second transfer structure 187 are located on the second gate dielectric layer 170. The first transfer structure 185 is filled into the first opening O1 and the second through hole TH2 and is electrically connected to the first gate 130. The second transfer structure 187 is filled into the second opening O2 and is electrically connected to the first conductive region 112 of the first semiconductor layer 110.

In some embodiments, the second gate 182, the third gate 184, the first transfer structure 185, and the second transfer structure 187 belong to the same conductive layer. The materials of the second gate 182, the third gate 184, the first transfer structure 185, and the second transfer structure 187 include, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The second gate 182, the third gate 184, the first transfer structure 185, and the second transfer structure 187 may each have a single-layer structure or a multi-layer structure.

In the present embodiment, at least one side wall of the orthographic projection pattern of the second semiconductor layer 162 on the substrate 100 (for example, corresponding to the left side wall or the right side wall of the second semiconductor layer 162 in FIG. 1B ) is located between at least one side wall of the orthographic projection pattern of the second gate 182 on the substrate 100 (for example, corresponding to the left side wall or the right side wall of the second gate 182 in FIG. 1B ) and the corresponding side wall of the orthographic projection pattern of the first electrode 152 on the substrate 100, thereby reducing the parasitic capacitance between the second gate 182 and the first electrode 152. Similarly, at least one sidewall of the orthographic projection pattern of the third semiconductor layer 164 on the substrate 100 is located between at least one sidewall of the orthographic projection pattern of the third gate 184 on the substrate 100 (e.g., corresponding to the left sidewall or the right sidewall of the third gate 184 in FIG. 1B ) and the corresponding sidewall of the orthographic projection pattern of the second electrode 154 on the substrate 100, thereby reducing the parasitic capacitance between the third gate 184 and the second electrode 154.

The photosensitive element PD is electrically connected to the first gate 130. In this embodiment, the photosensitive element PD includes a bottom electrode (the first transfer structure 185 in this embodiment), a top electrode (the third transfer structure 210 in this embodiment), and a photosensitive layer 190. The photosensitive layer 190 is located between the bottom electrode and the top electrode.

In some embodiments, the material of the photosensitive layer 190 includes, for example, silicon-rich oxide, silicon-rich nitride, silicon-rich oxynitride, silicon-rich carbide, silicon-rich oxycarbide, hydrogenated silicon-rich oxide, hydrogenated silicon-rich nitride, hydrogenated silicon-rich carbide, or a combination thereof, but the present invention is not limited thereto. In other embodiments, the photosensitive layer 190 includes a stacked layer of a P-type semiconductor and an N-type semiconductor, and the P-type semiconductor and the N-type semiconductor may optionally include an intrinsic semiconductor.

In this embodiment, the photosensitive element PD is located above the first gate dielectric layer 120 and the first gate electrode 130, and at least part of the photosensitive layer 190 overlaps the first gate dielectric layer 120 and the first gate electrode 130, but the present invention is not limited thereto. In other embodiments, the first transfer structure 185 extends from above the first gate electrode 130 to a position that does not overlap the first gate dielectric layer 120 and the first gate electrode 130 in the normal direction ND, and the photosensitive layer 190 does not overlap the first gate dielectric layer 120 and the first gate electrode 130, thereby reducing the adverse effects of the topographic undulations caused by the first gate dielectric layer 120 and the first gate electrode 130 on the photosensitive layer 190.

The cover layer 200 is located on the second gate 182, the third gate 184, the first transfer structure 185 and the second transfer structure 187, and laterally covers the photosensitive layer 190. In some embodiments, the material of the cover layer 200 includes, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide, organic insulating material or other suitable materials or a combination of the above materials. The cover layer 200 includes a first opening H1 and a second opening H2. The first opening H1 and the second opening H2 overlap the photosensitive layer 190 and the second transfer structure 187, respectively.

The third transfer structure 210 (the top electrode of the photosensitive element PD in this embodiment) is located on the cover layer 200 and is filled in the first opening H1 and the second opening H2. The photosensitive element PD is electrically connected to the second transfer structure 187 through the third transfer structure 210, and is further electrically connected to the first conductive region 112 of the first semiconductor layer 110. In some embodiments, the third transfer structure 210 can also be called a common signal line and is used to transmit a common voltage signal.

FIG1C is an equivalent circuit diagram of the photosensitive device 10A of FIG1B . Referring to FIG1B and FIG1C , the photosensitive device 10A substantially includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3. The first thin film transistor T1 includes a first semiconductor layer 110 and a first gate 130. The second thin film transistor T2 includes a second semiconductor layer 162 and a second gate 182. The third thin film transistor T3 includes a third semiconductor layer 164 and a third gate 184.

The first thin film transistor T1 can be used as a driving transistor. The first gate 130 of the first thin film transistor T1 is electrically connected to one end of the photosensitive element PD (i.e., the first transfer structure 185). The first conductive region 112 can be used as the first source/drain of the first thin film transistor T1 and is electrically connected to the second transfer structure 187. The first source/drain of the first thin film transistor T1 and the other end of the photosensitive element PD (i.e., the third transfer structure 210) are both used to receive the common voltage signal V_com. The second conductive region 116 can be used as the second source/drain of the first thin film transistor T1 and the first source/drain of the third thin film transistor T3.

The second thin film transistor T2 can be used as a reset transistor. The second gate 182 is used to receive the reset voltage signal V_reset. The first source/drain of the second thin film transistor T2 (i.e., the first gate 130) is electrically connected to one end of the photosensitive element PD (i.e., the first switching structure 185). The second source/drain of the second thin film transistor T2 (i.e., the first electrode 152) is electrically connected to the system bias terminal V_b.

The third thin film transistor T3 can be used as a read transistor. The third gate 184 is used to receive the scan line signal V_gate. The second source/drain (i.e., the second electrode 154) of the third thin film transistor T3 outputs the signal V_out.

In this embodiment, the first semiconductor layer 110 is a flat semiconductor layer with a higher manufacturing yield. Therefore, using the first semiconductor layer 110 as the semiconductor channel of the first thin film transistor T1 can obtain a more stable analog amplification effect. In addition, the vertically arranged second thin film transistor T2 and the third thin film transistor T3 have the advantage of high on current per unit area.

In this embodiment, the second thin film transistor T2 and the third thin film transistor T3 at least partially overlap the first thin film transistor T1, so the required area of the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 can be effectively reduced, thereby improving the filling factor of the photosensitive device 10A.

Figures 2A to 2J are cross-sectional schematic diagrams of a manufacturing method of the photosensitive device 10A of Figure 1B. Referring to Figures 2A to 2C, a first semiconductor layer 110' is formed on a substrate 100. A first gate dielectric layer 120 and a first gate electrode 130 are formed on the first semiconductor layer 110', wherein the first gate electrode 130 is located on the first gate dielectric layer 120.

Specifically, referring to FIG. 2A , a dielectric material layer 120’ is formed on the first semiconductor layer 110’. Then, a gate material layer 130’ is formed on the dielectric material layer 120’.

Referring to FIG. 2B , the gate material layer 130' is patterned to form the first gate 130. In some embodiments, a patterned photoresist layer (not shown) is formed on the gate material layer 130', and then the gate material layer 130' is etched using the patterned photoresist layer as a mask to form the first gate 130. In some embodiments, the method of patterning the gate material layer 130' includes dry etching or wet etching.

Referring to FIG. 2C , an etching process is performed on the dielectric material layer 120' using the first gate 130 or the patterned photoresist layer thereon as a mask to form the first gate dielectric layer 120. The first gate dielectric layer 120 is aligned with the first gate 130.

In some embodiments, the etching process of the first gate dielectric layer 120 is a dry etching process, and the gas used contains fluorine, such as carbon fluoride gas. During the etching process, the fluorine element dopes the exposed portion of the first semiconductor layer 110' to form the first conductive region 112 and the second conductive region 114. The portion of the first semiconductor layer 110' covered by the first gate dielectric layer 120 and not doped forms the channel region 114.

In some embodiments, over etching may occur on the first semiconductor layer 110, so that the top surfaces of the first conductive region 112 and the second conductive region 114 are slightly lower than the top surface of the channel region 114, but the present invention is not limited thereto.

Referring to FIG. 2D , an isolation material layer 140’ is formed on the first gate 130 and the first semiconductor layer 110. A first conductive layer 150’ is formed on the isolation material layer 140’. A patterned photoresist layer PR is formed on the first conductive layer 150’.

Referring to FIG. 2E , the first conductive layer 150' is patterned using the patterned photoresist layer PR as a mask to form a first electrode 152 and a second electrode 154. In some embodiments, the method of patterning the first conductive layer 150' includes dry etching or wet etching.

Referring to FIG. 2F , the first electrode 152 and the second electrode 154 are used as masks to pattern the isolation material layer 140' to form an isolation structure 140. In some embodiments, the method of patterning the isolation material layer 140' includes dry etching or wet etching.

In some embodiments, before or after the patterned isolation material layer 140', the patterned photoresist layer PR is removed by an ashing process or other suitable process (see FIG. 2D ).

Referring to FIG. 2G , a second semiconductor layer 162 is formed in the first through hole TH1 of the isolation structure 140, and the second semiconductor layer 162 is electrically connected to the first gate 130 and the first electrode 152. A third semiconductor layer 164 is formed in the third through hole TH3 of the isolation structure 140, and the third semiconductor layer 164 is electrically connected to the second conductive region 116 of the first semiconductor layer 110 and the second electrode 154.

In some embodiments, the method of forming the second semiconductor layer 162 and the third semiconductor layer 164 includes the following steps. First, one or more semiconductor material layers are deposited on the entire surface. Then, the one or more semiconductor material layers are patterned to simultaneously form the second semiconductor layer 162 and the third semiconductor layer 164.

In some embodiments, after forming the second semiconductor layer 162 and the third semiconductor layer 164, a first annealing process is performed to diffuse oxygen in the second semiconductor layer 162 and the third semiconductor layer 164 or the environment and store it in the isolation structure 140.

Referring to FIG. 2H , a second gate dielectric layer 170 is formed on the second semiconductor layer 162 and the third semiconductor layer 164. In some embodiments, a dielectric material layer is first formed on the entire surface, and then the dielectric material layer is patterned to form the second gate dielectric layer 170. The second gate dielectric layer 170 has a first opening O1 exposing the first gate 130 and a second opening O2 exposing the second conductive region 112.

Referring to FIG. 2I , a second gate 182, a third gate 184, a first transfer structure 185, and a second transfer structure 187 are formed on the second gate dielectric layer 170. In some embodiments, a conductive material layer is first formed on the entire surface, and then the conductive material layer is patterned to form the second gate 182, the third gate 184, the first transfer structure 185, and the second transfer structure 187.

Finally, please return to Figure 1B to form the photosensitive element PD and the covering layer 200.

FIG3 is a cross-sectional schematic diagram of a photosensitive device 10B according to an embodiment of the present invention. It must be noted that the embodiment of FIG3 uses the component numbers and partial contents of the embodiments of FIG1A to FIG1C, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, which will not be elaborated here.

3 , the photosensitive element PD of the photosensitive device 10B includes a top electrode 191, a photosensitive layer 190, and a bottom electrode (i.e., a first transfer structure 185), wherein the photosensitive layer 190 is located between the top electrode 191 and the bottom electrode. In this embodiment, the side surface of the top electrode 191 is aligned with the side surface of the photosensitive layer 190. The third transfer structure 210 is electrically connected to the top electrode 191 of the photosensitive element PD. In some embodiments, the shapes of the top electrode 191 and the photosensitive layer 190 are defined by the same mask, so the top electrode 191 and the photosensitive layer 190 have substantially the same vertical projection pattern on the substrate 100, and the sidewalls of the top electrode 191 are aligned with the sidewalls of the photosensitive layer 190. In this embodiment, the sidewalls of the photosensitive layer 190 are aligned with the sidewalls of the bottom electrode (i.e., the first transfer structure 185), but the present invention is not limited thereto. In other embodiments, the width of the bottom electrode (i.e., the first transfer structure 185) is greater than the width of the photolayer 190 and the width of the top electrode 191.

FIG4 is a cross-sectional schematic diagram of a photosensitive device 10C according to an embodiment of the present invention. It must be noted that the embodiment of FIG4 uses the component numbers and partial contents of the embodiment of FIG3, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Referring to FIG. 4 , the photosensitive layer 190 of the photosensitive element PD of the photosensitive device 10C does not overlap the first gate 130 and the first semiconductor layer 110 in the normal direction of the top surface of the substrate. More specifically, in the present embodiment, the photosensitive layer 190 does not overlap the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 in the normal direction of the top surface of the substrate, thereby avoiding the adverse effects of the topographic undulations caused by the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 on the photosensitive layer 190. In addition, since the interference of the topographic undulations is reduced, the photosensitive layer 190 in the present embodiment can be formed to have a larger area.

In summary, by setting up the isolation structure of the present invention, the area required for setting up the semiconductor layer can be reduced, thereby improving the filling factor of the photosensitive device.

10A, 10B, 10C: Photosensitive device

100: Substrate

110: First semiconductor layer

110’: first semiconductor layer

112: First conductive area

114: Channel area

116: Second conductive area

120: First gate dielectric layer

120’: Dielectric material layer

130: First gate

130’: Gate material layer

140: Isolation structure

140’: Isolation material layer

142: First isolation section

144: Second isolation section

150’: First conductive layer

152: First electrode

154: Second electrode

162: Second semiconductor layer

164: Third semiconductor layer

170: Second gate dielectric layer

182: Second Gate

184: The third gate

185: First transfer structure

187: Second transfer structure

190: Photosensitive layer

191: Top electrode

200: Covering layer

210: The third switching structure

H1: First opening

H2: Second opening

ND: Normal direction

O1: First opening

O2: Second opening

PD: Photosensitive element

PR: Patterned photoresist layer

T1: First thin film transistor

T2: Second thin film transistor

T3: The third thin film transistor

TH1: First through hole

TH2: Second through hole

TH3:Third through hole

TH4: Fourth through hole

V_b: System bias terminal

V_com: common voltage signal

V_gate: scanning line signal

V_out: output signal

V_reset: reset voltage signal

Figure 1A is a top view schematic diagram of a photosensitive device according to an embodiment of the present invention.

FIG1B is a schematic cross-sectional view along line A-A’ of FIG1A .

FIG1C is a schematic diagram of an equivalent circuit of the photosensitive device of FIG1B .

Figures 2A to 2I are cross-sectional schematic diagrams of the manufacturing method of the photosensitive device of Figure 1B.

Figure 3 is a cross-sectional schematic diagram of a photosensitive device according to an embodiment of the present invention.

Figure 4 is a top view schematic diagram of a photosensitive device according to an embodiment of the present invention.

10A: Photosensitive device

100: Substrate

110: First semiconductor layer

112: First conductive area

114: Channel area

116: Second conductive area

120: First gate dielectric layer

130: First gate

140: Isolation structure

142: First isolation section

144: Second isolation section

152: First electrode

154: Second electrode

162: Second semiconductor layer

164: Third semiconductor layer

170: Second gate dielectric layer

182: Second Gate

184: The third gate

185: First transfer structure

187: Second transfer structure

190: Photosensitive layer

200: Covering layer

210: The third switching structure

H1: First opening

H2: Second opening

ND: Normal direction

O1: First opening

O2: Second opening

PD: Photosensitive element

T1: First thin film transistor

T2: Second thin film transistor

T3: The third thin film transistor

TH1: First through hole

TH2: Second through hole

TH3:Third through hole

TH4: Fourth through hole

Claims (10)

A photosensitive device, comprising: A first semiconductor layer, located on a substrate; A first gate dielectric layer, located on the first semiconductor layer; A first gate, located on the first gate dielectric layer; An isolation structure, located on the first gate, and comprising a first through hole, a second through hole and a third through hole, wherein the first through hole and the second through hole overlap the first gate in a normal direction of the top surface of the substrate, and the third through hole overlaps the first semiconductor layer in the normal direction; A first electrode and a second electrode, located on the isolation structure; A second semiconductor layer extends from the first electrode into the first through hole and electrically connects the first gate and the first electrode; A third semiconductor layer extends from the second electrode into the third through hole and electrically connects the first semiconductor layer and the second electrode; A second gate dielectric layer covers the second semiconductor layer and the third semiconductor layer; A second gate and a third gate are located on the second gate dielectric layer and are filled into the first through hole and the third through hole respectively; and A photosensitive element is electrically connected to the first gate. The photosensitive device as described in claim 1, wherein the photosensitive element is located above the first gate dielectric layer and the first gate. The photosensitive device as described in claim 1, wherein the photosensitive element comprises: a bottom electrode located in the second through hole and electrically connected to the first gate; a top electrode; and a photosensitive layer located between the bottom electrode and the top electrode. A photosensitive device as described in claim 3, wherein the first semiconductor layer includes a first conductive region, a channel region and a second conductive region, wherein the channel region is located between the first conductive region and the second conductive region and overlaps the first gate dielectric layer in the normal direction, and the resistivity of the first conductive region and the second conductive region is lower than the resistivity of the channel region, wherein the top electrode is electrically connected to the first conductive region, and the third semiconductor layer is electrically connected to the second conductive region. A photosensitive device as described in claim 4, wherein the second semiconductor layer overlaps the channel region in the normal direction. A photosensitive device as described in claim 1, wherein the second gate dielectric layer is filled into a fourth through hole of the isolation structure and contacts the first semiconductor layer, and wherein the fourth through hole separates the first electrode and the second electrode from each other. A method for manufacturing a photosensitive device, comprising: Forming a first semiconductor layer on a substrate; Forming a first gate dielectric layer and a first gate electrode on the first semiconductor layer, wherein the first gate electrode is located on the first gate dielectric layer; Forming an isolation material layer on the first gate electrode and the first semiconductor layer; Forming a first conductive layer on the isolation material layer; Patterning the first conductive layer to form a first electrode and a second electrode; Patterning the isolation material layer to form an isolation structure, wherein the first electrode and the second electrode are located on the isolation structure, and the isolation structure includes a first through hole, a second through hole and a third through hole, wherein the first through hole and the second through hole overlap the first gate in a normal direction of the top surface of the substrate, and the third through hole overlaps the first semiconductor layer in the normal direction; Forming a second semiconductor layer in the first through hole, and the second semiconductor layer is electrically connected to the first gate and the first electrode; Forming a third semiconductor layer in the third through hole, and the third semiconductor layer is electrically connected to the first semiconductor layer and the second electrode; A second gate dielectric layer is formed on the second semiconductor layer and the third semiconductor layer; A second gate and a third gate are formed on the second gate dielectric layer, wherein the second gate and the third gate are respectively filled into the first through hole and the third through hole; and A photosensitive element is formed, and the photosensitive element is electrically connected to the first gate. The manufacturing method as described in claim 7, wherein the isolation material layer is patterned using the first electrode and the second electrode as masks to form the isolation structure, wherein the isolation structure includes a first isolation portion and a second isolation portion separated from each other, and the first electrode and the second electrode are aligned with the first isolation portion and the second isolation portion, respectively. The manufacturing method as described in claim 7, wherein the method for forming the first gate dielectric layer and the first gate comprises: forming a dielectric material layer on the first semiconductor layer; forming a gate material layer on the dielectric material layer; patterning the gate material layer to form the first gate; and An etching process is performed on the dielectric material layer using the first gate as a mask to form the first gate dielectric layer, wherein the etching process forms a first conductive region, a channel region and a second conductive region in the first semiconductor layer, wherein the channel region is located between the first conductive region and the second conductive region and overlaps the first gate dielectric layer in the normal direction, and the resistivity of the first conductive region and the second conductive region is lower than the resistivity of the channel region. A manufacturing method as described in claim 7, wherein the second semiconductor layer and the third semiconductor layer are formed simultaneously.

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