TWI872000B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first and a second dielectric layer, a first and a second conductive structure, a first and a second via, and a polymer lining layer. The first conductive structure is in the first dielectric layer. The second conductive structure is in the first dielectric layer and is spaced apart the first conductive structure. The first via is over the first conductive structure. The second via is over the second conductive structure. The polymer spacing layer laterally surrounds the second via. The first via has a first size at a cross-section, the polymer lining layer and the second via has a second size collectively at the cross-section, and the second size is greater than the first size. A width of the first via is greater than a width of the second via. The second dielectric layer laterally surrounds the first via and the polymer lining layer and is separated from the second via from the polymer lining layer.

Description

Semiconductor device and method for manufacturing the same

Some embodiments of the present disclosure relate to semiconductor devices and methods of making the same.

In the back end of line (BEOL) process of semiconductor devices, interconnect structures are formed on the device layer of the wafer. The interconnect structures can be used to provide electrical connections between different devices (such as transistors). The interconnect structures can include multiple metal layers and vias connecting different metal layers.

Some embodiments of the present disclosure provide a semiconductor device, comprising a first dielectric layer, a first conductive structure, a second conductive structure, a first through-hole component, a second through-hole component, a polymer liner layer, and a second dielectric layer. The first conductive structure is located in the first dielectric layer. The second conductive structure is located in the first dielectric layer and is separated from the first conductive structure. The first through-hole component is located on the first conductive structure. The second through-hole component is located on the second conductive structure. The polymer liner layer laterally surrounds the second through-hole component, wherein the first through-hole component has a first size in a cross-section, the sum of the polymer liner layer and the second through-hole component has a second size in a cross-section, the second size is greater than the first size, and the width of the first through-hole component is greater than the width of the second through-hole component. And, the second dielectric layer laterally surrounds the first through-hole component and the polymer liner layer, wherein the second dielectric layer contacts the first through-hole component and is separated from the second through-hole component by the polymer liner layer.

In some embodiments, the width of the polymer pad layer becomes narrower as it is farther away from the first dielectric layer, so that the bottom surface of the polymer pad layer is wider than the top surface of the polymer pad layer, and the bottom surface of the polymer pad layer contacts the top surface of the first dielectric layer and the top surface of the second conductive structure.

In some embodiments, a width of the second through-hole member is different from that of the second conductive structure.

In some embodiments, a side surface of the polymer pad layer forms an angle with an upper surface of the second conductive structure, and the angle is between 65 degrees and 75 degrees.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising forming a first conductive structure and a second conductive structure in a first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a first through-hole opening and a second through-hole opening in the second dielectric layer, wherein the first through-hole opening exposes the first conductive structure, and the second through-hole opening exposes the second conductive structure, and forming a polymer layer in the first through-hole opening and the second through-hole opening, wherein the polymer layer is formed in the first through-hole opening. The thickness of the first portion of the opening is less than the thickness of the second portion of the polymer layer in the second through-hole opening, an etching process is performed on the first portion and the second portion of the polymer layer to completely remove the first portion of the polymer layer, while the second portion of the polymer layer remains after the etching process, and after performing the etching process, metal material is filled in the first through-hole opening and the second through-hole opening to form a first through-hole in the first through-hole opening and a second through-hole in the second through-hole opening.

In some embodiments, when forming the polymer layer, the polymer layer in the second via opening is thicker than the polymer layer in the first via opening.

In some embodiments, forming the polymer layer comprises using a gas to deposit the polymer layer, and the gas comprises hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or a combination thereof.

In some embodiments, performing the etching process includes using a gas having a high fluorine ratio.

In some embodiments, the first through-hole member and the second through-hole member have different widths.

In some embodiments, the width of the second portion of the polymer layer becomes narrower as it is farther away from the first dielectric layer, so that the bottom surface of the second portion of the polymer layer is wider than the top surface of the second portion of the polymer layer, and the bottom surface of the second portion of the polymer layer contacts the top surface of the first dielectric layer and the top surface of the second conductive structure.

In summary, some embodiments of the present disclosure can be used to form through-hole components of different sizes in the same process. Specifically, a photoresist layer with openings of different sizes can be formed on a dielectric layer, and then a polymer layer can be deposited on the photoresist layer. When etching the dielectric layer, the polymer layer can be used to adjust the size of the opening to form through-hole components of different sizes.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner.

Some embodiments of the present disclosure are related to methods for adjusting the size of through-hole components by depositing polymers. Specifically, a photoresist layer with openings of different sizes may be formed on a dielectric layer, and then a polymer layer may be deposited on the photoresist layer. When etching the dielectric layer, the polymer layer may be used to adjust the size of the opening to form through-hole components of different sizes.

FIG. 1 to FIG. 8 are cross-sectional views of intermediate stages of the process of manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 , a first conductive structure 112, a second conductive structure 114, and a third conductive structure 116 are formed in a first dielectric layer 102. The first dielectric layer 102 may be formed on a component of a semiconductor device (e.g., a transistor, a diode, a capacitor, a resistor, or the like). Then, an etching process is used to form a plurality of openings in the first dielectric layer 102, and a suitable conductive material is filled in the openings to form the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 in the first dielectric layer 102. The first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 are not interconnected and are separated from each other by the first dielectric layer 102. The first dielectric layer 102 can provide electrical isolation between the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116. In some embodiments, the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 can be made of metal, such as copper, and the first dielectric layer 102 can be made of a low dielectric constant or ultra-low dielectric constant dielectric material, such as a dielectric material with a dielectric constant lower than 3.0.

In some embodiments, the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 may be metal lines in an interconnect structure in a semiconductor device, so that the bottom of the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 may be connected to other components in the semiconductor device, such as transistors, diodes, capacitors, resistors, or the like. Alternatively, the bottom of the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 may be connected to a via in the interconnect structure. The first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 may be located in different regions of the wafer, for example, in different peripheral circuit regions. Since the resistance values required for the through-hole components in different regions are different, the sizes (such as width) of the through-hole components in different regions are also different to meet the resistance values required for each region.

2 , an etch stop layer 122 is formed on the first conductive structure 112, the second conductive structure 114, the third conductive structure 116, and the first dielectric layer 102, so that the etch stop layer 122 completely covers the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116. In some embodiments, the etch stop layer 122 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In some embodiments, the etch stop layer 122 may be formed of a suitable material, such as silicon nitride, silicon carbide, silicon carbonitride, or the like.

3 , a second dielectric layer 124 is formed on the etch stop layer 122. In some embodiments, the second dielectric layer 124 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In some embodiments, the second dielectric layer 124 may be made of a low dielectric constant dielectric material, such as a dielectric material with a dielectric constant lower than 3.0. In some embodiments, the second dielectric layer 124 may be made of the same material as the first dielectric layer 102.

Referring to FIG. 4 , a photoresist layer PR is formed on the second dielectric layer 124, wherein the photoresist layer PR has a first opening O1, a second opening O2, and a third opening O3. Specifically, a photoresist material layer may be formed on the second dielectric layer 124. Then, the photoresist material layer may be exposed to a light-proof pattern, and the exposed photoresist material layer may be developed to form a photoresist layer PR having a pattern on the second dielectric layer 124, and the pattern includes a first opening O1, a second opening O2, and a third opening O3. The first opening O1 is located above the first conductive structure 112, the second opening O2 is located above the second conductive structure 114, and the third opening O3 is located above the third conductive structure 116. In some embodiments, the first opening O1, the second opening O2, and the third opening O3 may be formed with different sizes according to the width of the through-hole member to be formed later. For example, the first opening O1 and the second opening O2 are different in size, and the first opening O1 and the third opening O3 are the same in size. Specifically, the second opening O2 may be larger than the first opening O1 and the third opening O3. Therefore, the sidewalls of the first opening O1 and the third opening O3 may be aligned with the edges of the upper surfaces of the first conductive structure 112 and the third conductive structure 116, respectively. The sidewalls of the second opening O2 are not aligned with the edges of the upper surface of the second conductive structure 114, and the width of the second opening O2 is wider than the width of the upper surface of the second conductive structure 114.

Referring to FIG. 5 , the second dielectric layer 124 and the etch stop layer 122 are etched through the photoresist layer PR to form a first through-hole component opening VO1, a second through-hole component opening VO2, and a third through-hole component opening VO3 in the second dielectric layer 124 and the etch stop layer 122. In some embodiments, a first etching process may be performed to etch the second dielectric layer 124 through the photoresist layer PR, and then a second etching process may be performed to etch the etch stop layer 122 through the photoresist layer PR and the second dielectric layer 124 to form a first through-hole component opening VO1, a second through-hole component opening VO2, and a third through-hole component opening VO3 in the second dielectric layer 124 and the etch stop layer 122. Then, the photoresist layer PR may be removed by a suitable method, such as photoresist ashing. The first etching process and the second etching process may be dry etching, wet etching or a combination thereof.

The first through-hole opening VO1 exposes the first conductive structure 112, the second through-hole opening VO2 exposes the second conductive structure 114, and the third through-hole opening VO3 exposes the third conductive structure 116. The first through-hole opening VO1 has the same width as the first conductive structure 112, and the third through-hole opening VO3 has the same width as the third conductive structure 116, so that the sidewalls of the first through-hole opening VO1 and the third through-hole opening VO3 can be aligned with the edges of the upper surfaces of the first conductive structure 112 and the third conductive structure 116, respectively, and the first through-hole opening VO1 and the third through-hole opening VO3 do not expose the first dielectric layer 102. The width of the second through-hole opening VO2 is wider than the width of the second conductive structure 114, so the second through-hole opening VO2 exposes a portion of the first dielectric layer 102.

6 , a polymer layer 130 is formed on the upper surface of the second dielectric layer 124, in the first via opening VO1, the second via opening VO2, and the third via opening VO3. Specifically, a gas may be used to deposit the polymer layer 130. In some embodiments, the gas used to deposit the polymer layer 130 includes hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or a combination thereof.

When the polymer gas is deposited on the first through-hole opening VO1, the second through-hole opening VO2 and the third through-hole opening VO3, the amount of polymer gas deposited in the openings will be different due to the different opening sizes. For example, when the openings are relatively small, such as the first through-hole opening VO1 and the third through-hole opening VO3, the polymer gas is not easy to deposit in the openings. Therefore, the polymer layer 132 formed in the first through-hole opening VO1 and the third through-hole opening VO3 is thinner. When the openings are relatively large, such as the second through-hole opening VO2, the polymer gas is easy to deposit in the openings, and is also easy to accumulate at the corner formed by the sidewalls of the openings and the upper surface of the first dielectric layer 102 below. Thus, when the polymer layer 130 is formed, the polymer layer 134 in the second via opening VO2 is thicker than the polymer layer 132 in the first via opening VO1 and the third via opening VO3. The width of the second via opening VO2 also becomes smaller than the first via opening VO1 and the third via opening VO3. In addition, since the polymer gas is easily accumulated at the corner of the second via opening VO2, the width of the polymer layer 134 becomes narrower in the direction away from the first dielectric layer 102. Thus, after the polymer layer 130 is formed, the width of the second via opening VO2 is reduced, and an opening that gradually widens in the direction away from the first dielectric layer 102 is formed. When the polymer layer 130 is formed, the polymer layer 134 in the second via opening VO2 covers the upper surface of the first dielectric layer 102 , so that the bottom of the second via opening VO2 becomes narrower than the upper surface of the second conductive structure 114 .

Referring to FIG. 7 , an etching process is performed to remove the polymer layer 130 on the upper surface of the second dielectric layer 124, the bottom surfaces of the first through-hole opening VO1, the second through-hole opening VO2 and the third through-hole opening VO3, the polymer layer 132 on the side walls of the first through-hole opening VO1 and the third through-hole opening VO3, and partially remove the polymer layer 134 on the side walls of the second through-hole opening VO2 to form a polymer liner layer 136 on the side walls of the second through-hole opening VO2.

Specifically, the etching process in FIG. 7 performs side etching on the polymer layer 130 on the sidewalls of the first through-hole opening VO1, the second through-hole opening VO2, and the third through-hole opening VO3. Since the polymer layer 132 on the sidewalls of the first through-hole opening VO1 and the third through-hole opening VO3 is thinner, when the etching process in FIG. 7 is performed, the polymer layer 132 on the sidewalls of the first through-hole opening VO1 and the third through-hole opening VO3 is easily removed, thereby exposing the sidewalls of the second dielectric layer 124 and the etch stop layer 122. On the other hand, the polymer layer 134 in the second via opening VO2 is thicker, so the etching process only partially etches the polymer layer 134 on the sidewall of the second via opening VO2, and forms a polymer liner layer 136 on the sidewall of the second via opening VO2. During the etching process, the polymer liner layer 136 still covers the upper surface of the first dielectric layer 102, so that the second via opening VO2 still only exposes the second conductive structure 114. In this way, the polymer layer 130 can be used to manufacture via openings of different sizes in the same process. In some embodiments, a suitable etching gas can be used to perform etching, such as a gas with a high fluorine ratio, such as carbon tetrafluoride. Since the polymer layer 134 is a polymer layer stacked on the second via opening VO2, the sidewall of the polymer layer 134 and the upper surface of the second conductive structure 114 have an angle a. In some embodiments, the angle a is between 65 degrees and 75 degrees.

8 , metal material is filled in the first through-hole opening VO1 , the second through-hole opening VO2 and the third through-hole opening VO3 to form a first through-hole 142 in the first through-hole opening VO1 , a second through-hole 144 in the second through-hole opening VO2 and a third through-hole 146 in the third through-hole opening VO3 .

In this way, the semiconductor device is obtained as shown in FIG8. The semiconductor device may include a first dielectric layer 102, a first conductive structure 112, a second conductive structure 114, a third conductive structure 116, a first via 142, a second via 144, a third via 146, a polymer liner 136, and a second dielectric layer 124. The first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 are located in the first dielectric layer 102, and the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 are separated from each other by the first dielectric layer 102. The first via 142, the second via 144, and the third via 146 are respectively located on the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116. The polymer liner layer 136 laterally surrounds the second via 144. The second dielectric layer 124 laterally surrounds the first via 142, the third via 146, and the polymer liner layer 136. The second dielectric layer 124 contacts the first via 142 and is separated from the second via 144 by the polymer liner layer 136. In some embodiments, the semiconductor device further includes an etch stop layer 122. The etch stop layer 122 is located below the second dielectric layer 124 and above the first dielectric layer 102 , and contacts the polymer liner layer 136 .

The polymer liner layer 136 can be used to adjust the width of the through-hole opening. For example, the polymer liner layer 136 can be formed on the sidewall of the second through-hole opening VO2, so that the polymer liner layer 136 contacts the second conductive structure 114 and the first dielectric layer 102, thereby reducing the width of the second through-hole opening VO2. The widths of the first through-hole 142, the second through-hole 144, and the third through-hole 146 are thus different. For example, the widths of the first through-hole 142 and the third through-hole 146 are greater than the width of the second through-hole 144. The polymer liner layer 136 makes the bottom of the second via opening VO2 narrower than the second conductive structure 114, so the bottom width of the second via 144 is different from the width of the upper surface of the second conductive structure 114. The first via opening VO1 and the third via opening VO3 do not have the polymer liner layer, and the sidewalls of the first via opening VO1 and the third via opening VO3 are substantially aligned with the upper surface of the first conductive structure 112 and the upper surface of the third conductive structure 116, respectively. Therefore, the first via 142 and the third via 146 can be substantially aligned with the upper surface of the first conductive structure 112 and the upper surface of the third conductive structure 116, respectively. This allows vias of different sizes to be manufactured in the same process, reducing the complexity of the process. Vias of different sizes can be used in different areas of the wafer and provide specific resistance values for specific areas.

It should be noted that FIGS. 1 to 8 illustrate the process of manufacturing one layer of the conductive structure and the via member in the interconnection structure of the semiconductor device. After completing the process of FIG. 8, the process illustrated in FIGS. 1 to 8 may be repeated to form the conductive structure and the via member on the first via member 142, the second via member 144, and the third via member 146. In this way, the formation of the interconnection structure of the semiconductor device can be completed.

In summary, the process using the implementation method of the present disclosure can form through-hole component openings of different sizes in the same process. Specifically, the amount of polymer gas deposited in the opening will change according to the different opening sizes. For example, polymer gas is easily deposited in a wider opening and is not easy to deposit in a narrower opening. Therefore, through-hole component openings of different sizes can be formed in the dielectric layer first, and then polymer gas is deposited to form a polymer liner layer that can adjust the through-hole component opening. Then, through-hole components of different sizes can be formed. In this way, through-hole components of different sizes can be formed in the same process, so that the complexity of the process can be reduced.

Although the present disclosure has been disclosed in the form of implementation as above, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the attached patent application.

102: first dielectric layer 112: first conductive structure 114: second conductive structure 116: third conductive structure 122: etch stop layer 124: second dielectric layer 130: polymer layer 132: polymer layer 134: polymer layer 136: polymer liner layer 142: first through-hole component 144: second through-hole component 146: third through-hole component a: angle O1: first opening O2: second opening O3: third opening PR: photoresist layer VO1: first through-hole component opening VO2: second through-hole component opening VO3: third through-hole component opening

FIGS. 1 to 8 illustrate cross-sectional views of intermediate stages of a manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

102: first dielectric layer 112: first conductive structure 114: second conductive structure 116: third conductive structure 122: etch stop layer 124: second dielectric layer 136: polymer liner layer 142: first through-hole component 144: second through-hole component 146: third through-hole component a: angle

Claims (10)

A semiconductor device comprises: a first dielectric layer; a first conductive structure located in the first dielectric layer; a second conductive structure located in the first dielectric layer and separated from the first conductive structure; a first through-hole component located on the first conductive structure; a second through-hole component located on the second conductive structure; a polymer liner layer laterally surrounding the second through-hole component, wherein the first through-hole component has a first size in a cross-section, the sum of the polymer liner layer and the second through-hole component has a second size in the cross-section, the second size is larger than the first size, and the width of the first through-hole component is larger than the width of the second through-hole component; and A second dielectric layer laterally surrounds the first through-hole component and the polymer liner layer, wherein the second dielectric layer contacts the first through-hole component and is separated from the second through-hole component by the polymer liner layer. A semiconductor device as described in claim 1, wherein the width of the polymer pad layer becomes narrower as it is farther away from the first dielectric layer, so that a bottom surface of the polymer pad layer is wider than a top surface of the polymer pad layer, and the bottom surface of the polymer pad layer contacts a top surface of the first dielectric layer and a top surface of the second conductive structure. A semiconductor device as described in claim 1, wherein a width of the second through-hole member is different from that of the second conductive structure. A semiconductor device as described in claim 1, wherein a side surface of the polymer pad layer forms an angle with an upper surface of the second conductive structure, and the angle is between 65 degrees and 75 degrees. A method for manufacturing a semiconductor device, comprising: forming a first conductive structure and a second conductive structure in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a first through-hole opening and a second through-hole opening in the second dielectric layer, the first through-hole opening exposing the first conductive structure, and the second through-hole opening exposing the second conductive structure; forming a polymer layer in the first through-hole opening and the second through-hole opening, wherein a thickness of the polymer layer in a first portion of the first through-hole opening is less than a thickness of the polymer layer in a second portion of the second through-hole opening; Performing an etching process on the first portion and the second portion of the polymer layer to completely remove the first portion of the polymer layer, while the second portion of the polymer layer remains after the etching process; and After performing the etching process, filling a metal material in the first through-hole opening and the second through-hole opening to form a first through-hole in the first through-hole opening and a second through-hole in the second through-hole opening. The method of claim 5, wherein when forming the polymer layer, the polymer layer in the second via opening is thicker than the polymer layer in the first via opening. The method as described in claim 5, wherein when forming the polymer layer, the polymer layer is deposited using a gas, and the gas comprises hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane or a combination thereof. The method of claim 5, wherein performing the etching process comprises using a gas having a high fluorine ratio. A method as described in claim 5, wherein the width of the first through-hole member is different from that of the second through-hole member. A method as described in claim 5, wherein the width of the second portion of the polymer layer becomes narrower as it is farther away from the first dielectric layer, so that a bottom surface of the second portion of the polymer layer is wider than a top surface of the second portion of the polymer layer, and the bottom surface of the second portion of the polymer layer contacts a top surface of the first dielectric layer and a top surface of the second conductive structure.