TWI865111B - Method of forming contact plug - Google Patents

Abstract

A method of forming a contact plug includes: forming a block layer on a metal layer; forming an interlayer dielectric layer on the block layer; forming a first dielectric layer on the interlayer dielectric layer; forming a first opening in the first dielectric layer and the interlayer dielectric layer; forming an underlayer filling the first opening and covering the first dielectric layer; performing a plurality of etching processes to remove the underlayer and forming a contact opening in the first dielectric layer and the interlayer dielectric layer; and filling the contact opening with the contact plug. The etching processes include a flash etching process, which the performed prior to removing the underlayer such that the underlayer has a step gap in the first opening.

Description

Method for manufacturing contact plug

The present invention relates to a method for manufacturing a contact plug.

In the manufacture of integrated circuits, contact plugs (vias) are used to electrically couple different metal layers. These contact plug formation processes include: etching one or more dielectric layers to form contact openings in the dielectric layers to expose the underlying metal layers, filling one or more layers of metal into the contact openings, and performing a chemical mechanical polishing (CMP) process to remove excess metal.

However, if the etching precision is not well controlled during the process of etching the dielectric layer to form the contact opening, the surface of the dielectric layer will have bowl-shaped depressions or even fence-shaped protrusions, which will limit the metal filling capacity and affect the electrical properties of the contact plug.

One embodiment of the present invention provides a method for making a contact plug, including forming a blocking layer on a metal layer; forming an interlayer dielectric layer on the blocking layer; forming a first dielectric layer on the interlayer dielectric layer; forming a first opening in the first dielectric layer and the interlayer dielectric layer; forming a bottom layer filling the first opening and covering the first dielectric layer; performing a plurality of etching processes to remove the bottom layer and form a contact opening in the first dielectric layer and the interlayer dielectric layer, wherein the etching process includes a flash etching process, and the flash etching process is used to make the bottom layer have a step difference in the first opening before removing the bottom layer; and forming a contact plug to fill the contact opening.

In some embodiments, the first dielectric layer, the interlayer dielectric layer, and the bottom layer include different materials.

In some embodiments, the step difference is 35-45% of the thickness of the bottom layer covering the first dielectric layer.

In some embodiments, the method of manufacturing the contact plug further includes forming a bottom anti-reflective coating on the bottom layer, and the etching process includes a first etching process to partially remove the bottom anti-reflective coating to expose the bottom layer.

In some embodiments, the etching process includes a second etching process to partially remove the bottom layer to expose the first dielectric layer, wherein a portion of the bottom layer is still filled in the first opening and surrounded by the first dielectric layer.

In some embodiments, the etching process includes a third etching process to partially remove the bottom layer so that a top surface of the bottom layer is between a top surface of the first dielectric layer and a top surface of the interlayer dielectric layer.

In some embodiments, the etching process includes a fourth etching process for partially removing the first dielectric layer to expose the interlayer dielectric layer, wherein the flash etching process is performed subsequent to the fourth etching process.

In some embodiments, the etching process includes a sixth etching process to partially remove the interlayer dielectric layer and the bottom layer after the flash etching process to form a second opening in the interlayer dielectric layer.

In some embodiments, the etching process includes a seventh etching process to remove the bottom layer so that the first opening is connected to the second opening to serve as a contact opening.

In some embodiments, the process pressure of the flash etching process is 13-17 mT, and the etching gas of the flash etching process includes CO ₂ , and the flow rate of CO ₂ is 360-440 sccm.

Since different etching processes are used when etching the first dielectric layer and the interlayer dielectric layer, and a flash etching process is inserted to pre-make a step between the bottom layer filled in the first opening and the interlayer dielectric layer as a buffer, the etched interlayer dielectric layer has a flatter top surface, and the profile of the contact opening is therefore flatter.

The following will clearly illustrate the spirit of the present invention with drawings and detailed descriptions. After understanding the preferred embodiments of the present invention, any person having ordinary knowledge in the relevant technical field can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

In order to solve the problem that the surface of the dielectric layer has bowl-shaped depressions or even fence-shaped protrusions due to poor etching precision control in the process of etching the dielectric layer to form a contact opening, one embodiment of the present invention provides a method for manufacturing a contact plug, which improves the metal filling capability of the contact plug by etching the dielectric layer in multiple stages.

Referring to FIG. 1 to FIG. 25, they are schematic diagrams of a method of manufacturing a contact plug according to an embodiment of the present invention at different manufacturing stages. First, in FIG. 1, a device layer 110 is formed on a substrate 100. The substrate 100 may be a silicon substrate, or the substrate 100 may include another element semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; silicon germanium, gallium arsenide phosphide, indium aluminum phosphide, gallium aluminum arsenide, indium arsenide, indium gallium phosphide, and gallium indium arsenic phosphide; or a combination of the above.

Multiple processes are performed on the substrate 100 to provide different layers to form various integrated circuit element features in the component layer 110. For the sake of ease of explanation, the features of the integrated circuit elements are simplified in this disclosure. The component layer 110 includes a plurality of integrated circuit elements 112, which may include active elements, such as transistors, switch elements, etc., and/or passive elements, such as resistors, capacitors, inductors, converters, etc.

In some embodiments, the device layer 110 includes a first metal layer M1 connected to the integrated circuit device 112 and a dielectric layer 114 surrounding the integrated circuit device 112 and the first metal layer M1. FIG. 1 further includes forming a blocking layer 120 on the first metal layer M1. The material of the blocking layer 120 includes a material different from that of the dielectric layer 114 and can be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or any appropriate deposition technology. For example, the material of the dielectric layer 114 may be silicon dioxide, and the material of the blocking layer 120 may include silicon nitride, etc., so as to form an etching selectivity between the dielectric layer 114 and the blocking layer 120.

Next, as shown in FIG. 2 , an interlayer dielectric layer 130 is further formed on the blocking layer 120. The interlayer dielectric layer 130 may be undoped silicate glass or doped silicon oxide, or any suitable low-k dielectric material (e.g., a material with a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. In some embodiments, the thickness of the interlayer dielectric layer 130 is about 450-550 nm.

Next, as shown in FIG. 3 , another dielectric layer 140 is further formed on the interlayer dielectric layer 130, and the material of the dielectric layer 140 is different from the material of the interlayer dielectric layer 130. For example, the dielectric layer 140 may include tetraethylorthosilicate (TEOS) oxide, and therefore, in the following text, the dielectric layer 140 is also referred to as the TEOS layer 140. The TEOS layer 140 may be deposited by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or any appropriate deposition technique, and the thickness of the TEOS layer 140 is less than the thickness of the interlayer dielectric layer 130. In some embodiments, the thickness of TEOS layer 140 is about 90-110 nm.

Next, as shown in FIG. 4 , an underlayer 150 is formed on the TEOS layer 140. In some embodiments, the underlayer 150 may include a patternable carbon-containing material, such as an organic polymer, such as polyimide. In other embodiments, the underlayer 150 may include a suitable non-photosensitive patternable material. The underlayer 150 preferably includes a material different from that of the TEOS layer 140 and the interlayer dielectric layer 130, so that the underlayer 150 and the TEOS layer 140 and the interlayer dielectric layer 130 can be etched separately in different etching processes. In some embodiments, the bottom layer 150 can be formed by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. In some embodiments, the bottom layer 150 has a thickness of about 170-210 nm.

Next, as shown in FIG. 5 , a bottom antireflective coating (BARC) 160 is formed on the bottom layer 150. Then, as shown in FIG. 6 , a photoresist layer 170 is formed on the bottom antireflective coating 160. The bottom antireflective coating 160 disposed between the bottom layer 150 and the photoresist layer 170 may include selecting an appropriate organic material for the patterned photoresist layer 170. More specifically, the bottom antireflective coating 160 may provide suitable antireflective properties according to the wavelength of radiation that exposes the photoresist layer 170. In some embodiments, the bottom antireflective coating 160 may be formed by spin coating, and the thickness of the bottom antireflective coating 160 is about 32-40 nm.

The photoresist layer 170 may include a photosensitive material. In some embodiments, the photoresist layer 170 may include a suitable photoresist material different from the bottom layer 150. For example, the photoresist layer 170 may include an epoxy resin while the bottom layer 150 is a carbon-containing layer. In some embodiments, the thickness of the photoresist layer 170 is about 340-420 nm.

Next, as shown in FIG. 7 , the photoresist layer 170 is exposed and developed to pattern the photoresist layer 170 . More specifically, the step of patterning the photoresist layer 170 includes forming a first opening O1 in the photoresist layer 170 and exposing the bottom anti-reflective coating 160 under the photoresist layer 170 .

Next, as shown in FIG. 8 , the patterned photoresist layer 170 (see FIG. 7 ) is used as a mask to continue etching to deepen the first opening O1 until the blocking layer 120 is exposed. In some embodiments, etching to deepen the first opening O1 is to adopt directional dry etching, such as ion bombardment in the vertical direction. During the etching to deepen the first opening O1, a portion of the bottom anti-reflective coating 160 (see FIG. 7 ), a portion of the bottom layer 150 (see FIG. 7 ), a portion of the TEOS layer 140 (see FIG. 7 ), and a portion of the interlayer dielectric layer 130 (see FIG. 7 ) are removed. Furthermore, a cleaning process may be further performed such that the remaining bottom layer 150 and the bottom anti-reflective coating 160 are removed together with the patterned photoresist layer 170.

Next, as shown in FIG. 9 , the bottom layer 150 ′ is once again backfilled into the first opening O1, and the bottom layer 150 ′ covers the upper surface of the TEOS layer 140. The bottom layer 150 ′ may include a carbonaceous material or a suitable non-photosensitive patternable material. In some embodiments, the bottom layer 150 ′ may be formed by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. In some embodiments, the thickness of the bottom layer 150 ′ on the upper surface of the TEOS layer 140 is about 170-210 nm.

Next, as shown in FIG. 10 and FIG. 11 , a bottom anti-reflection coating 160′ is formed on the bottom layer 150′ again, and a photoresist layer 170′ is formed on the bottom anti-reflection coating 160′ again. The material of the bottom anti-reflection coating 160′ can be the same as or different from that of the bottom anti-reflection coating 160, and the material of the photoresist layer 170′ can be the same as or different from that of the photoresist layer 170.

Next, as shown in FIG. 12 , the photoresist layer 170’ is exposed and developed to pattern the photoresist layer 170’. More specifically, the step of patterning the photoresist layer 170’ includes forming a second opening O2 in the photoresist layer 170’ and exposing the bottom anti-reflective coating 160’ under the photoresist layer 170’. It should be noted that the width of the second opening O2 is greater than the width of the first opening O1, and the projection of the second opening O2 on the substrate 100 covers the projection of the first opening O1 on the substrate 100. After the photoresist layer 170’ is patterned to expose the bottom anti-reflective coating 160’ under the photoresist layer 170’, a plurality of non-identical etching processes are subsequently performed to form the desired contact openings.

First, as shown in FIG. 13 , a first etching process is performed to remove the portion of the bottom anti-reflective coating 160 ′ exposed to the second opening O2 and expose the bottom layer 150 ′ thereunder. The first etching process may be plasma etching, and the gas used may include oxygen and fluorine. For example, the etching gas used in the first etching process may include O ₂ , CHF ₃ , and CF ₄ , wherein the flow rate of O ₂ is approximately 6 to 10 sccm, the flow rate of CHF ₃ is approximately 60 to 80 sccm, and the flow rate of CF ₄ is approximately 110 to 150 sccm. The process pressure of the first etching process is approximately 90 to 110 mT. In the first etching process, the photoresist layer 170 still covers the bottom anti-reflective coating 160 ′, and only a portion of the photoresist layer 170 ′ is subsequently removed in the first etching process.

Next, as shown in FIG. 14 , a second etching process is performed to remove the portion of the bottom layer 150′ exposed to the second opening O2 and expose the TEOS layer 140 thereunder. The second etching process may be plasma etching, and the process pressure of the second etching process may be less than the process pressure of the first etching process, so that while removing the portion of the bottom layer 150′ located above the TEOS layer 140, the bottom layer 150′ is still retained to fill the first opening O1, and the top surface of the bottom layer 150′ in the first opening O1 is substantially flush with the top surface of the TEOS layer 140.

In some embodiments, the gas used in the second etching process may include CO ₂ , wherein the flow rate of CO ₂ is about 360-440 sccm, and the process pressure of the second etching process is about 13-17 mT. In the second etching process, the photoresist layer 170 ′ still covers the bottom anti-reflective coating 160 ′, and the amount of the photoresist layer 170 ′ removed in the second etching process is slightly greater than the amount of the photoresist layer 170 ′ removed in the first etching process.

Next, as shown in FIG. 15 , a third etching process is performed to recess the portion of the bottom layer 150′ that is filled in the first opening O1. The second etching process may be plasma etching, and the etching gas used in the second etching process may have a significant etching selectivity between the bottom layer 150′ and other layers, such as the TEOS layer 140, the bottom anti-reflective coating 160′, and the photoresist layer 170′, so that the etching rate of the bottom layer 150′ is much greater than the etching rate of the other layers. The recess amount of the bottom layer 150′ may be controlled so that the top surface of the portion of the bottom layer 150′ that is recessed and filled in the first opening O1 is between the interlayer dielectric layer 130 and the TEOS layer 140. That is, the top surface of the bottom layer 150′ is higher than the top surface of the interlayer dielectric layer 130 but lower than the top surface of the TEOS layer 140.

In some embodiments, the gas used in the third etching process may include H ₂ and N ₂ , wherein the flow rate of H ₂ is about 270-330 sccm, the flow rate of N ₂ is about 270-330 sccm, and the process pressure of the third etching process is about 13-17 mT. During the third etching process, the photoresist layer 170 'covers the bottom anti-reflective coating 160 ', and after the third etching process is completed, a portion of the photoresist layer 170 'still covers the bottom anti-reflective coating 160 '.

Next, as shown in FIG. 16 , a fourth etching process is performed to remove the portion of the TEOS layer 140 exposed to the second opening O2. The fourth etching process may be plasma etching, and the etching gas used in the fourth etching process may have a relatively indistinct etching selection between the layers, so that while removing the portion of the TEOS layer 140 exposed to the second opening O2, the photoresist layer 170 '(see FIG. 15 ) and the bottom layer 150 'are also consumed together.

In some embodiments, the gas used in the fourth etching process may include Ar, CHF ₃ and CF ₄ , wherein the flow rate of Ar is about 270-330 sccm, the flow rate of CHF ₃ is about 45-55 sccm, and the flow rate of CF ₄ is about 45-55 sccm. The process pressure of the fourth etching process is about 27-33 mT. After the fourth etching process is completed, the photoresist layer 170' may be completely consumed to expose the bottom anti-reflective coating 160', and the top surface of the bottom layer 150' filled in the first opening O1 may be flush with or lower than the top surface of the interlayer dielectric layer 130.

Next, referring to FIG. 17 , a fifth etching process is performed to once again recess the bottom layer 150′ and form a sufficient step T1 between the bottom layer 150′ filled in the first opening O1 and the interlayer dielectric layer 130. The height of the step T1 (i.e., the distance between the top surface of the bottom layer 150′ filled in the first opening O1 and the top surface of the interlayer dielectric layer 130) is approximately 35-45% of the thickness T2 of the bottom layer 150′ (here, the bottom layer 150′ between the bottom anti-reflective coating 160′ and the TEOS layer 140) to improve the surface profile of the contact opening. More specifically, if the height of the step difference T1 is less than 35% of the thickness T2 of the bottom layer 150', the interlayer dielectric layer 130 subsequently etched will have a fence-like protrusion defect; if the height of the step difference T1 is greater than 45% of the thickness T2 of the bottom layer 150', the interlayer dielectric layer 130 subsequently etched will have a bowl-shaped depression defect.

In some embodiments, the fifth etching process lasts for a very short time, and thus can be referred to as a flash etching process. The gas used in the fifth etching process can include CO ₂ , wherein the flow rate of CO ₂ is about 360-440 sccm, and the process pressure of the fifth etching process is about 13-17 mT.

Next, as shown in FIG. 18 , a sixth etching process is performed to deepen the second opening O2. The sixth etching process includes etching the interlayer dielectric layer 130 and the bottom layer 150’ filled in the first opening O1 using the bottom anti-reflective coating 160’ (see FIG. 17 ) and the bottom layer 150’ and TEOS layer 140 covered therewith as masks. The bottom anti-reflective coating 160’ is also consumed in this sixth etching process, so that the bottom layer 150’ thereunder is exposed.

Since the TEOS layer 140 and the interlayer dielectric layer 130 are etched using different processes respectively, and a flash etching process is inserted between the step of etching the TEOS layer 140 and the step of etching the interlayer dielectric layer 130 to pre-make a step difference T1 between the bottom layer 150' filled in the first opening O1 and the interlayer dielectric layer 130 as a buffer, the etched interlayer dielectric layer 130 has a relatively flat top surface, and this top surface does not have obvious fence-like protrusions or bowl-shaped depressions. The top surface of the bottom layer 150' filled in the first opening O1 may be substantially continuous with the top surface of the etched interlayer dielectric layer 130.

In some embodiments, the sixth etching process may be a high pressure and low power plasma etching, the process pressure of the sixth etching process is about 90-110 mT, and the power of the sixth etching process is about 360-440 W. In some embodiments, the gas used in the sixth etching process may include Ar, N ₂ , and CF ₄ , wherein the flow rate of Ar is about 225-275 sccm, the flow rate of N ₂ is about 225-275 sccm, and the flow rate of CF ₄ is about 270-330 sccm.

Next, as shown in FIG. 19 , the seventh etching process is performed, which is also called an ash process, to completely remove the remaining bottom layer 150 ′ (see FIG. 18 ) and expose the blocking layer 120. The seventh etching process includes removing the bottom layer 150 ′ in the first opening O1 and the bottom layer 150 ′ above the TEOS layer 140. In some embodiments, the gas used in the seventh etching process may include CO ₂ , wherein the flow rate of CO ₂ is about 630-770 sccm, and the process pressure of the seventh etching process is about 63-77 mT.

Then, as shown in FIG. 20 , an eighth etching process is performed, including etching with the interlayer dielectric layer 130 and the TEOS layer 140 as masks to remove the portion of the blocking layer 120 exposed to the first opening O1, and to expose the first metal layer M1 below the first opening O1. In some embodiments, the gas used in the eighth etching process may include N ₂ and CF ₄ , wherein the flow rate of N ₂ is about 180-220 sccm, the flow rate of CF ₄ is about 270-330 sccm, and the process pressure of the eighth etching process is about 90-110 mT.

At this point, a contact opening 180 can be formed in the interlayer dielectric layer 130, and the first metal layer M1 is exposed to the contact opening 180, wherein the contact opening 180 includes a first opening O1 and a second opening O2 on the first opening O1, and the first opening O1 and the second opening O2 are interconnected. Moreover, the width of the second opening O2 is greater than the width of the first opening O1, and the projection of the second opening O2 on the substrate 100 covers the projection of the first opening O1 on the substrate 100.

As mentioned above, different etching processes are used when etching the TEOS layer 140 and the interlayer dielectric layer 130, and a flash etching process is inserted between the step of etching the TEOS layer 140 and the step of etching the interlayer dielectric layer 130 to pre-make a step difference T1 between the bottom layer 150' filled in the first opening O1 and the interlayer dielectric layer 130 as a buffer. Therefore, the etched interlayer dielectric layer 130 has a flatter top surface, and the contour of the contact opening 180 is also flatter.

Next, referring to FIG. 21 , a barrier layer 190 is deposited in the contact opening 180. The barrier layer 190 can be conformally formed on the sidewalls of the contact opening 180 and the first metal layer M1 by chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or any appropriate deposition technology. The function of the barrier layer 190 is to prevent the subsequent filled metal material from diffusing into the interlayer dielectric layer 130. In some embodiments, the material of the barrier layer 190 includes Ta, and the thickness of the barrier layer 190 is about 9-11 nm.

Next, as shown in FIG. 22 , a seed layer 200 is continuously deposited on the barrier layer 190 in the contact opening 180. The seed layer 200 can be conformally formed on the barrier layer 190 by chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition or any appropriate deposition technology. The function of the seed layer 200 is to make it easier for the metal material filled subsequently to grow. In some embodiments, the material of the seed layer 200 includes Cu, and the thickness of the seed layer 200 is about 80-100 nm.

Next, as shown in FIG. 23 , a filling metal 210 is continuously deposited in the contact opening 180 until the entire contact opening 180 is filled. The filling metal 210 can be filled in the entire contact opening 180 by chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or any appropriate deposition technology. In some embodiments, the material of the filling metal 210 includes Cu, and the thickness of the filling metal 210 is about 820-1000 nm. After the filling metal 210 fills the entire contact opening 180, a certain portion of the filling metal 210 covers the TEOS layer 140.

Next, as shown in FIG. 24 , a planarization process such as chemical mechanical polishing (CMP) is performed to remove the TEOS layer 140 (see FIG. 23 ) and the filling metal 210 thereon, and to make the filling metal 210 coplanar with the top surface of the interlayer dielectric layer 130. At this point, a contact plug 220 is provided to be disposed in the interlayer dielectric layer 130 and connected to the first metal layer M1 below. The contact plug 220 includes multiple layers of metal materials, such as a barrier layer 190, a seed layer 200, and a filling metal 210. The contact plug 220 has an upper portion 222 and a lower portion 224, wherein the width of the upper portion 222 is greater than the width of the lower portion 224.

Then, as shown in FIG. 25, another blocking layer 230 may be deposited on the structure shown in FIG. 24, and the aforementioned manufacturing method may be repeated on the blocking layer 230 to manufacture other metal layers and contact plugs as interconnection structures for connection with external circuits.

Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100: Substrate 110: Component layer 112: IC components 114: Dielectric layer 120,230: Barrier layer 130: Interlayer dielectric layer 140: Dielectric layer/TEOS layer 150,150’: Bottom layer 160,160’: Bottom anti-reflective coating 170,170’: Photoresist layer 180: Contact opening 190: Barrier layer 200: Seed layer 210: Filling metal 220: Contact plug 222: Upper part 224: Lower part M1: First metal layer O1: First opening O2: Second opening T1: Step difference T2: Thickness

In order to make the purpose, features, advantages and embodiments of the present invention more clearly understandable, the attached drawings are described in detail as follows: Figures 1 to 25 are schematic diagrams of the method of making a contact plug in one embodiment of the present invention at different manufacturing stages.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Substrate

110: Component layer

112: Integrated circuit components

114: Dielectric layer

120: barrier layer

130: Interlayer dielectric layer

140: Dielectric layer/TEOS layer

150’: bottom layer

160’: Bottom anti-reflective coating

M1: First metal layer

O1: First opening

O2: Second opening

T1: Step difference

T2: Thickness

Claims (10)

A method for making a contact plug, comprising: forming a blocking layer on a metal layer; forming an interlayer dielectric layer on the blocking layer; forming a first dielectric layer on the interlayer dielectric layer; forming a first opening in the first dielectric layer and the interlayer dielectric layer; forming a bottom layer to fill the first opening and cover the first dielectric layer; Performing a plurality of etching processes to remove the bottom layer and form a contact opening in the first dielectric layer and the interlayer dielectric layer, wherein the etching processes include a flash etching process, which is used to make the bottom layer have a step difference in the first opening before removing the bottom layer; and forming a contact plug to fill the contact opening. A method for manufacturing a contact plug as described in claim 1, wherein the first dielectric layer, the interlayer dielectric layer and the bottom layer respectively include different materials. A method for manufacturing a contact plug as described in claim 1, wherein the step difference is 35-45% of the thickness of the bottom layer covering the first dielectric layer. The method for manufacturing a contact plug as described in claim 1 further includes forming a bottom anti-reflective coating on the bottom layer, and the etching processes include a first etching process to partially remove the bottom anti-reflective coating to expose the bottom layer. A method for manufacturing a contact plug as described in claim 4, wherein the etching processes include a second etching process to partially remove the bottom layer to expose the first dielectric layer, wherein a portion of the bottom layer still fills the first opening and is surrounded by the first dielectric layer. A method for manufacturing a contact plug as described in claim 5, wherein the etching processes include a third etching process to partially remove the bottom layer so that a top surface of the bottom layer is between a top surface of the first dielectric layer and a top surface of the interlayer dielectric layer. A method for manufacturing a contact plug as described in claim 6, wherein the etching processes include a fourth etching process to partially remove the first dielectric layer to expose the interlayer dielectric layer, and wherein the flash etching process is performed in succession to the fourth etching process. A method for manufacturing a contact plug as described in claim 7, wherein the etching processes include a sixth etching process to partially remove the interlayer dielectric layer and the bottom layer after the flash etching process to form a second opening in the interlayer dielectric layer. A method for manufacturing a contact plug as described in claim 8, wherein the etching processes include a seventh etching process to remove the bottom layer so that the first opening is connected to the second opening to serve as the contact opening. The method for manufacturing a contact plug as described in claim 1, wherein the process pressure of the flash etching process is 13-17 mT, the etching gas of the flash etching process includes CO ₂ , and the flow rate of CO ₂ is 360-440 sccm.

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