201121053 六、發明說明： 【發明所屬之技術領域】 本發明係關於一薄膜電晶體結構及其製作方法，特別是 關於一種具厚源汲極之薄膜電晶體結構及其製作方法。 【先前技術】 近年來，多晶矽薄膜電晶體由於比非晶矽薄膜電晶體有 較高的載子移動率，因此應用在主動式液晶顯示器和電路 整合在玻璃基板上面，可提供良好之效能，而已被應用在 液晶顯示器、手機面板、薄膜太陽能電池、三維積體電路 ’當成畫素的開關元件。然而’由於汲極端的高電場會導 致強大的漏電流與扭結效應（kink effect)使元件產生不穩 定性，因此阻礙了多晶矽薄膜電晶體在高效能電路上的應 用。漏電流主要的機制是及極端空乏區的強大電場誘使載 子經由晶粒邊界的缺陷而形成漏電流。因此，為了減少強 大的漏電流，如何降低汲極端的高電場乃係亟欲克服之技 術瓶頸。 在目前的研究中’已經有學者提出改善的方法，如偏移 (offset)、輕摻雜汲極（Lightly doped drain ; LDD)(例如美國 專利118 6,468,83 9揭露1^00薄膜電晶體結構）、閘極覆蓋輕 摻雜 ^^(Gate overlapped lightly doped drain ; G0LDD)等 結構，都是用來減輕汲極端的高電場，不過由於其中有的 方法需要額外的離子佈植（ion-implantation)條件，而且捧雜 的能量藥劑都不好控制，並且產生額外寄生電阻降低開電 流（on-state current)，而有其侷限。另外一些方法則需要額 201121053 外的光罩，因此會增加整體的花費。 近年來，也有相關研究提出厚源汲極（Raised Source/Drain; RSD)之薄膜電晶體結構來降低没極端高電場 ，例如：201121053 VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor structure and a method of fabricating the same, and more particularly to a thin film transistor structure having a thick source drain and a method of fabricating the same. [Prior Art] In recent years, polycrystalline germanium thin film transistors have higher carrier mobility than amorphous germanium thin film transistors, so they are applied to an active liquid crystal display and a circuit integrated on a glass substrate to provide good performance. It is used as a switching element for liquid crystal displays, mobile phone panels, thin film solar cells, and three-dimensional integrated circuits. However, due to the extremely high electric field of the 汲, the strong leakage current and the kink effect make the components unstable, thus hindering the application of the polycrystalline silicon transistor to the high-performance circuit. The main mechanism of leakage current is that the strong electric field in the extremely depleted region induces the carrier to form a leakage current through defects in the grain boundary. Therefore, in order to reduce the strong leakage current, how to reduce the high electric field of the 汲 extreme is a technical bottleneck to be overcome. In the current research, 'suggested methods have been proposed, such as offset, Lightly doped drain (LDD) (for example, U.S. Patent 1,186,468,83 9 discloses a 1^00 thin film transistor structure). ), Gate overlapped lightly doped drain (G0LDD) and other structures are used to reduce the high electric field of the 汲 extreme, but some methods require additional ion-implantation. Conditions, and the possession of energy agents are not well controlled, and additional parasitic resistance is generated to reduce the on-state current, which has its limitations. Other methods require a mask outside of 201121053, which increases overall cost. In recent years, related research has also proposed a thin film transistor structure of Raised Source/Drain (RSD) to reduce the extremely high electric field, such as:
Kow Ming Chang等人於2007年提出論文"A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process" (IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 9, SEPTEMBER 2007)中揭露一種厚源汲極架構10， 如圖1A所示。厚源汲極架構10包含載板11、源極12、汲極 13、通道區14、閘極介電層15及閘極層16。該載板11可為 氧化層，通道區14則由多晶矽組成。形成該厚源汲極架構 10 需進行化學機械研磨（chemical mechanical polishing; CMP)及離子佈值等製程。 II_Suk Kang 等人於 2008 年提出論文"Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain" (IEEE ELECTRON DEVICE LETTERS，VOL. 29, NO. 3, MARCH 2008)中揭露一種 厚源汲極架構20，厚源汲極架構20包含載板21、源極22、 汲極23、氣化石夕層24、閘極介電層25、通道區26及閘極層 27。該載板21係玻璃，通道區26則由多晶矽組成。本論文 之閘極層27係直接設置於載板21上，而與一般傳統結構略 有不同。形成該厚源汲極架構20需進行背向曝光（back surface exposure)及離子佈值（ion-implanting)製程，整體製 201121053 程較為複雜。 縱然目前學界或業界已提出厚源汲極架構以解決漏電流 的問題，然而該等技術製作厚源汲極結構時需要化學機械 研磨技術或者額外的離子佈植，因此製程較複雜且有增加 整體花費的疑慮。 【發明内容】 本發明提出一種結合厚源汲極與間隔物結構的薄膜電晶 Φ 體，因為間隔物與厚源汲極將發生熱點（Hot spot)遠離通道 區，並且使電場的強度更加擴散開，可以更有效降低汲極 端高電場，改善元件的不理想效應，如扭結效應、熱載子 效應’進-步減少漏電流。另外，本發明不需使用化學機 械研磨以及離子佈植技術，具簡化製程之功效。 根據本發明之一實施例之具厚源汲極之薄膜電晶體結構 ，其包含載板、半導體層、二間隔物、閘極介電層及閘極 層。半導體層形成於該載板上，包含通道區、源極區域及 鲁 》及極區域，其中通道區介於源極區域及没極區域之間，且 通道區鄰接源極區域及汲極區域處形成二内侧壁，亦即半 導體層於通道區上方形成一凹陷。二間隔物分別鄰接該二 内側壁且形成於該通道區上方。閘極介電層形成於通道區 及一間隔物上方。閘極層形成於該閘極介電層上方。 根據本發明之一實施例之一種薄膜電晶體結構之製作方 法，包含以下步驟：提供一載板；形成半導體層於該載板 ^方；蝕刻該半導體層形成一凹陷，凹陷兩側之半導體層 分別為源極區域及没極區域，且凹陷鄰接該源極區域及沒 [S] -6 · 201121053 極區域處形成二内侧壁；沉積一絕緣層於該半導體層上方 ;蚀刻該絕緣層以形成二間隔物，該二間隔物鄰接該二内 侧壁；依序沉積閘極介電層及閘極層於該半導體層及二間 隔物上方；以及蝕刻去除位於該半導體層之源極區域及汲 極區域上方之閘極介電層及閘極層。 【實施方式】 以下詳細討論本發明於目前較佳實施例的製作和使用。 不過應當理解，本發明提供許多可應用的發明概念，其可 在各種各樣的具體情況下實施。該討論的具體實施例僅說 明了製作和使用該發明的具體方式，並沒有限制本發明的 Λ-Λ* CS3 範圍。 為降低汲極端的高電場，本發明提出一個具有厚源汲極 (RSD)薄膜電晶體，而且不需使用額外的離子佈植或化學機 械研磨步驟。與傳統型結構比較之下，本發明之RSD薄膜 電晶體降低了汲極端的高電場，並且改善了扭結效應，及 降低漏電流。本發明的製程步驟較一般的RSD結構來的簡 單。另外，本發明使用ISE_TCAD模擬軟體來驗證結構的元 件特性。 圖2A至圖2G繪示本發明一實施例之薄膜電晶體結構之 製作方法。參照圖2A，提供一基板31，其可為矽基板，並 在基板31上面形成一載板32。載板32可為氧化矽層，例如 緩衝氧化層（buffer oxide)，以模擬薄膜電晶體用之玻璃基 板。一實施例中，利用水平爐管於1050t形成厚度約4〇= 至5000埃之緩衝氧化層作為後續製作薄膜電晶體之載板& m 201121053 參照圖2B，接著在載板32上形成半導體㈣，例如非曰 石夕層（am〇rphous silic〇n)。一實施例中，作為半導體層^ 非晶石夕層係利用水平爐管中形成，其厚度介於25〇〇至侧 埃之間。 參照圖2C ’利帛源極（s〇urce)/沒極（drain)光罩定義相應區 域’且於半導體層33中蝕刻出凹陷34。一實施例中，凹陷 ® 34可利用（多晶秒）银刻或雷射形成，而凹陷34的深度約介於 1500至2500埃之間。若該半導體層33為非晶石夕層，凹陷％ 形成後，利用爐管將非晶矽層進行回火，而形成多晶矽層 。凹陷34兩側之半導體層33即形成源極區域44和汲極區域 45，而凹陷34下方之位於源極區域44和汲極區域45間之區 域即形成通道區43。凹陷34中通道區43鄰接源極區域44及 汲極區域45處形成二内側壁37。 參照圖2D ’沉積絕緣層35於半導體層33上。該沉積順應 • 凹陷34之形狀或輪廓，使得絕緣層35中形成一開口刊。一 實施例中，絕緣層3 _5係利用化學氣相沉積形成之四乙氧基 矽烷（丁61^6比〇\丫311&1^;丁£〇3)，厚度約 1500至2500埃。 參照圖2E’等向性姓刻（anis〇tropic etching)絕緣層35而形 成間隔物38於半導體層33之内侧壁37的兩側，即二間隔物 38分別鄰接該二内侧壁37。至於位於源極區域44及汲極區 域45上之絕緣層35則完全去除。 參照圖2F，於該半導體層33及二間隔物38上方依序沉積 閘極介電層39及閘極層40。一實施例中，閘極介電層39係 201121053 氧化層，且其厚度約400至600埃。閘極層4〇可為多晶矽層 ，其厚度約800至1200埃。閘極介電層39及閘極層4〇可利用 水平爐管依序進行沉積。閘極層4〇可為經過摻雜形成N+型 多晶碎層。 參照圖2G ’利用微影及蝕刻技術去除源極區域44和汲極 區域45上方（即凹陷外）之閘極介電層39及閘極層4〇，定義出 電晶體之閘極。然後，離子佈植位於源極區域44及汲極區 域45之半導體層33(例如形成摻雜多晶矽層）定義出源極與 沒極。 至此’即形成本發明一實施例之薄膜電晶體結構3〇，就 結構關係而言，薄膜電晶體結構3〇包含基板31、載板32、 半導體層33、二間隔物38、閘極介電層39及閘極層40。半 導體層33形成於載板32上，且包含通道區43、源極區域44 及汲極區域45，其中通道區43介於該源極區域44及汲極區 域45之間。通道區43鄰接源極區域44及汲極區域45處形成 一内侧壁37。二間隔物38分別鄰接二内側壁37且形成於通 道區43上方。閘極介電層39形成於通道區43及二間隔物38 上方。閘極層40形成於該閘極介電層39上方。 位於二間隔物38上方之閘極介電層39及閘極層40順應二 間隔物38之形狀而延伸凸起。間隔物38包含第一連接面“ 、第二連接面52及第三連接面53,其中第一連接面51鄰接 源極區域44或汲極區域45之一端部；第二連接面52鄰接該 通道區43之至少一部分；第三連接面53鄰接閘極介電層 之至少一部分。 [S1 -9- 201121053 較佳地，間隔物38可選自高介電常數（highk)之材料，其 介電常數係、大於等於3·9。除前述實施例使用之氧化梦外， 亦可使用氮化矽或氧化铪。閘極層41之材料選自多晶矽、 碳化矽或石夕化鍺。 本發明在通道中，其電場強度比傳統型結構來的低，主 要因為内側壁與厚源汲極將發生熱點（Hot spot)遠離通道 區’並且使電場的強度更加擴散開，可以更有效降低没極 端南電場。 圖3為本發明一實施例之RSD薄膜電晶體之電場曲線圖 ，可以明顯的得知本發明之RSD薄膜電晶體相較於習知者 ，其汲極端高電場從2.67><105乂^111降低至2.14><105乂化111。 圖4為本發明一實施例之RSD薄膜電晶體與傳統型多晶 矽溥膜電晶體的汲極_源極輸出電流L與汲極_源極電壓乂^ 之關係曲線圖，在閘極-源極電壓Vgs從〇〜1〇 乂且¥心為〇〜2〇 V的量測條件下，可以明顯的發現本發明之RSD薄膜電晶體 結構相對於傳統型的多晶矽薄膜電晶體其扭結電流的改善 很多，主要是因為除了 RSD結構有降電場的因素，並且内 侧壁也能將電場的強度分散開來，因此證明此Rs〇薄膜電 晶體的確可以更有效的降低汲極端的高電場，進而改善扭 結效應。 圖5為為本發明一實施例之rSd薄膜電晶體與傳統型多 晶矽薄膜電晶體的的汲極-源極輸出電流Ids與閘極_源極電 壓Vgs關係曲線圖，從圖5中可以明顯看出在Vds為5V與V 為-15V的情況下，本發明之RSD薄膜電晶體的漏電流明顯 201121053 的比傳統型的來的小，可從651 pA降低到133 pA，其原因 主要是因為内側壁與RSD結構的結合，大幅降低了汲極端 的高電場’因此減少了由閘極引發的汲極漏電流，證明本 發明之RSD薄膜電晶體可以有效降低汲極端的高電場，以 減少其漏電流’也證明先前模擬數據的可靠性。另外值得 注意的是，在Vds為0.1 V時，RSD薄膜電晶體的漏電流比傳 統型的稍微大一些，可能是在形成内侧壁時，由於使用乾 蝕刻機來蝕刻出侧壁，因此通道表面的缺陷狀態（interface trap state density)比傳統型來略多，才導致其漏電流比傳統 型略大一些。 圖6為本發明一實施例之RSD薄膜電晶體與傳統型在不 同通道長度之崩潰電壓曲線，一樣是在氨電漿能量2〇〇w、 時間30分鐘處理後，從圖6中可以發現在不同通道長度下本 發明之R S D薄膜電晶體的崩潰電壓明顯的比傳統型高出許 多，尤其在6 μπι的情況下將近為傳統型的兩倍，此結果再 次證明本發明之RSD薄膜電晶體降電場的能力，因此，在 短通道操作下，本發明之RSD薄膜電晶體也能有良好的操 作特性。 本發明提出一種結合厚源汲極與内側壁之間隔物結構的 薄膜電晶體，不需使用化學機械研磨以及離子佈植技術， 從電場強度曲線與輸出特性圖，可以看出在通道的電場有 明顯的降低許多，主要因為内侧壁上之間隔物與厚源没極 將發生熱點（Hot spot)遠離通道區，並且使電場的強度更加 擴散開’可以更有效降減極端高電場，改善元件的扭結 201121053 效應、熱載子效應等，進一步減少漏電流。 進一步言之，由於厚源没極降低其串聯電阻，可降低元 件汲極端的高電場；而内側壁之間隔物相當於FID結構，可 以有效降低通道内的空間電何區（space charge region)中的 峰值電場，因此結合這兩種結構，可以更加有效的降低j：及 極端的高電場，並且不需要使用離子佈植以及化學機械研 磨等的高昂貴製程。 • 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範園 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1A及1B顯示習知之具厚源汲極之薄膜電晶體結構； 圖2A至2G顯示根據本發明一實施例之薄膜電晶體結構 • 之製作方法； 圖3顯示根據本發明一實施例之RSD薄膜電晶體之電場 曲線圖； 圖4及圖5顯示根據本發明一實施例之rSD薄膜電晶體之 電流及電壓之關係曲線圖；以及 圖ό顯示根據本發明一實施例之rSD薄膜電晶體與傳統 型之通道長度與崩潰電壓之關係曲線圖。 【主要元件符號說明】 10厚源汲極架構 丨丨載板 I S1 -12- 201121053Kow Ming Chang et al. presented a paper in 2007 "A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process" (IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO 9. SEPTEMBER 2007) discloses a thick source drain structure 10, as shown in Figure 1A. The thick source drain structure 10 includes a carrier 11, a source 12, a drain 13, a via region 14, a gate dielectric layer 15, and a gate layer 16. The carrier 11 can be an oxide layer and the channel region 14 can be composed of polysilicon. The formation of the thick source drain structure 10 requires chemical mechanical polishing (CMP) and ion cloth values. II_Suk Kang et al. filed a paper in 2008 "Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain" (IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 3, MARCH 2008 A thick-source drain structure 20 is disclosed. The thick-source drain structure 20 includes a carrier 21, a source 22, a drain 23, a gasification layer 24, a gate dielectric layer 25, a channel region 26, and a gate layer. 27. The carrier 21 is glass and the channel region 26 is composed of polycrystalline germanium. The gate layer 27 of this paper is directly disposed on the carrier 21, which is slightly different from the conventional structure. The formation of the thick source drain structure 20 requires a back surface exposure and an ion-implanting process, and the overall process is more complicated. Even though academics or the industry have proposed thick-source bungee architectures to solve the problem of leakage current, these technologies require chemical mechanical polishing or additional ion implantation when making thick-source bungee structures, so the process is complicated and increases overall. The doubts spent. SUMMARY OF THE INVENTION The present invention provides a thin film electro-crystalline Φ body combining a thick source drain and a spacer structure, because a spacer and a thick source drain will have a hot spot away from the channel region, and the intensity of the electric field is further diffused. On, it can effectively reduce the extremely high electric field of the crucible and improve the undesired effects of the components, such as the kink effect and the hot carrier effect, to reduce the leakage current. In addition, the present invention does not require the use of chemical mechanical grinding and ion implantation techniques to simplify the process. A thin film transistor structure having a thick source drain according to an embodiment of the present invention includes a carrier, a semiconductor layer, a spacer, a gate dielectric layer, and a gate layer. a semiconductor layer is formed on the carrier, and includes a channel region, a source region, and a gate region, wherein the channel region is between the source region and the gate region, and the channel region is adjacent to the source region and the drain region. Two inner sidewalls are formed, that is, the semiconductor layer forms a recess above the channel region. Two spacers respectively adjoin the two inner sidewalls and are formed above the channel region. A gate dielectric layer is formed over the channel region and a spacer. A gate layer is formed over the gate dielectric layer. A method for fabricating a thin film transistor structure according to an embodiment of the present invention comprises the steps of: providing a carrier; forming a semiconductor layer on the carrier; etching the semiconductor layer to form a recess, and a semiconductor layer on both sides of the recess The source region and the gate region are respectively, and the recess is adjacent to the source region and the second inner sidewall is formed at the [S] -6 · 201121053 pole region; an insulating layer is deposited over the semiconductor layer; and the insulating layer is etched to form a spacer, the two spacers are adjacent to the two inner sidewalls; a gate dielectric layer and a gate layer are sequentially deposited over the semiconductor layer and the two spacers; and etching is performed to remove the source region and the drain region of the semiconductor layer The gate dielectric layer and gate layer above the region. [Embodiment] The making and using of the present invention in the presently preferred embodiments are discussed in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts which can be embodied in various specific embodiments. The specific embodiments of the discussion are merely illustrative of specific ways of making and using the invention, and do not limit the Λ-Λ* CS3 range of the present invention. In order to reduce the high electric field of the crucible extreme, the present invention proposes a thick-source drain (RSD) thin film transistor without the need for additional ion implantation or chemical mechanical polishing steps. Compared with the conventional structure, the RSD thin film transistor of the present invention lowers the high electric field of the 汲 extreme, and improves the kink effect and reduces the leakage current. The process steps of the present invention are simpler than the general RSD structure. In addition, the present invention uses the ISE_TCAD simulation software to verify the component characteristics of the structure. 2A to 2G illustrate a method of fabricating a thin film transistor structure according to an embodiment of the present invention. Referring to Fig. 2A, a substrate 31 is provided which may be a germanium substrate, and a carrier 32 is formed on the substrate 31. The carrier 32 can be a ruthenium oxide layer, such as a buffer oxide, to simulate a glass substrate for a thin film transistor. In one embodiment, a buffer oxide layer having a thickness of about 4 〇 = 5000 Å is formed by using a horizontal furnace tube at 1050 tt as a carrier for the subsequent fabrication of a thin film transistor & m 201121053. Referring to FIG. 2B, a semiconductor is formed on the carrier 32 (4). For example, it is not a 〇 hou hou hou hou (am〇rphous silic〇n). In one embodiment, the amorphous layer is formed as a semiconductor layer using a horizontal furnace tube having a thickness of between 25 Å and Å. Referring to Fig. 2C, the s〇urce/drain reticle defines the corresponding region' and the recess 34 is etched in the semiconductor layer 33. In one embodiment, the recesses ® 34 may be formed using (polycrystalline seconds) silver engraving or laser formation, while the depressions 34 have a depth of between about 1500 and 2500 angstroms. If the semiconductor layer 33 is an amorphous layer, after the % of the recess is formed, the amorphous germanium layer is tempered by a furnace tube to form a polycrystalline germanium layer. The semiconductor layer 33 on both sides of the recess 34 forms the source region 44 and the drain region 45, and the region below the recess 34 between the source region 44 and the drain region 45 forms the channel region 43. The channel region 43 in the recess 34 forms two inner sidewalls 37 adjacent the source region 44 and the drain region 45. The insulating layer 35 is deposited on the semiconductor layer 33 with reference to Fig. 2D. The deposition conforms to the shape or contour of the recess 34 such that an opening is formed in the insulating layer 35. In one embodiment, the insulating layer 3_5 is formed by chemical vapor deposition of tetraethoxy decane (Ding 61^6 〇 丫 & 311 &1;; 〇 〇 3), having a thickness of about 1500 to 2500 angstroms. Referring to Fig. 2E' anis tropic etching insulating layer 35, spacers 38 are formed on both sides of the inner side wall 37 of the semiconductor layer 33, i.e., two spacers 38 respectively adjoin the two inner side walls 37. The insulating layer 35 on the source region 44 and the drain region 45 is completely removed. Referring to FIG. 2F, a gate dielectric layer 39 and a gate layer 40 are sequentially deposited over the semiconductor layer 33 and the two spacers 38. In one embodiment, the gate dielectric layer 39 is an oxide layer of 201121053 and has a thickness of about 400 to 600 angstroms. The gate layer 4A may be a polysilicon layer having a thickness of about 800 to 1200 angstroms. The gate dielectric layer 39 and the gate layer 4〇 can be deposited sequentially using a horizontal furnace tube. The gate layer 4〇 may be doped to form an N+ type polycrystalline layer. Referring to Fig. 2G', the gate dielectric layer 39 and the gate layer 4'' are removed from the source region 44 and the drain region 45 (i.e., outside the recess) by lithography and etching techniques to define the gate of the transistor. Ion implantation of the semiconductor layer 33 located in the source region 44 and the drain region 45 (e.g., forming a doped polysilicon layer) defines the source and the immersion. Thus, the thin film transistor structure 3A of the embodiment of the present invention is formed. In terms of structural relationship, the thin film transistor structure 3 includes a substrate 31, a carrier 32, a semiconductor layer 33, two spacers 38, and a gate dielectric. Layer 39 and gate layer 40. The semiconductor layer 33 is formed on the carrier 32 and includes a channel region 43, a source region 44 and a drain region 45, wherein the channel region 43 is interposed between the source region 44 and the drain region 45. The channel region 43 forms an inner sidewall 37 adjacent the source region 44 and the drain region 45. Two spacers 38 are respectively adjacent to the two inner side walls 37 and formed above the channel area 43. A gate dielectric layer 39 is formed over the channel region 43 and the two spacers 38. A gate layer 40 is formed over the gate dielectric layer 39. The gate dielectric layer 39 and the gate layer 40 over the spacers 38 extend in a shape conforming to the shape of the spacers 38. The spacer 38 includes a first connecting surface, a second connecting surface 52 and a third connecting surface 53, wherein the first connecting surface 51 abuts one end of the source region 44 or the drain region 45; the second connecting surface 52 abuts the channel At least a portion of the region 43; the third connection surface 53 abuts at least a portion of the gate dielectric layer. [S1 -9- 201121053 Preferably, the spacer 38 may be selected from a high dielectric material, which is dielectrically The constant system is greater than or equal to 3·9. In addition to the oxidizing dream used in the foregoing embodiment, tantalum nitride or yttrium oxide may be used. The material of the gate layer 41 is selected from the group consisting of polycrystalline germanium, tantalum carbide or shihuahua. In the channel, the electric field strength is lower than that of the conventional structure, mainly because the inner sidewall and the thick source drain will have a hot spot away from the channel region and the intensity of the electric field will be more diffused, which can effectively reduce the extreme south. Fig. 3 is an electric field curve diagram of an RSD thin film transistor according to an embodiment of the present invention. It can be clearly seen that the RSD thin film transistor of the present invention has an extremely high electric field from 2.67> 105乂^111 lowered to 2.14><105 Figure 4 is a graph showing the relationship between the drain-source output current L and the drain-source voltage 乂^ of an RSD thin film transistor and a conventional polycrystalline germanium transistor according to an embodiment of the present invention. - Under the condition that the source voltage Vgs is from 〇1 to 1〇乂 and the core is 〇~2〇V, it can be clearly found that the RSD film structure of the present invention has a kink current relative to the conventional polycrystalline germanium film transistor. The improvement is mainly because the RSD structure has the effect of reducing the electric field, and the inner sidewall can also spread the intensity of the electric field. Therefore, it is proved that the Rs〇 thin film transistor can effectively reduce the high electric field of the 汲 extreme, and further FIG. 5 is a graph showing the relationship between the drain-source output current Ids and the gate-source voltage Vgs of the rSd thin film transistor and the conventional polycrystalline germanium thin film transistor according to an embodiment of the present invention, and FIG. It can be clearly seen that in the case where Vds is 5V and V is -15V, the leakage current of the RSD thin film transistor of the present invention is significantly smaller than that of the conventional type, and can be reduced from 651 pA to 133 pA. Mainly due to The combination of the inner sidewall and the RSD structure greatly reduces the high electric field of the 汲 extremes, thus reducing the gate leakage current caused by the gate, which proves that the RSD thin film transistor of the present invention can effectively reduce the high electric field of the 汲 extreme to reduce Its leakage current' also proves the reliability of the previous analog data. It is also worth noting that the leakage current of the RSD thin film transistor is slightly larger than that of the conventional type when the Vds is 0.1 V, which may be due to the formation of the inner sidewall. The dry etching machine is used to etch the sidewalls, so the interface trap state density is slightly larger than that of the conventional type, so that the leakage current is slightly larger than the conventional type. 6 is a breakdown voltage curve of an RSD thin film transistor and a conventional type at different channel lengths according to an embodiment of the present invention, which is the same as that after the treatment of the ammonia plasma energy of 2 〇〇 w and time 30 minutes, which can be found in FIG. 6 The breakdown voltage of the RSD thin film transistor of the present invention is significantly higher than that of the conventional type under different channel lengths, especially twice as large as the conventional type in the case of 6 μm, which again proves that the RSD thin film transistor of the present invention is lowered. The ability of the electric field, therefore, the RSD thin film transistor of the present invention can also have good operational characteristics under short channel operation. The invention provides a thin film transistor combining the spacer structure of the thick source drain and the inner sidewall, and does not need to use chemical mechanical polishing and ion implantation technology. From the electric field strength curve and the output characteristic diagram, it can be seen that the electric field in the channel has Significantly a lot of reduction, mainly because the spacers on the inner sidewall and the thick source have a hot spot away from the channel region, and the intensity of the electric field is more diffused' can more effectively reduce the extreme high electric field and improve the components. Kinking 201121053 effect, hot carrier effect, etc., further reduce leakage current. Furthermore, since the thick source does not reduce its series resistance, the high electric field of the device 汲 extreme can be reduced; and the spacer of the inner sidewall is equivalent to the FID structure, which can effectively reduce the space charge region in the channel. The peak electric field, combined with these two structures, can more effectively reduce j: and extreme high electric fields, and does not require the use of high-cost processes such as ion implantation and chemical mechanical polishing. The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the present invention is not limited by the scope of the invention, and is intended to cover various modifications and modifications of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B show a conventional thin film transistor structure having a thick source drain; FIGS. 2A to 2G show a method of fabricating a thin film transistor structure according to an embodiment of the present invention; FIG. 4 and FIG. 5 are graphs showing the relationship between current and voltage of an rSD thin film transistor according to an embodiment of the present invention; and FIG. 5 is a view showing an embodiment of the present invention according to an embodiment of the present invention; The relationship between the length of the rSD thin film transistor and the conventional channel length and breakdown voltage. [Main component symbol description] 10 thick source drain structure 丨丨 carrier board I S1 -12- 201121053
12 源極 13 14 通道區 15 16 閘極層 20 厚源汲極架構 21 22 源極 23 24 氮化矽層 25 26 通道區 27 30 薄膜電晶體結構 31 32 載板 33 34 凹陷 35 36 開口 37 38 間隔物 39 40 閘極層 43 44 源極區域 45 51 第一連接面 52 53 第三連接面 汲極 閘極介電層 載板 汲極 閘極介電層 閘極層 基板 半導體層 絕緣層 内侧壁 閘極介電層 通道區 〉及極區域 第二連接面 13-12 Source 13 14 Channel region 15 16 Gate layer 20 Thick source drain structure 21 22 Source 23 24 Tantalum nitride layer 25 26 Channel region 27 30 Thin film transistor structure 31 32 Carrier 33 34 Recess 35 36 Opening 37 38 Spacer 39 40 gate layer 43 44 source region 45 51 first connection surface 52 53 third connection surface drain gate dielectric layer carrier pad gate dielectric layer gate layer substrate semiconductor layer insulation layer inner sidewall Gate dielectric layer channel area> and pole area second connection surface 13-