TWI865100B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a first package and a second package. The first package includes a substrate, a plurality of conductive pillars, an interposer and an encapsulant. The conductive pillars are disposed on the substrate. between adjacent conductive pillars has first pitch. The interposer is disposed on the conductive pillars. The encapsulant encapsulates the interposer and the conductive pillars. The second package is disposed on the first package and includes a plurality of conductive terminals. between adjacent conductive terminals has a second pitch which greater than the first pitch, and the first package is electrically connected to the second package through the interposer. A manufacturing method of a semiconductor package structure is also provided.

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a semiconductor package structure and a manufacturing method thereof.

Semiconductor packaging technology is continuously improving in an attempt to develop more competitive products. For example, 3D stacking technologies such as PoP packaging have been developed. However, due to limitations such as ball placement capabilities, the pitch cannot be effectively reduced, and thus cannot meet the requirements for higher packaging density.

The present invention provides a semiconductor package structure and a manufacturing method thereof, which can meet the requirements of higher packaging density.

A semiconductor package structure of the present invention includes a first package and a second package. The first package includes a substrate, a plurality of conductive posts, an intermediate component and a sealing body. The plurality of conductive posts are arranged on the substrate. There is a first distance between adjacent conductive posts. The intermediate component is arranged on the plurality of conductive posts. The sealing body encapsulates the intermediate component and the plurality of conductive posts. The second package is arranged on the first package and includes a plurality of conductive terminals. There is a second distance between adjacent conductive terminals that is greater than the first distance, and the first package is electrically connected to the second package through the intermediate component.

In one embodiment of the present invention, the sealing body fills the space between the interposer and the substrate.

In one embodiment of the present invention, the sealing body extends from the top surface of the interposer to the top surface of the substrate.

In an embodiment of the present invention, the interposer comprises a plurality of joint terminals, and the sealing body covers the side walls of the plurality of joint terminals and the side walls of the plurality of conductive pillars.

In one embodiment of the present invention, the top surface of the sealing body is coplanar with the top surface of the intermediate member.

In one embodiment of the present invention, the intermediate member is retracted into the sealing body.

In one embodiment of the present invention, the size of the interposer is smaller than that of the substrate.

In an embodiment of the present invention, the intermediary component includes a plurality of separated intermediary units, and a portion of the sealing body is filled between two adjacent ones of the plurality of intermediary units.

The manufacturing method of a semiconductor package structure of the present invention comprises at least the following steps: forming a plurality of conductive pillars on a substrate, wherein adjacent conductive pillars have a first spacing; bonding an interposer to the plurality of conductive pillars; forming a sealing body to encapsulate the interposer and the plurality of conductive pillars to form a first package; and bonding a second package to the interposer, wherein the second package comprises a plurality of conductive terminals, wherein adjacent conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package via the interposer.

In one embodiment of the present invention, a singulation process is performed between forming the sealing body and bonding the second packaging component.

Based on the above, the bottom package of the semiconductor package structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I/O terminals of the semiconductor package structure, thereby meeting the requirements of higher packaging density.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or dimensions of layers or regions in the drawings may be exaggerated for clarity, and some components may be omitted for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

The term "between" used in this specification to define a numerical range is intended to cover ranges equal to the endpoint values and between the endpoint values. For example, a size range is between a first value and a second value, which means that the size range can cover the first value, the second value, and any value between the first value and the second value.

Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

Figures 1A to 1D are partial cross-sectional schematic diagrams of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Figure 2 is a partial top view schematic diagram of a stage corresponding to Figure 1A according to some embodiments of the present invention. Figure 3 is a partial top view schematic diagram of a stage corresponding to Figure 1B according to some embodiments of the present invention. Figures 4 and 5 are partial top view schematic diagrams of a stage corresponding to Figure 1C according to some embodiments of the present invention.

Referring to FIG. 1A , in this embodiment, the manufacturing process of the semiconductor package structure may include the following steps. First, a substrate 110 is provided, wherein the substrate 110 has a top surface 110t and a bottom surface 110b opposite to each other. Next, a plurality of conductive pillars 120 may be formed on the top surface 110t of the substrate 110, and adjacent conductive pillars 120 have a spacing 120p (which may be regarded as a first spacing) therebetween. Here, the spacing 120p may be formed by the center points between adjacent conductive pillars 120. Since the conductive pillars 120 are formed using a fine process (manufactured by photomask exposure followed by electroplating, the accuracy of the photomask can provide a finer spacing), the spacing 120p is a fine pitch. For example, the spacing 120p may be at least less than 200 microns, but the present invention is not limited thereto, and the spacing may also have other appropriate definitions.

In addition, as shown in FIG. 1A , a chip 130 may be disposed on the top surface 110t of the substrate 110. According to actual design requirements, in some embodiments, the conductive pillar 120 is formed first and then the chip 130 is disposed. In other embodiments, the chip 130 is disposed first and then the conductive pillar 120 is formed.

In some embodiments, the substrate 110 may be a circuit substrate including a circuit 111, a protective layer 112 and a conductive pad 113. For example, the substrate 110 is a plate made of an organic material or an inorganic material, in which the circuit 111 is formed, and on opposite surfaces thereof, the conductive pad 113 and the protective layer 112 electrically isolating the conductive pad 113 are formed. The circuit 111 and the conductive pad 113 may be formed by, for example, aluminum, copper, tin, nickel, gold, silver or other suitable conductive materials, and the protective layer 112 may be formed by green paint or other suitable insulating materials, but the present invention is not limited thereto, and the substrate 110 may also be other suitable substrate types.

In some embodiments, the conductive post 120 is disposed on the conductive pad 113 and electrically connected to the substrate 110, and the conductive post 120 is a copper post (Cu post) made by electroplating method, but the present invention is not limited thereto, and the conductive post 120 can also be formed by other appropriate conductive materials and deposition processes.

On the other hand, in the present embodiment, the chip 130 is electrically connected to the substrate 110 by means of a plurality of bumps 131 using a flip chip bonding technique, such that the active surface 130a of the chip 130 faces the substrate 110, but the present invention is not limited thereto. In an embodiment not shown, the chip may also be electrically connected to the substrate 110 by means of wire bonding, such that the active surface of the chip faces away from the substrate.

Please refer to Figure 1B, the interposer 300 is bonded to multiple conductive pillars 120, wherein the interposer 300 may include a substrate 310 and bonding terminals 320, and the bonding terminals 320 are in direct contact with the conductive pillars 120, so that the conductive pillars 120 can become an electrical connection path between the interposer and the substrate 110 to achieve electrical conduction in the stacking direction, but the present invention is not limited to this.

In some embodiments, substrate 310 is similar to substrate 110, and thus substrate 310 may be a circuit substrate including circuit 311, protective layer 312, and conductive pad 313. For example, substrate 310 is a plate made of organic material or inorganic material, in which circuit 311 is formed, and conductive pad 313 and protective layer 312 electrically isolating conductive pad 313 are formed on opposite surfaces thereof, wherein circuit 311 and conductive pad 313 may be formed by, for example, aluminum, copper, tin, nickel, gold, silver, or other suitable conductive materials, and protective layer 312 may be formed by green paint or other suitable insulating materials, but the present invention is not limited thereto, and substrate 310 may also be other suitable substrate types.

In some embodiments, the portion of the circuit 311 that overlaps with the conductive pillar 120 in the orthographic projection direction includes a plating through hole (PTH), wherein the plating through hole is formed in a plated layer in a through hole in the substrate 310. Since the plating through hole can also be made using a fine process, such as penetrating the base material of the interposer 300 with a laser and then plating, it can correspond to the fine pitch of the conductive pillar 120 with the precision of the laser. In addition, a suitable resin material 314 can be optionally formed in the aforementioned through hole to further improve the electrical performance, but the present invention is not limited thereto.

In some embodiments, the connection terminal 320 is a solder formed by solder paste printing, micro balling or electroplating, but the present invention is not limited thereto. The connection terminal 320 can also be formed by other suitable conductive materials and deposition processes.

In some embodiments, when the connection terminal 320 is solder, the interposer 300 can be electrically connected to the plurality of conductive pillars 120 by performing a reflow process on the connection terminal 320, wherein after the reflow process, the connection terminal 320 can be wrapped around the sidewall of the conductive pillar 120 to increase adhesion and improve the connection quality, but the present invention is not limited thereto. It should be noted that, since the sealing body 140 shown in FIG. 1C has not yet been formed in this step, the interposer 300 can be supported only by the conductive pillars 120 during the reflow process.

In some embodiments, the interposer 300 does not include a function die. In other words, the interposer 300 only has a circuit fan-out function. Therefore, the thickness of the interposer 300 can be effectively reduced. The thickness range can be determined according to actual design requirements and is not limited by the present invention.

1C , a sealing body 140 is formed to encapsulate the interposer 300, the chip 130, and the plurality of conductive pillars 120 to form a package 100 (which can be regarded as a first package), wherein the sealing body 140, for example, extends from the side wall 300a of the interposer 300 to the top surface 110t of the substrate 110 to completely encapsulate the components on the top surface 110t of the substrate 110, but the present invention is not limited thereto.

In some embodiments, the sealing body 140 is formed of insulating materials such as epoxy resin or other suitable resins. For example, a molding compound is formed by a molding process, and the molding process is performed after the conductive column 120 and the interposer 300 are joined. At this time, an electrical connection has been formed between the conductive column 120 and the interposer 300. Therefore, it is not necessary to perform steps such as through mold via (TMV) on the sealing body 140 in order to expose the conductive column for electrical connection. Therefore, the cost of performing steps such as through mold via (TMV) can be reduced (such as damage such as melting and shorting of the conductive column due to excessive laser power), thereby effectively reducing the manufacturing cost. Compared with the V-shaped molded through hole, the conductive column 120 can meet the fine pitch requirement.

In some embodiments, part of the sealing body 140 fills the space between the conductive bumps 131, thereby replacing the underfill process to provide good electrical isolation between the conductive bumps 131. In this way, the process can be more effectively simplified to reduce the manufacturing cost, but the present invention is not limited thereto.

In some embodiments, the sealing body 140 may fill the space between the interposer 300 and the substrate 110. In other words, there is no gap between the interposer 300 and the substrate 110, but the present invention is not limited thereto.

In some embodiments, the sealing body 140 covers the sidewalls 320s of the connecting terminal 320 and the sidewalls 120s of the connecting member 120, so that the interposer 300 can be embedded in the sealing body 140 to be more completely protected and improve product reliability, but the present invention is not limited thereto.

In some embodiments, the top surface 140t of the sealing body 140 and the top surface 300t of the intermediary member 300 are substantially coplanar, that is, the top surface 140t of the sealing body 140 and the top surface 300t of the intermediary member 300 are located on the same horizontal plane, but the present invention is not limited thereto.

In some embodiments, the interposer 300 is retracted into the sealing body 140. For example, as shown in FIGS. 2 to 4 , the size of the interposer 300 is smaller than the size of the substrate 110 (the interposer 300 is, for example, the solid line portion of FIG. 3 ). Therefore, the interposer 300 exposes the edge of the substrate 110 to form a channel, and the sealing body 140 can flow into the space between the interposer 300 and the substrate 110 through the aforementioned channel, and the interposer 300 is a single component, but the present invention is not limited to this. In other embodiments, as shown in FIG. 5 , the interposer 300 includes a plurality of separated interposer units 300u, and a portion of the sealing body 140 is filled between two adjacent ones of the plurality of interposer units 300u. In this way, the stress borne by the conductive column 120 can be reduced, but the present invention is not limited to this. Here, although two intermediate units 300u are schematically shown in FIG. 5 , the present invention does not limit the number of intermediate units 300u, and the number can be determined according to actual design requirements.

In some embodiments, multiple intermediate units 300u include cutting lanes (not shown), so after joining the intermediate component 300 (before joining the package 200 shown in Figure 1D), a singulation process can be performed first, wherein the singulation process is, for example, cutting with a rotating blade or a laser beam to form multiple discrete intermediate units 300u and corresponding packages 100, but the present invention is not limited to this.

1D , the package 200 (which can be regarded as a second package) is bonded to the interposer 300 to form a stacked semiconductor package structure 10 (which can be regarded as a PoP structure), wherein the package 200 includes a plurality of conductive terminals 220, and adjacent conductive terminals 220 have a spacing 220p (which can be regarded as a second spacing) greater than the spacing 120p, and the package 100 can be electrically connected to the package 200 through the interposer 300. Here, the spacing 220p is formed by the center point between adjacent conductive terminals 220, and the spacing 220p can be at least greater than 400 microns, but the present invention is not limited thereto, and the spacing can also have other appropriate definition methods.

Accordingly, the bottom package 100 of the semiconductor package structure 10 of the present embodiment can effectively reduce the pitch by designing the conductive pillar 121, and by introducing the interposer 300, the bottom package 100 with a fine pitch can be fanned out to the top package 200 with a coarse pitch, so as to increase the number of I/O terminals of the semiconductor package structure 10, thereby meeting the requirements of higher packaging density.

In some embodiments, the conductive terminal 220 may be a solder ball formed by a ball placement process, but the present invention is not limited thereto. Based on design requirements, the conductive terminal 220 may have other possible forms and shapes.

In some embodiments, other components of the package 200 have a similar formation structure to the package 100. For example, the package 200 further includes a substrate 210, a chip 230 and a sealing body 240, wherein the substrate 210, the chip 230 and the sealing body 240 are similar to the substrate 110, the chip 130 and the sealing body 140, and are not described again herein.

It should be noted that the package 100 and the package 200 can be configured with other components according to actual design requirements, and the chip 130 and the chip 230 can select appropriate chip types according to actual design requirements, for example, the chip 130 is an application-specific integrated circuit (ASIC) or the like, and the chip 230 is a dynamic random access memory (DRAM) or a NAND flash memory or the like, or it can also be an application-specific integrated circuit (ASIC) or the like that is the same as the chip 130.

In some embodiments, before or after bonding the package 200, a conductive terminal 400 is further formed on the bottom surface 110b of the substrate 110 to further electrically connect with other semiconductor elements (not shown), wherein the conductive terminal 400 can be a solder ball formed by a ball implantation process or can have other possible forms and shapes based on design requirements, and the present invention is not limited thereto.

In summary, the bottom package of the semiconductor package structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I/O terminals of the semiconductor package structure, thereby meeting the requirements of higher packaging density.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10:Semiconductor packaging structure

100, 200: packaging

110, 210, 310: substrate

111, 311: Line

112, 312: Protective layer

113, 313: Conductive pad

110t, 122t, 140t: Top surface

110b: bottom surface

120: Conductive column

120s, 300s, 320s: Sidewall

220, 400: Conductive terminal

120p, 220p: Pitch

130, 230: Chip

130a: Active surface

131: Bump

140, 240: Sealing body

300:Intermediary

314: Resin material

300u:Intermediary unit

320:Joint terminal

Figures 1A to 1D are partial cross-sectional schematic diagrams of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Figure 2 is a partial top view schematic diagram of a stage corresponding to Figure 1A according to some embodiments of the present invention. Figure 3 is a partial top view schematic diagram of a stage corresponding to Figure 1B according to some embodiments of the present invention. Figures 4 and 5 are partial top view schematic diagrams of a stage corresponding to Figure 1C according to some embodiments of the present invention.

10:Semiconductor packaging structure

100, 200: packaging parts

110, 210, 310: Substrate

111, 311: Lines

112, 312: Protective layer

313: Conductive pad

110t, 140t: Top surface

110b: bottom surface

120: Conductive column

220, 400: Conductive terminal

220p: Pitch

130, 230: Chip

131: Bump

140, 240: Sealing body

300:Intermediary

314: Resin material

320:Joint terminal

Claims (10)

A semiconductor package structure includes: a first package, including: a substrate; a plurality of conductive pillars, arranged on the substrate, wherein adjacent conductive pillars have a first spacing; an intermediary, arranged on the plurality of conductive pillars, wherein the intermediary includes a plurality of bonding terminals, wherein the plurality of bonding terminals cover the side walls of the plurality of conductive pillars; and a sealing body, encapsulating the intermediary and the plurality of conductive pillars; and a second package, arranged on the first package and including a plurality of conductive terminals, wherein adjacent conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package via the intermediary. A semiconductor package structure as described in claim 1, wherein the sealing body fills the space between the interposer and the substrate. A semiconductor package structure as described in claim 1, wherein the sealing body extends from the side wall of the interposer to the top surface of the substrate. A semiconductor package structure as described in claim 1, wherein the sealing body covers the side walls of the plurality of bonding terminals and the side walls of the plurality of conductive pillars. A semiconductor package structure as described in claim 1, wherein the top surface of the sealing body is coplanar with the top surface of the interposer. A semiconductor package structure as described in claim 1, wherein the interposer is retracted within the sealing body. A semiconductor package structure as described in claim 1, wherein the size of the interposer is smaller than the size of the substrate. A semiconductor package structure as described in claim 1, wherein the interposer includes a plurality of separated interposer units, and a portion of the sealing body is filled between two adjacent interposer units. A method for manufacturing a semiconductor package structure includes: forming a plurality of conductive pillars on a substrate, wherein adjacent conductive pillars have a first spacing; bonding an interposer to the plurality of conductive pillars, wherein the interposer includes a plurality of bonding terminals, and the plurality of bonding terminals cover the side walls of the plurality of conductive pillars; forming a sealing body to encapsulate the interposer and the plurality of conductive pillars to form a first package; and bonding a second package to the interposer, wherein the second package includes a plurality of conductive terminals, and adjacent conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package via the interposer. A method for manufacturing a semiconductor package structure as described in claim 9, wherein a singulation process is performed between forming the sealing body and bonding the second package.

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