TWI863620B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a first package, an interposer and a second package. The first package includes a substrate, a plurality of bonding components, and an encapsulant. The bonding components are disposed on the substrate. Each bonding component includes a conductive pillar and a first conductive terminal, and between adjacent conductive pillar has first pitch. The encapsulant encapsulates the bonding components. The interposer is disposed on the first package. The second package is disposed on the interposer and includes a plurality of second conductive terminals. between adjacent second conductive terminal has a second pitch which greater than the first pitch, and the first package is electrically connected to the second package through the interposer. A manufacturing method of a semiconductor package structure is also provided.

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a semiconductor package structure and a manufacturing method thereof.

Semiconductor packaging technology is continuously improving in an attempt to develop more competitive products. For example, 3D stacking technologies such as PoP packaging have been developed. However, due to limitations such as ball placement capabilities, the pitch cannot be effectively reduced, and thus cannot meet the requirements for higher packaging density.

The present invention provides a semiconductor package structure and a manufacturing method thereof, which can meet the requirements of higher packaging density.

A semiconductor package structure of the present invention includes a first package, an intermediate component and a second package. The first package includes a substrate, a plurality of bonding components and a sealing body. The plurality of bonding components are arranged on the substrate. Each bonding component includes a conductive column and a first conductive terminal, and there is a first distance between adjacent conductive columns. The sealing body encapsulates the plurality of bonding components. The intermediate component is arranged on the first package. The second package is arranged on the intermediate component and includes a plurality of second conductive terminals. There is a second distance between the second conductive terminals that is greater than the first distance, and the first package is electrically connected to the second package through the intermediate component.

In one embodiment of the present invention, the plurality of joining components are recessed in the sealing body.

In one embodiment of the present invention, the interposer comprises a plurality of intermediate conductive terminals, wherein the intermediate conductive terminals extend into the sealing body and directly contact the first conductive terminals to form a bonding interface, and the bonding interface is lower than the top surface of the sealing body.

In one embodiment of the present invention, the height of the sealing body is greater than the height of each bonding component.

In an embodiment of the present invention, the first package further comprises a chip. The chip is disposed on a substrate, and the sealing body encapsulates the chip and has a gap with the substrate of the interposer.

In one embodiment of the present invention, the chip includes a plurality of conductive bumps, and a portion of the sealing body fills the space between the plurality of conductive bumps.

In one embodiment of the present invention, the size of the interposer is smaller than that of the substrate.

In an embodiment of the present invention, the intermediary component includes a plurality of separated intermediary units, and a portion of the sealing body is filled between two adjacent ones of the plurality of intermediary units.

The manufacturing method of a semiconductor package structure of the present invention comprises at least the following steps: forming a plurality of bonding components on a substrate, wherein each bonding component comprises a conductive column and a first conductive terminal, and adjacent conductive columns have a first spacing; forming a sealing body to encapsulate the plurality of bonding components; forming a plurality of openings in the sealing body to expose the plurality of bonding components, so as to form a first package; bonding an interposer to the first package; and bonding a second package to the interposer, wherein the second package comprises a plurality of second conductive terminals, adjacent second conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package via the interposer.

In one embodiment of the present invention, the method for manufacturing the semiconductor package structure further includes performing a laser drilling process to form a plurality of openings.

Based on the above, the bottom package of the semiconductor package structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I/O terminals of the semiconductor package structure, thereby meeting the requirements of higher packaging density.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or dimensions of layers or regions in the drawings may be exaggerated for clarity, and some components may be omitted for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

The term "between" used in this specification to define a numerical range is intended to cover ranges equal to the endpoint values and between the endpoint values. For example, a size range is between a first value and a second value, which means that the size range can cover the first value, the second value, and any value between the first value and the second value.

Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

Figures 1A to 1F are partial cross-sectional schematic diagrams of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Figure 2 is a partial top view schematic diagram of a stage corresponding to Figure 1D according to some embodiments of the present invention. Figures 3 and 4 are partial top view schematic diagrams of a stage corresponding to Figure 1E according to some embodiments of the present invention.

Referring to FIG. 1A , in this embodiment, the manufacturing process of the semiconductor package structure may include the following steps. First, a substrate 110 is provided, wherein the substrate 110 has a top surface 110t and a bottom surface 110b opposite to each other. Then, a plurality of bonding components 120 may be formed on the top surface 110t of the substrate 110, wherein each bonding component 120 includes a conductive column 121 and a conductive terminal 122 (which may be regarded as a first conductive terminal), and adjacent conductive columns 121 have a spacing 121p (which may be regarded as a first spacing). Here, the spacing 121p can be formed by the center points between adjacent conductive pillars 121. Since the conductive pillars 121 are formed using a fine process (manufactured by photomask exposure followed by electroplating, the accuracy of the photomask can provide a finer spacing), the spacing 121p is a fine pitch. For example, the spacing 121p can be at least less than 200 microns, but the present invention is not limited thereto, and the spacing can also have other appropriate definitions.

In some embodiments, the substrate 110 may be a circuit substrate including a circuit 111, a protective layer 112 and a conductive pad 113. For example, the substrate 110 is a plate made of an organic material or an inorganic material, in which the circuit 111 is formed, and on opposite surfaces thereof, the conductive pad 113 and the protective layer 112 electrically isolating the conductive pad 113 are formed. The circuit 111 and the conductive pad 113 may be formed by, for example, aluminum, copper, tin, nickel, gold, silver or other suitable conductive materials, and the protective layer 112 may be formed by green paint or other suitable insulating materials, but the present invention is not limited thereto, and the substrate 110 may also be other suitable substrate types.

In some embodiments, the conductive post 121 and the conductive terminal 122 are disposed on the conductive pad 113 and electrically connected to the substrate 110, and the conductive post 121 is a copper post (Cu post) manufactured by an electroplating method, and the conductive terminal 122 is a solder formed by solder paste printing, micro-ball drop or electroplating, but the present invention is not limited thereto, and the conductive post 121 and the conductive terminal 122 can also be formed by other suitable conductive materials and deposition processes.

Referring to FIG. 1B , a chip 130 may be disposed on the top surface 110t of the substrate 110, and in the present embodiment, the chip 130 is electrically connected to the substrate 110 by a plurality of bumps 131 using a flip chip bonding technique, such as the active surface 130a of the chip 130 faces the substrate 110, but the present invention is not limited thereto. In an embodiment not shown, the chip may also be electrically connected to the substrate 110 by wire bonding, such as the active surface of the chip faces away from the substrate. In addition, although FIG. 1A and FIG. 1B show that a plurality of bonding components 120 are formed first and then the chip 130 is formed, the present invention is not limited thereto. In an embodiment not shown, the chip may also be formed first and then the plurality of bonding components may be formed.

1C , a sealing body 140 is formed to encapsulate the bonding component 120 and the chip 130, wherein a height 140T of the sealing body 140 is greater than a height 120T of the bonding component 120. For example, a top surface 140t of the sealing body 140 may be higher than a top surface 122t of a conductive terminal 122 in the bonding component 120. In other words, the conductive terminal 122 may be located below a horizontal extension plane of the top surface 140t of the sealing body 140, but the present invention is not limited thereto.

In some embodiments, part of the sealing body 140 is filled into the space between the conductive bumps 131, thereby replacing the underfill process to provide good electrical isolation between the conductive bumps 131. In this way, the process can be effectively simplified to reduce the manufacturing cost, but the present invention is not limited thereto.

In some embodiments, a distance between the top surface 140t of the sealing body 140 and the back surface of the chip 130 is greater than zero, that is, the back surface of the chip 130 is covered by the sealing body 140 and is not exposed, but the present invention is not limited thereto.

In some embodiments, the sealing body 140 is formed of insulating materials such as epoxy resin or other suitable resins, and is, for example, a molding compound formed by a molding process. However, the present invention is not limited thereto, and the sealing body 140 may be formed by other suitable materials and methods.

Please refer to Figure 1D, multiple openings 141 exposing multiple bonding components 120 are formed in the sealing body 140 to constitute a package 100 (which can be regarded as a first package), so that the bonding components 120 can be recessed in the sealing body 140. In this way, the sealing body 140 can support the conductive column 121 to reduce the stress on the conductive column 121 during the subsequent bonding process of the interposer 300, thereby reducing the probability of the conductive column 121 breaking, but the present invention is not limited to this.

In this embodiment, the opening 141 exposes a portion of the conductive pillar 121 and the conductive terminal 122 and the width of the bottom of the opening 141 is greater than the width of the conductive pillar 121 , but the present invention is not limited thereto. In an embodiment not shown, the opening may only expose the conductive terminal.

In some embodiments, the opening 141 is formed by laser drilling, so that in a cross-sectional view, the opening 141 has a conical shape (the top width is greater than the bottom width), and the bottom of the opening 141 can be lower than the conductive terminal 122 to effectively expose the conductive terminal 122, but the present invention is not limited thereto, and the opening 141 can also be formed by other appropriate processes.

In some embodiments, in order to simplify the manufacturing process, the conductive terminal 122 is formed before the opening 141, so the conductive terminal 122 may not fill the opening 141 and does not extend to the top surface 140t of the sealing body 140. In addition, the joint position of other components and the conductive terminal 122 is limited within the opening 141, but the present invention is not limited thereto.

In some embodiments, the bonding assembly 120 is located on two sides of the sealing body 140. In other words, the bonding assembly 120 is not disposed on four sides of the sealing body 140 at the same time, as shown in FIG. 2, but the present invention is not limited thereto.

1E , the interposer 300 is bonded to the package 100, wherein the interposer 300 includes a substrate 310 and an interposer assembly 320, and each interposer assembly 320 includes a conductive pillar 321 and a conductive terminal 322 (which can be regarded as an intermediate conductive terminal). In addition, the interposer assembly 320 is in direct contact with the bonding assembly 120, so that the interposer 300 is electrically connected to the package 100.

In some embodiments, substrate 310 is similar to substrate 110, and thus substrate 310 may be a circuit substrate including circuit 311, protective layer 312, and conductive pad 313. For example, substrate 310 is a plate made of organic material or inorganic material, in which circuit 311 is formed, and conductive pad 313 and protective layer 312 electrically isolating conductive pad 313 are formed on opposite surfaces thereof, wherein circuit 311 and conductive pad 313 may be formed by, for example, aluminum, copper, tin, nickel, gold, silver, or other suitable conductive materials, and protective layer 312 may be formed by green paint or other suitable insulating materials, but the present invention is not limited thereto, and substrate 310 may also be other suitable substrate types.

In some embodiments, the conductive pillar 321 and the conductive terminal 322 are disposed on the conductive pad 313 and electrically connected to the substrate 310, and the intermediate component 320 is similar to the bonding component 120, so the conductive pillar 321 is a copper pillar made by electroplating, and the conductive terminal 322 is a solder formed by solder paste printing, micro balling or electroplating, but the present invention is not limited to this, and the conductive pillar 321 and the conductive terminal 322 can also be formed by other suitable conductive materials and deposition processes.

In some embodiments, when the conductive terminals 322 and the conductive terminals 122 are solder, a reflow process can be performed on the conductive terminals 322 and the conductive terminals 122 in the opening 141, so that the interposer 300 is electrically connected to the package 100. In addition, when the opening 141 is formed by a laser drilling process, a larger accommodation space can be formed, so the amount of solder used for the conductive terminals 122 and the conductive terminals 322 can be increased. In this way, after the reflow process, the non-wetting problem caused by the warp between the package 100 and the interposer 300 can be reduced, thereby improving the product quality, but the present invention is not limited thereto.

In some embodiments, after the interposer 300 is joined to the package 100, the conductive terminals 122 and the conductive terminals 322 are not respectively covered on the side walls of the conductive posts 121 and the conductive posts 321. In other words, the conductive terminals 122 and the conductive terminals 322 are respectively only located on the top surfaces of the conductive posts 121 and the conductive posts 321 to effectively avoid the risk of short circuits caused by overflow of the conductive material in the horizontal direction, thereby increasing product reliability. However, the present invention is not limited to this. In embodiments not shown, the conductive terminals may be covered on the side walls of the conductive posts and may optionally contact the sealing body. It should be noted that in any of the aforementioned implementations, the conductive terminals 122 and the conductive terminals 322 will only flow within the openings 141 and will not overflow onto the top surface 140 t of the sealing body 140 .

In the present embodiment, adjacent openings 141 are separated to prevent solder from overflowing horizontally to the tops of adjacent openings 141, thereby effectively preventing short circuits from occurring. However, the present invention is not limited thereto. In an embodiment not shown, the tops of adjacent openings may be connected together (e.g., the tops overlap), so that adjacent conductive terminals may be considered to be exposed by the same opening.

In some embodiments, the conductive terminal 322 extends into the sealing body 140 to directly contact the conductive terminal 122 and form a bonding interface, and the bonding interface is lower than the top surface 140t of the sealing body 140, but the present invention is not limited thereto.

In some embodiments, a gap G is provided between the sealing body 140 and the substrate 310 of the interposer 300. For example, the substrate 310 of the interposer 300 and the sealing body 140 may not be in direct contact with each other, but the present invention is not limited thereto.

In some embodiments, as shown in FIG. 1E and FIG. 3 , the size of the interposer 300 is smaller than the size of the substrate 110 , so the interposer 300 exposes the edge of the sealing body 140 , and the interposer 300 is a single component, but the present invention is not limited thereto.

In some embodiments, as shown in FIG. 4 , the interposer 300 includes a plurality of separated interposer units 300u, and a portion of the sealing body 140 is filled between two adjacent interposer units 300u, so that the stress on the conductive pillar 121 can be reduced, but the present invention is not limited thereto. Although FIG. 4 schematically shows two interposer units 300u, the present invention does not limit the number of interposer units 300u, and the number can be determined according to actual design requirements.

In some embodiments, multiple intermediate units 300u include cutting lanes (not shown), so after joining the intermediate component 300 to the package 100, a singulation process can be performed first, wherein the singulation process is, for example, cutting with a rotating blade or a laser beam to form multiple discrete intermediate units 300u and corresponding packages 100, but the present invention is not limited to this.

In some embodiments, the interposer 300 does not include a function die. In other words, it has a circuit fan-out function. Therefore, the thickness of the interposer 300 can be effectively reduced. The thickness range can be determined according to actual design requirements and is not limited by the present invention.

1F , a package 200 (which can be regarded as a second package) is bonded to an interposer 300 to form a stacked semiconductor package structure 10 (which can be referred to as a PoP structure), wherein the package 200 includes a plurality of conductive terminals 220 (which can be regarded as second conductive terminals), adjacent conductive terminals 220 have a spacing 220p (which can be regarded as a second spacing) greater than the spacing 121p, and the package 100 can be electrically connected to the package 200 through the interposer 300. Here, the spacing 220p is formed by the center points between adjacent conductive terminals 220, and the spacing 220p can be at least greater than 400 microns, but the present invention is not limited thereto.

Accordingly, the bottom package 100 of the semiconductor package structure 10 of the present embodiment can effectively reduce the pitch by designing the conductive pillar 121, and by introducing the interposer 300, the bottom package 100 with a fine pitch can be fanned out to the top package 200 with a coarse pitch, so as to increase the number of I/O terminals of the semiconductor package structure 10, thereby meeting the requirements of higher packaging density.

In some embodiments, the conductive terminal 220 may be a solder ball formed by a ball placement process, but the present invention is not limited thereto. Based on design requirements, the conductive terminal 220 may have other possible forms and shapes.

In some embodiments, other components of the package 200 have a similar formation structure to the package 100. For example, the package 200 includes a substrate 210, a chip 230 and a sealing body 240, wherein the substrate 210, the chip 230 and the sealing body 240 are similar to the substrate 110, the chip 130 and the sealing body 140, and are not described again herein.

It should be noted that package 100 and package 200 may be configured with other components according to actual design requirements, and chip 130 and chip 230 may select appropriate chip types according to actual design requirements, for example, chip 130 may be an application-specific integrated circuit (ASIC) or the like and chip 230 may be a dynamic random access memory (DRAM) or a NAND flash memory or the like, or may be an application-specific integrated circuit (ASIC) or the like that is the same as chip 130.

In some embodiments, the semiconductor package structure 10 further includes a conductive terminal 400 to further electrically connect with other semiconductor elements (not shown), wherein the conductive terminal 400 can be a solder ball formed by a ball implantation process or can have other possible forms and shapes based on design requirements, and the present invention is not limited thereto.

In summary, the bottom package of the semiconductor package structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I/O terminals of the semiconductor package structure, thereby meeting the requirements of higher packaging density.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10:Semiconductor packaging structure

100, 200: packaging

110, 210, 310: substrate

111, 311: Line

112, 312: Protective layer

113, 313: Conductive pad

110t, 122t, 140t: Top surface

110b: bottom surface

120:Joint assembly

120T, 140T: Height

121, 321: Conductive column

122, 220, 322, 400: conductive terminals

121p, 220p: Pitch

130, 230: Chip

130a: Active surface

131: Bump

140, 240: Sealing body

141: Open

300:Intermediary

300u:Intermediary unit

320:Mediator Component

G: Gap

Figures 1A to 1F are partial cross-sectional schematic diagrams of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Figure 2 is a partial top view schematic diagram of a stage corresponding to Figure 1D according to some embodiments of the present invention. Figures 3 and 4 are partial top view schematic diagrams of a stage corresponding to Figure 1E according to some embodiments of the present invention.

10:Semiconductor packaging structure

100, 200: packaging parts

110, 210, 310: Substrate

111, 311: Lines

112, 312: Protective layer

113, 313: Conductive pad

121, 321: Conductive column

122, 220, 322, 400: conductive terminals

220p: Pitch

130, 230: Chip

130a: Active surface

131: Bump

140, 240: Sealing body

300:Intermediary

Claims (9)

A semiconductor package structure includes: a first package, including: a substrate; a plurality of bonding components, arranged on the substrate, wherein each of the bonding components includes a conductive column and a first conductive terminal, and the adjacent conductive columns have a first spacing; and a sealing body, encapsulating the plurality of bonding components, wherein the plurality of bonding components are recessed in the sealing body; an interposer, arranged on the first package; and a second package, arranged on the interposer and including a plurality of second conductive terminals, wherein the adjacent second conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package via the interposer. A semiconductor package structure as described in claim 1, wherein the intermediate component includes a plurality of intermediate conductive terminals, wherein the intermediate conductive terminals extend into the sealing body and directly contact the first conductive terminals to form a bonding interface, and the bonding interface is lower than the top surface of the sealing body. A semiconductor package structure as described in claim 1, wherein the height of the sealing body is greater than the height of each of the bonding components. The semiconductor package structure as described in claim 1, wherein the first package further includes a chip, the chip is disposed on the substrate, and the sealing body encapsulates the chip and has a gap with the substrate of the interposer. A semiconductor package structure as described in claim 4, wherein the chip includes a plurality of conductive bumps, and a portion of the sealing body fills the space between the plurality of conductive bumps. A semiconductor package structure as described in claim 1, wherein the size of the interposer is smaller than the size of the substrate. A semiconductor package structure as described in claim 1, wherein the interposer includes a plurality of separated interposer units, and a portion of the sealing body is filled between two adjacent interposer units. A method for manufacturing a semiconductor package structure includes: forming a plurality of bonding components on a substrate, wherein each of the bonding components includes a conductive column and a first conductive terminal, and adjacent conductive columns have a first spacing; forming a sealing body to encapsulate the plurality of bonding components; forming a plurality of openings in the sealing body to expose the plurality of bonding components to form a first package; bonding an interposer to the first package; and bonding a second package to the interposer, wherein the second package includes a plurality of second conductive terminals, adjacent second conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package via the interposer. The method for manufacturing a semiconductor package structure as described in claim 8 further includes performing a laser drilling process to form the multiple openings.

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