TWI864391B - Light-emitting element - Google Patents
Light-emitting element Download PDFInfo
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- TWI864391B TWI864391B TW111116475A TW111116475A TWI864391B TW I864391 B TWI864391 B TW I864391B TW 111116475 A TW111116475 A TW 111116475A TW 111116475 A TW111116475 A TW 111116475A TW I864391 B TWI864391 B TW I864391B
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- light
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- insulating layer
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- emitting element
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Abstract
Description
本申請案係有關於發光元件,且特別有關於半導體發光元件。 This application relates to light-emitting devices, and in particular to semiconductor light-emitting devices.
半導體發光元件,例如發光二極體,已廣泛地應用於各種照明領域中。半導體發光元件通常包含反射結構,半導體發光元件射向反射結構的光會被反射至出光面摘出,以提高出光效率。 Semiconductor light-emitting elements, such as light-emitting diodes, have been widely used in various lighting fields. Semiconductor light-emitting elements usually include a reflective structure, and the light emitted from the semiconductor light-emitting element toward the reflective structure will be reflected to the light-emitting surface to improve the light-emitting efficiency.
因此,如何調整半導體發光元件的反射結構,進而有效提升半導體發光元件之出光效率,實為研發人員研發的重點之一。 Therefore, how to adjust the reflective structure of semiconductor light-emitting elements to effectively improve the light extraction efficiency of semiconductor light-emitting elements is one of the key points of research and development.
根據本申請案之一實施例,發光元件包含半導體疊層、第一電極結構、第一圖案化絕緣層與第二圖案化絕緣層。半導體疊層包含具有第一表面的第一型半導體層、具有第二表面的第二型半導體層、以及形成於第一型半導體層與第二型半導體層之 間的主動區域。第一電極結構形成於第一表面上。第一圖案化絕緣層形成於第二表面上。第二圖案化絕緣層形成於第二表面上。第二圖案化絕緣層圍繞並連接第一圖案化絕緣層。第一圖案化絕緣層與第二圖案化絕緣層包含不同材料。 According to one embodiment of the present application, the light-emitting element includes a semiconductor stack, a first electrode structure, a first patterned insulating layer, and a second patterned insulating layer. The semiconductor stack includes a first-type semiconductor layer having a first surface, a second-type semiconductor layer having a second surface, and an active region formed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode structure is formed on the first surface. The first patterned insulating layer is formed on the second surface. The second patterned insulating layer is formed on the second surface. The second patterned insulating layer surrounds and connects the first patterned insulating layer. The first patterned insulating layer and the second patterned insulating layer include different materials.
為了對本申請案之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: In order to better understand the above and other aspects of this application, the following is a specific example, and the attached drawings are explained in detail as follows:
1,2,3:發光元件 1,2,3: Light-emitting element
11:半導體疊層 11: Semiconductor stacking
12:第一電極結構 12: First electrode structure
13:第一圖案化絕緣層 13: The first patterned insulating layer
13m:第一絕緣材料層 13m: First insulating material layer
14:第二圖案化絕緣層 14: Second patterned insulating layer
14s:絕緣表面 14s: Insulation surface
14sw,16sw:外側邊緣 14sw,16sw:outer edge
15:圖案化反射層 15: Patterned reflective layer
15’:反射層 15’: Reflection layer
15A,15A’:黏著層 15A, 15A’: Adhesive layer
16:反射阻障層 16: Reflection barrier
17:阻障層 17: Barrier layer
18:接合層 18:Joint layer
19:基板 19: Substrate
20:第二電極結構 20: Second electrode structure
21:保護層 21: Protective layer
110:第一型半導體層 110: Type I semiconductor layer
110s:第一表面 110s: First surface
111:第二型半導體層 111: Type II semiconductor layer
111s:第二表面 111s: Second surface
112:主動區域 112: Active area
131:外圍部 131: Outer periphery
131s,132s:表面 131s,132s:Surface
132:長條部 132: Long strips
151:反射區 151: Reflexology area
200:發光封裝體 200: Luminescent package
201:封裝基板 201:Packaging substrate
205:封裝牆 205: Encapsulation wall
213,214:外部電極 213,214: External electrode
230:導線 230: Conductor
232:螢光體 232: Fluorescent body
240:封裝材 240:Packaging material
300:發光裝置 300: Light-emitting device
301:燈罩 301: Lampshade
302:反射鏡 302: Reflector
303:承載部 303: Carrying part
304:發光單元 304: Light-emitting unit
305:發光模組 305: Light-emitting module
306:燈座 306: Lamp holder
307:散熱片 307: Heat sink
308:連接部 308:Connection part
309:電連接元件 309: Electrical connection components
A-A’:剖面線 A-A’: section line
T1,T2,T3:厚度 T1, T2, T3: thickness
X,Y,Z:方向 X,Y,Z: Direction
第1圖係繪示根據一實施例之發光元件1的上視透視示意圖;第2圖係為沿著第1圖所示之剖面線A-A’繪示的發光元件1的剖面示意圖;第3圖係繪示根據一實施例之反射結構的反射率模擬曲線圖;第4-6圖係繪示根據一實施例之發光元件1的部分製造步驟的下視示意圖;第7圖係繪示根據一實施例之發光元件2的剖面示意圖;第8圖係繪示根據一實施例之發光元件3的剖面示意圖;第9圖係繪示一實施例之發光元件與比較例之發光元件的功率曲線圖;第10圖係繪示不同實施例之發光元件的功率曲線圖;
第11圖係繪示根據一實施例之發光封裝體200的剖面示意圖;及第12圖係繪示根據一實施例之發光裝置300的示意圖。
FIG. 1 is a schematic diagram showing a perspective view of a light-
本說明書中所使用的序數例如「第一」、「第二」、「第三」等用詞,是用以修飾元件,其本身並不意含及代表該元件有任何之前的序數,也不代表某一元件與另一元件的順序,或是製造方法上的順序,這些序數的使用僅用來使具有相同命名的元件能做出清楚區分。另外,圖式係簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製。相同或相似的元件符號用以代表相同或相似的元件。 The ordinal numbers used in this manual, such as "first", "second", "third", etc., are used to modify the components. They do not imply or represent any previous ordinal numbers of the components, nor do they represent the order of one component and another component, or the order of the manufacturing method. These ordinal numbers are used only to make components with the same name clearly distinguishable. In addition, the drawings are simplified to facilitate the clear description of the contents of the embodiments, and the size ratios in the drawings are not drawn in proportion to the actual products. The same or similar component symbols are used to represent the same or similar components.
請同時參照第1-2圖。第1圖係繪示根據一實施例之發光元件1的上視透視示意圖,第2圖係為沿著第1圖所示之剖面線A-A’繪示的發光元件1的剖面示意圖。為了便於理解半導體疊層11、第一電極結構12、第一圖案化絕緣層13、第二圖案化絕緣層14與圖案化反射層15的相對位置關係,第1圖所示之發光元件1的上視透視示意圖僅繪示半導體疊層11、第一電極結構12、自半導體疊層11透視,被第一電極結構12遮蓋的部分第一圖案化絕緣層13、第二圖案化絕緣層14、以及圖案化反射層15,係將其他元件省略,故並未完全代表實際結構。參考第2圖所示,發光元件1可包含基板19、第二電極結構20與半導體疊
層11。第二電極結構20與半導體疊層11分別設置於基板19的相反側。半導體疊層11可包含第一型半導體層110、第二型半導體層111與形成於第一型半導體層110與第二型半導體層111之間的主動區域112。如第2圖所示,主動區域112與第一型半導體層110可沿著正Z方向依序形成於第二型半導體層111上。第一型半導體層110具有第一表面110s。第一型半導體層110之第一表面110s,例如是發光元件1的出光面。第二型半導體層111具有第二表面111s。第二型半導體層111之第二表面111s,例如是位於發光元件1的出光面之相對側的表面。在一實施例中,第一型半導體層110之第一表面110s可包含粗糙表面,以提升光提取效率。
Please refer to Figures 1 and 2 at the same time. Figure 1 is a schematic top perspective view of a light-emitting
在一實施例中,基板19包含導電材料或半導體材料,基板19可為透光或不透光的。導電透光材料包含但不限於透明導電氧化物(TCO),例如氧化鋅(ZnO)、;導電不透光材料包含但不限於金屬材料,例如鋁(Al)、銅(Cu)、鉬(Mo)、鍺(Ge)或鎢(W)等元素或上述材料之合金或疊層;半導體材料包含矽(Si)、碳化矽(SiC)、砷化鎵(GaAs)、氮化鎵(GaN)、氮化鋁(AlN)、磷化鎵(GaP)、磷砷化鎵(GaAsP)、硒化鋅(ZnSe)、硒化鋅(ZnSe)或磷化銦(InP)。 In one embodiment, the substrate 19 includes a conductive material or a semiconductor material, and the substrate 19 can be transparent or opaque. The conductive transparent material includes but is not limited to a transparent conductive oxide (TCO), such as zinc oxide (ZnO); the conductive opaque material includes but is not limited to a metal material, such as aluminum (Al), copper (Cu), molybdenum (Mo), germanium (Ge) or tungsten (W) and other elements or alloys or stacks of the above materials; the semiconductor material includes silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe), zinc selenide (ZnSe) or indium phosphide (InP).
在一實施例中,半導體疊層11為發光疊層,第一型半導體層110與第二型半導體層111可用做侷限層、載子供應層、或接觸層。主動區域112可用做發光結構。第一型半導體層
110與第二型半導體層111可包含不同摻雜類型的半導體材料以供應載子,例如第一型半導體層110包含n型半導體層,第二型半導體層111包含p型半導體層,以分別提供電子與電洞,或者第一型半導體層110包含p型半導體層,第二型半導體層111包含n型半導體層,以分別提供電洞與電子。第一型半導體層110、主動區域112與第二型半導體層111可包含相同系列之III-V族化合物半導體材料,例如AlInGaAs系列、AlGaInP系列、InGaAsP系列或AlInGaN系列。其中,AlInGaAs系列可表示為(Alx1In(1-x1))1-x2Gax2As,AlInGaP系列可表示為(Alx1In(1-x1))1-x2Gax2P,AlInGaN系列可表示為(Alx1In(1-x1))1-x2Gax2N,InGaAsP系列可表示Inx1Ga1-x1Asx2P1-x2,其中,0≦x1≦1,0≦x2≦1。發光元件1例如為一發光二極體,其所發出之光線的波長取決於主動區域112之材料組成。具體來說,主動區域112之材料可包含AlInGaAs、InGaAsP、AlGaInP、InGaN或AlGaN。當主動區域112之材料為AlInGaP系列材料時,可發出波長介於610nm及650nm之間的紅光、或波長介於530nm及570nm之間的綠光。當主動區域112之材料為InGaN系列材料時,可發出波長介於400nm及490nm之間的藍光、波長介於490nm及530nm之間的青色光(Cyan)、或波長介於530nm及570nm之間的綠光。當主動區域112之材料為AlGaN系列或AlInGaN系列材料時,可發出波長介於400nm及250nm之間的紫外光。於一實施例中,主動區域112可包含單異質結構(single heterostructure)、雙異質結構(double
heterostructure)或多重量子井結構(multiple quantum wells)。在一實施例中,主動區域112包含多重量子井結構,主動區域112包含在Z方向上一次或多次交替堆疊的一或複數個量子井層(quantum well layer)與一或複數個障蔽層(barrier layer),且障蔽層的能障大於量子井層以限制載子分布,此外,複數個量子井層彼此之間可以具有相同或不同的材料組成及能障,本申請案對此不加以限制。在一實施例中,主動區域112之材料可以是i型、p型或n型半導體。
In one embodiment, the semiconductor stack 11 is a light-emitting stack, and the first type semiconductor layer 110 and the second type semiconductor layer 111 can be used as confinement layers, carrier supply layers, or contact layers. The active region 112 can be used as a light-emitting structure. The first type semiconductor layer 110 and the second type semiconductor layer 111 can include semiconductor materials of different doping types to supply carriers, for example, the first type semiconductor layer 110 includes an n-type semiconductor layer, and the second type semiconductor layer 111 includes a p-type semiconductor layer to provide electrons and holes, respectively, or the first type semiconductor layer 110 includes a p-type semiconductor layer, and the second type semiconductor layer 111 includes an n-type semiconductor layer to provide holes and electrons, respectively. The first type semiconductor layer 110, the active region 112 and the second type semiconductor layer 111 may include the same series of III-V compound semiconductor materials, such as AlInGaAs series, AlGaInP series, InGaAsP series or AlInGaN series. Among them, the AlInGaAs series can be expressed as (Al x1 In (1-x1) ) 1-x2 Ga x2 As, the AlInGaP series can be expressed as (Al x1 In (1-x1) ) 1-x2 Ga x2 P, the AlInGaN series can be expressed as (Al x1 In (1-x1) ) 1-x2 Ga x2 N, and the InGaAsP series can be expressed as In x1 Ga 1-x1 As x2 P 1-x2 , wherein 0≦x1≦1, 0≦x2≦1. The light-emitting
發光元件1還可包含第一電極結構12、第一圖案化絕緣層13、第二圖案化絕緣層14、圖案化反射層15與反射阻障層16。第一電極結構12可設置於第一型半導體層110之第一表面110s上。第一圖案化絕緣層13、第二圖案化絕緣層14與圖案化反射層15可設置於第二型半導體層111之第二表面111s上。於一實施例中,圖案化反射層15直接接觸第二型半導體層111,以形成一歐姆接觸。於一實施例中,圖案化反射層15與第二型半導體層111之間更包含一透明導電層(圖未示),例如氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、砷化鋁鎵(AlGaAs)、氮化鎵(GaN)、磷化鎵(GaP)、砷化鎵(GaAs)、磷砷化鎵(GaAsP)、氧化銦鋅(IZO)、類鑽碳薄膜(DLC)或石墨烯,透明導電層直接接觸第二型半導體層111,以形成一歐姆接觸。第二圖案化絕緣層14可在XY平面
上圍繞第一圖案化絕緣層13與圖案化反射層15。在一些實施例中,第二圖案化絕緣層14可連接第一圖案化絕緣層13。在一些實施例中,第一圖案化絕緣層13可連接圖案化反射層15。在另一些實施例中,第一圖案化絕緣層13可對應第一電極結構12的位置設置。例如,第一電極結構12可在Z方向上重疊於第一圖案化絕緣層13。第一電極結構12在XY平面上的面積可小於第一圖案化絕緣層13在XY平面上的面積,以避免過多的第一電極結構12面積遮蔽主動區域112發出的光。此外當第一型半導體層110為n型半導體層,第二型半導體層111為p型半導體層時,電子在第一型半導體層110橫向擴散速度大於電洞在第二型半導體層111的橫向擴散速度,因此自第二電極結構20注入的電流(電洞)藉由較大的第一圖案化絕緣層13能夠和橫向擴散較快的電子集中在主動區域112避開第一電極結構12遮蔽區域發光,以進一步減少第一電極結構12遮光的影響。反射阻障層16可設置於第一圖案化絕緣層13、第二圖案化絕緣層14與圖案化反射層15上。反射阻障層16與半導體疊層11分別設置於第一圖案化絕緣層13的相反側。
The light-emitting
具體而言,第一圖案化絕緣層13可包含外圍部131與內部,外圍部131圍繞內部。外圍部131可為封閉環形,例如方環形或圓環形等。內部的圖案可為幾何圖案,例如矩形、或圓形。於一實施例,第一圖案化絕緣層13的內部可由複數個長條部132構成,可例如沿著Y方向延伸且在X方向上彼此間隔設 置。複數個長條部132可連接外圍部131且被外圍部131所圍繞。圖案化反射層15可包含複數個反射區151。複數個反射區151可例如沿著Y方向延伸且在X方向上彼此間隔設置。第一圖案化絕緣層13之外圍部131可接觸第二圖案化絕緣層14。第一圖案化絕緣層13之複數個長條部132和圖案化反射層15之複數個反射區151可沿著X方向交錯設置。 Specifically, the first patterned insulating layer 13 may include an outer portion 131 and an inner portion, wherein the outer portion 131 surrounds the inner portion. The outer portion 131 may be a closed ring, such as a square ring or a circular ring. The pattern of the inner portion may be a geometric pattern, such as a rectangle or a circle. In one embodiment, the inner portion of the first patterned insulating layer 13 may be composed of a plurality of long strips 132, which may extend along the Y direction and be spaced apart from each other in the X direction. The plurality of long strips 132 may be connected to the outer portion 131 and surrounded by the outer portion 131. The patterned reflective layer 15 may include a plurality of reflective regions 151. The plurality of reflective regions 151 may extend along the Y direction and be spaced apart from each other in the X direction. The outer peripheral portion 131 of the first patterned insulating layer 13 may contact the second patterned insulating layer 14. The plurality of long strip portions 132 of the first patterned insulating layer 13 and the plurality of reflective regions 151 of the patterned reflective layer 15 may be arranged alternately along the X direction.
反射阻障層16可覆蓋第一圖案化絕緣層13、第二圖案化絕緣層14與圖案化反射層15。反射阻障層16接觸第一圖案化絕緣層13,並與第一圖案化絕緣層13形成全方位反射結構(omni-directional reflector;ODR),以提升發光元件1之出光效率。第一圖案化絕緣層13可用做電流阻擋層,經由第二電極結構20注入的外部電流被第一圖案化絕緣層13阻擋,再經由圖案化反射層15分佈擴散至第二型半導體層111中。於一實施例中,第一圖案化絕緣層13及/或第二圖案化絕緣層14可增加半導體疊層11和反射阻障層16之間的附著力。反射阻障層16可用以避免圖案化反射層15之材料於製程中擴散而破壞發光元件1之電性。於一實施例中,圖案化反射層15對主動區域112發出的特定波長的光,例如紫外光,具有一第一反射率,反射阻障層16對主動區域112發出的特定波長的光具有一第二反射率,且第一反射率小於第二反射率。圖案化反射層15與半導體疊層11之間有良好的電性接觸。因此藉由圖案化反射層15非整面,例如分散設置於圖案化絕緣層13之間,再藉由具有高反射率的反射阻障層
16的大面積,例如整面覆蓋,再搭配第一圖案化絕緣層13構成的全方位反射結構來增加整體的反射率,進而提高發光元件1之光電特性。
The reflection barrier layer 16 can cover the first patterned insulating layer 13, the second patterned insulating layer 14 and the patterned reflective layer 15. The reflection barrier layer 16 contacts the first patterned insulating layer 13 and forms an omni-directional reflector (ODR) with the first patterned insulating layer 13 to improve the light extraction efficiency of the
在一實施例中,第二圖案化絕緣層14包含背向半導體疊層11之絕緣表面14s,反射阻障層16可完全覆蓋第二圖案化絕緣層14的絕緣表面14s,且反射阻障層16的外側邊緣16sw可與第二圖案化絕緣層14的外側邊緣14sw切齊,例如是在Z方向上切齊。 In one embodiment, the second patterned insulating layer 14 includes an insulating surface 14s facing away from the semiconductor stack 11, the reflection barrier layer 16 can completely cover the insulating surface 14s of the second patterned insulating layer 14, and the outer edge 16sw of the reflection barrier layer 16 can be aligned with the outer edge 14sw of the second patterned insulating layer 14, for example, in the Z direction.
第一電極結構12與第二電極結構20可包含導電材料。第一電極結構12與第二電極結構20可包含相同或不同的材料。第一電極結構12與第二電極結構20可包含金屬材料或透明導電材料;例如,金屬材料可包含但不限於鋁(Al)、鉻(Cr)、銅(Cu)、錫(Sn)、金(Au)、鎳(Ni)、鈦(Ti)、鉑(Pt)、鈀(Pd)、銀(Ag)、鉛(Pb)、鋅(Zn)、鎘(Cd)、銻(Sb)、鈷(Co)或上述材料之合金等;透明導電材料可包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、砷化鋁鎵(AlGaAs)、氮化鎵(GaN)、磷化鎵(GaP)、砷化鎵(GaAs)、磷砷化鎵(GaAsP)、氧化銦鋅(IZO)、類鑽碳薄膜(DLC)或石墨烯。在一實施例,第一電極結構12與第二電極結構20係分別包含單層或多層結構。第一電極結構12與第二電極結構20設置於半導體疊層11的相反側,以形成垂直式的發光元件。在另一實施例中,
第一電極結構12與第二電極結構20可設置於半導體疊層11的同一側,以形成水平式的發光元件。第一電極結構12與第二電極結構20均可用以連接外部電源,並將電流均勻擴散至半導體疊層11中。於此實施例中,基板19可包含但並不限於絕緣材料,例如藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、環氧樹脂(Epoxy)、氮化鋁(AlN)。
The first electrode structure 12 and the
第一圖案化絕緣層13和第二圖案化絕緣層14可包含相同或不同的材料。在一實施例中,第一圖案化絕緣層13可包含對主動區域112發出的特定波長的光具有第一吸收率,第二圖案化絕緣層14可包含對主動區域112發出的特定波長的光具有第二吸收率,其中第一吸收率小於第二吸收率。在一實施例中,主動區域112發出的光包含紫外光波段,例如峰值波長為380nm以下的波長的光,第一圖案化絕緣層13對於波長小於約380nm的光吸收率小於第二圖案化絕緣層14對於波長小於約380nm的光吸收率。在一實施例中,第一圖案化絕緣層13對於波長小於約380nm的光吸收率小於40%,第二圖案化絕緣層14對於波長小於約380nm的光吸收率大於40%。在一實施例中,第一圖案化絕緣層13的折射率小於第二圖案化絕緣層14的折射率。第一圖案化絕緣層13的材料可包含對光低吸收率的材料,例如二氧化矽(SiO2)、或五氧化二鈮(Nb2O5)等。第二圖案化絕緣層14可包含對製程容忍性高的材料,例如耐酸蝕的材料,例如二氧化鈦(TiO2)、或五氧化二鈮(Nb2O5)等。以上內容僅為本申請案之實施例,並不 以此為限。第一圖案化絕緣層13的材料選擇可根據主動區域112發出的光的波長進行選擇調整。 The first patterned insulating layer 13 and the second patterned insulating layer 14 may include the same or different materials. In one embodiment, the first patterned insulating layer 13 may include a first absorptivity for light of a specific wavelength emitted by the active region 112, and the second patterned insulating layer 14 may include a second absorptivity for light of a specific wavelength emitted by the active region 112, wherein the first absorptivity is less than the second absorptivity. In one embodiment, the light emitted by the active region 112 includes an ultraviolet light band, such as light with a peak wavelength of less than 380 nm, and the absorptivity of the first patterned insulating layer 13 for light with a wavelength less than about 380 nm is less than the absorptivity of the second patterned insulating layer 14 for light with a wavelength less than about 380 nm. In one embodiment, the first patterned insulating layer 13 has an absorption rate of less than 40% for light with a wavelength less than about 380 nm, and the second patterned insulating layer 14 has an absorption rate of more than 40% for light with a wavelength less than about 380 nm. In one embodiment, the refractive index of the first patterned insulating layer 13 is less than the refractive index of the second patterned insulating layer 14. The material of the first patterned insulating layer 13 may include a material with low light absorption rate, such as silicon dioxide (SiO 2 ) or niobium pentoxide (Nb 2 O 5 ). The second patterned insulating layer 14 may include a material with high process tolerance, such as a material resistant to acid corrosion, such as titanium dioxide (TiO 2 ) or niobium pentoxide (Nb 2 O 5 ). The above contents are merely examples of the present application and are not limited thereto. The material selection of the first patterned insulating layer 13 can be selected and adjusted according to the wavelength of the light emitted by the active region 112.
圖案化反射層15可包含金屬材料,例如銀(Ag)、金(Au)、鋁(Al)、鈦(Ti)、鉻(Cr)、銅(Cu)、鎳(Ni)、鉑(Pt)、釕(Ru)、鎢(W)、銠(Rh)或上述材料之合金或疊層。。在一實施例中,圖案化反射層15可包含多層結構(未繪示),例如,圖案化反射層15可包含堆疊的第一反射金屬層、第二反射金屬層與第三反射金屬層之多層結構,第一反射金屬層、第二反射金屬層與第三反射金屬層可沿著負Z方向依序堆疊,第一反射金屬層可包含銀(Ag),第二反射金屬層可包含鈦鎢(TiW),第三反射金屬層可包含鉑(Pt)。圖案化反射層15可和第二型半導體層111形成歐姆接觸。 The patterned reflective layer 15 may include a metal material, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), tungsten (W), rhodium (Rh), or alloys or stacked layers thereof. In one embodiment, the patterned reflective layer 15 may include a multi-layer structure (not shown). For example, the patterned reflective layer 15 may include a multi-layer structure of a stacked first reflective metal layer, a second reflective metal layer, and a third reflective metal layer. The first reflective metal layer, the second reflective metal layer, and the third reflective metal layer may be stacked in sequence along the negative Z direction. The first reflective metal layer may include silver (Ag), the second reflective metal layer may include titanium tungsten (TiW), and the third reflective metal layer may include platinum (Pt). The patterned reflective layer 15 may form an ohmic contact with the second type semiconductor layer 111.
反射阻障層16可包含金屬材料,例如鋁(Al)、鉻(Cr)、鉑(Pt)、鈦(Ti)、鎢(W)、鋅(Zn)、銠(Rh)或上述材料之合金或疊層。在一實施例中,反射阻障層16可包含多層結構(未繪示),例如,反射阻障層16可包含堆疊的第一阻障金屬層、第二阻障金屬層與第三阻障金屬層之多層結構,第一阻障金屬層、第二阻障金屬層與第三阻障金屬層可沿著負Z方向依序堆疊,第一阻障金屬層可包含鋁(Al),第二阻障金屬層可包含鈦鎢(TiW),第三阻障金屬層可包含鉑(Pt)。在一實施例中,反射阻障層16與第一圖案化絕緣層13接觸的部分包含高反射率的鋁(Al)、鉑(Pt)或銠(Rh)。 The reflection barrier layer 16 may include a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), rhodium (Rh), or alloys or stacked layers thereof. In one embodiment, the reflection barrier layer 16 may include a multi-layer structure (not shown). For example, the reflection barrier layer 16 may include a multi-layer structure of a stacked first barrier metal layer, a second barrier metal layer, and a third barrier metal layer. The first barrier metal layer, the second barrier metal layer, and the third barrier metal layer may be stacked in sequence along the negative Z direction. The first barrier metal layer may include aluminum (Al), the second barrier metal layer may include titanium tungsten (TiW), and the third barrier metal layer may include platinum (Pt). In one embodiment, the portion of the reflection barrier layer 16 that contacts the first patterned insulating layer 13 includes aluminum (Al), platinum (Pt), or rhodium (Rh) with high reflectivity.
發光元件1還可包含設置於反射阻障層16和基板19之間的阻障層17與接合層18。阻障層17與接合層18可沿著負Z方向依序設置於反射阻障層16上。發光元件1還可包含保護層21。保護層21可設置於第一型半導體層110之第一表面110s上且覆蓋部分的第一型半導體層110之第一表面110s,並延伸覆蓋半導體疊層11的側表面。保護層21更可覆蓋第二圖案化絕緣層14。第一電極結構12可穿過保護層21而接觸半導體疊層11之第一型半導體層110。於一實施例,第一電極結構12位於保護層21上且覆蓋保護層21之一部分。於一實施例,第一電極結構12不覆蓋保護層21。於一實施例,保護層21可順應覆蓋第一型半導體層110的粗糙表面,故保護層21之上表面可包含凹凸圖案。阻障層17可用以避免接合層18之材料於製程中擴散而至反射阻障層16及/或圖案化反射層15,反應生成化合物或形成合金而影響圖案化反射層15及/或反射阻障層16之反射率及導電特性。接合層18可用以接合基板19與半導體疊層11及形成於其上的上述層疊。
The light-emitting
阻障層17可包含金屬材料,例如鉻(Cr)、鉑(Pt)、鈦(Ti)、鎢(W)、鋅(Zn)或上述材料之合金或疊層。於一實施例中,當阻障層17為金屬疊層時,阻障層17係包含由兩層或兩層以上的金屬交替堆疊而形成,例如Cr/Pt、Cr/Ti、Cr/TiW、Cr/W、Cr/Zn、Ti/Pt、Ti/W、Ti/TiW、Ti/Zn、TiW/Pt、Pt/W、Pt/Zn、TiW/W、TiW/Zn、或W/Zn等。在發光元件1為垂直式發光元
件時,接合層18可包含透明導電材料、金屬材料;透明導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)、石墨烯或上述材料之組合;金屬材料包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)或上述材料之合金或疊層等;在發光元件1為水平式的發光元件時,接合層18可包含非導電材料,例如氧化矽(SiO2)、苯並環丁烯(benzocyclobutene,BCB)、氮化矽(SiNx)、接合膠(如環氧樹脂、UV固化膠等)等或前述之組合。保護層21可包含絕緣材料;絕緣材料包含但不限於氧化矽(SiO2)、氮化矽(SiNx或Si3N4)或上述材料之組合。
The barrier layer 17 may include a metal material, such as chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or an alloy or a stack of the above materials. In one embodiment, when the barrier layer 17 is a metal stack, the barrier layer 17 includes two or more layers of metal alternately stacked, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, TiW/Pt, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn. When the light-emitting
第一圖案化絕緣層13具有Z方向上的厚度T1,第二圖案化絕緣層14具有Z方向上的厚度T2,圖案化反射層15具有Z方向上的厚度T3。第二圖案化絕緣層14的厚度T2可小於第一圖案化絕緣層13的厚度T1。圖案化反射層15的厚度T3可小於或等於第一圖案化絕緣層13的厚度T1。如第2圖所示,圖案化反射層15的厚度T3可小於或等於第一圖案化絕緣層13的厚度T1,反射阻障層16可同時接觸第一圖案化絕緣層13與圖案化反射層15,藉此可降低單一材料對介面所產生附著不良之問題。在一實施例中,圖案化反射層15未完全覆蓋第一圖案化絕緣 層13的側壁與下表面(此處所述之下表面係指面對基板19的表面),第一圖案化絕緣層13可同時接觸圖案化反射層15與反射阻障層16,藉由反射阻障層16分別與圖案化反射層15與第一圖案化絕緣層13之間良好的附著力,藉此可補強圖案化反射層15與第一圖案化絕緣層13的附著力,以解決圖案化反射層15與第一圖案化絕緣層13附著不良之問題。在一實施例中,第一電極結構12的橫向尺寸(例如是X方向的寬度)可小於第一圖案化絕緣層13的橫向尺寸,可避免影響半導體疊層11發出的光。 The first patterned insulating layer 13 has a thickness T1 in the Z direction, the second patterned insulating layer 14 has a thickness T2 in the Z direction, and the patterned reflective layer 15 has a thickness T3 in the Z direction. The thickness T2 of the second patterned insulating layer 14 may be less than the thickness T1 of the first patterned insulating layer 13. The thickness T3 of the patterned reflective layer 15 may be less than or equal to the thickness T1 of the first patterned insulating layer 13. As shown in FIG. 2 , the thickness T3 of the patterned reflective layer 15 may be less than or equal to the thickness T1 of the first patterned insulating layer 13 , and the reflection barrier layer 16 may contact the first patterned insulating layer 13 and the patterned reflective layer 15 at the same time, thereby reducing the problem of poor adhesion of a single material to the interface. In one embodiment, the patterned reflective layer 15 does not completely cover the sidewall and the lower surface (the lower surface referred to herein refers to the surface facing the substrate 19) of the first patterned insulating layer 13, and the first patterned insulating layer 13 can contact the patterned reflective layer 15 and the reflection barrier layer 16 at the same time. The reflection barrier layer 16 has good adhesion to the patterned reflective layer 15 and the first patterned insulating layer 13, respectively, thereby enhancing the adhesion between the patterned reflective layer 15 and the first patterned insulating layer 13, so as to solve the problem of poor adhesion between the patterned reflective layer 15 and the first patterned insulating layer 13. In one embodiment, the lateral dimension (e.g., the width in the X direction) of the first electrode structure 12 may be smaller than the lateral dimension of the first patterned insulating layer 13, so as to avoid affecting the light emitted by the semiconductor stack 11.
請參照第3圖。第3圖係繪示根據本申請案一實施例之反射結構與一比較例之反射結構的反射率模擬曲線圖,分別以不同波長及兩種入射角度(0度、45度)的入射光進行模擬。實施例之反射結構包含如前列舉之對光低吸收率的材料膜層,例如為二氧化矽搭配高反射的金屬材料膜層,例如為鋁。比較例之反射結構包含銀膜層以及對光高吸收率的二氧化鈦膜層。由第3圖可知,比較例之反射結構對於波長介於約380nm至約600nm的光之反射率大於對於波長介於約200nm至約380nm的光之反射率,而且在波長介於約200nm至約380nm的區段反射率急遽下降(例如,對於波長小於約350nm的光之反射率均低於60%),也就是說,使用比較例之反射結構的發光元件對於波長小於約380nm的光,亮度表現較差。相對於此,實施例之反射結構對於波長介於約200nm至約380nm的光之反射率、以及波長介於約380nm至約600nm的光之反射率均大於80%,表示在 波長介於約200nm至約600nm的區段均具有良好的反射率,因此使用實施例之反射結構的發光元件對於波長小於約380nm的光,亮度表現仍佳,具有相較於比較例更廣泛的發光波段應用。例如,根據一實施例,發光元件可發出波長介於約200nm至約600nm之間的光。例如,根據一實施例之發光元件可發出波長介於約360nm至約550nm之間的光。 Please refer to FIG. 3. FIG. 3 shows a reflectivity simulation curve of a reflective structure according to an embodiment of the present application and a reflective structure according to a comparative example, respectively, with incident light of different wavelengths and two incident angles (0 degrees and 45 degrees) for simulation. The reflective structure of the embodiment includes a material film layer with low light absorption rate as listed above, such as silicon dioxide and a metal material film layer with high reflection rate, such as aluminum. The reflective structure of the comparative example includes a silver film layer and a titanium dioxide film layer with high light absorption rate. As can be seen from Figure 3, the reflectivity of the reflective structure of the comparative example for light with a wavelength between about 380nm and about 600nm is greater than the reflectivity for light with a wavelength between about 200nm and about 380nm, and the reflectivity drops sharply in the wavelength range between about 200nm and about 380nm (for example, the reflectivity for light with a wavelength less than about 350nm is less than 60%). In other words, the light-emitting element using the reflective structure of the comparative example has poor brightness performance for light with a wavelength less than about 380nm. In contrast, the reflective structure of the embodiment has a reflectivity greater than 80% for light with a wavelength between about 200nm and about 380nm, and a reflectivity greater than 80% for light with a wavelength between about 380nm and about 600nm, indicating that the reflective structure has good reflectivity in the wavelength range between about 200nm and about 600nm. Therefore, the light-emitting element using the reflective structure of the embodiment still has good brightness performance for light with a wavelength less than about 380nm, and has a wider range of light-emitting wavelength band applications than the comparative example. For example, according to one embodiment, the light-emitting element can emit light with a wavelength between about 200nm and about 600nm. For example, according to one embodiment, the light-emitting element can emit light with a wavelength between about 360nm and about 550nm.
以下係示例性描述根據本申請案之發光元件1的製造過程,但不以此為限。
The following is an exemplary description of the manufacturing process of the light-emitting
半導體疊層11可成長於成長基板晶圓(圖未示)上,例如是透過有機金屬化學氣相沉積法(metal-organic chemical vapor deposition;MOCVD)、分子束磊晶法(molecular beam epitaxy;MBE)、氫化物氣相磊晶法(hydride vapor phase epitaxy;HVPE)或離子鍍,例如濺鍍或蒸鍍等方法以在成長基板晶圓上依序成長第一型半導體層110、主動區域112與第二型半導體層111。接著,於第二型半導體層111的第二表面111s上形成第一絕緣材料層13m與第二圖案化絕緣層14(如第4圖所示),在此步驟中,第一絕緣材料層13m與第二圖案化絕緣層14覆蓋第二表面111s,第二圖案化絕緣層14圍繞第一絕緣材料層13m,且第一絕緣材料層13m尚未被圖案化。在此步驟中,第一絕緣材料層13m可用來做為硬遮罩,第二圖案化絕緣層14可透過掀離製程(lift-off)來形成。在一實施例中,第一絕緣材料層13m與第二圖案化絕緣層14在同一黃光製程中形成而不需要重新對位,有 助於簡化製程並避免圖案偏移。如此可使第二圖案化絕緣層14與第一絕緣材料層13m相連接,。 The semiconductor stack 11 can be grown on a growth substrate wafer (not shown), for example, by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or ion plating, such as sputtering or evaporation, to sequentially grow a first type semiconductor layer 110, an active region 112 and a second type semiconductor layer 111 on the growth substrate wafer. Next, a first insulating material layer 13m and a second patterned insulating layer 14 are formed on the second surface 111s of the second type semiconductor layer 111 (as shown in FIG. 4 ). In this step, the first insulating material layer 13m and the second patterned insulating layer 14 cover the second surface 111s, the second patterned insulating layer 14 surrounds the first insulating material layer 13m, and the first insulating material layer 13m has not been patterned. In this step, the first insulating material layer 13m can be used as a hard mask, and the second patterned insulating layer 14 can be formed by a lift-off process. In one embodiment, the first insulating material layer 13m and the second patterned insulating layer 14 are formed in the same yellow light process without the need for re-alignment, which helps to simplify the process and avoid pattern deviation. In this way, the second patterned insulating layer 14 can be connected to the first insulating material layer 13m.
接著,如第5圖所示,對第一絕緣材料層13m進行圖案化,例如是透過溼式蝕刻或乾式蝕刻製程來移除部分的第一絕緣材料層13m,以形成第一圖案化絕緣層13,並使部分的第二表面111s暴露。第一圖案化絕緣層13包含封閉環形的外圍部131與被外圍部131圍繞之內部。於一實施例,第一圖案化絕緣層13的內部可由複數個長條部132構成。暴露的第二表面111s介於外圍部131與複數個長條部132之間。接著,如第6圖所示,可透過自對準製程(self-align)使圖案化反射層15形成於暴露的第二表面111s上,而使圖案化反射層15和第二型半導體層111形成電性連接。於一實施例中,圖案化反射層15直接接觸第二型半導體層111,以形成一歐姆接觸。於一實施例中,圖案化反射層15與第二型半導體層111之間更包含一透明導電層(圖未示),透明導電層直接接觸第二型半導體層111,以形成一歐姆接觸。第二圖案化絕緣層14可包含耐酸蝕,因此可在後續製程中用做蝕刻停止層。接著,在第一圖案化絕緣層13、第二圖案化絕緣層14與圖案化反射層15上依序形成反射阻障層16和阻障層17,例如是透過沉積、濺鍍或蒸鍍等方法來形成。 Next, as shown in FIG. 5 , the first insulating material layer 13m is patterned, for example, by removing a portion of the first insulating material layer 13m through a wet etching or dry etching process to form a first patterned insulating layer 13, and exposing a portion of the second surface 111s. The first patterned insulating layer 13 includes a closed annular outer portion 131 and an inner portion surrounded by the outer portion 131. In one embodiment, the inner portion of the first patterned insulating layer 13 may be composed of a plurality of long strip portions 132. The exposed second surface 111s is between the outer portion 131 and the plurality of long strip portions 132. Next, as shown in FIG. 6 , a patterned reflective layer 15 can be formed on the exposed second surface 111s by a self-alignment process, so that the patterned reflective layer 15 and the second type semiconductor layer 111 are electrically connected. In one embodiment, the patterned reflective layer 15 directly contacts the second type semiconductor layer 111 to form an ohmic contact. In one embodiment, a transparent conductive layer (not shown) is further included between the patterned reflective layer 15 and the second type semiconductor layer 111, and the transparent conductive layer directly contacts the second type semiconductor layer 111 to form an ohmic contact. The second patterned insulating layer 14 can include acid-resistant corrosion resistance, so it can be used as an etch stop layer in subsequent processes. Next, a reflection barrier layer 16 and a barrier layer 17 are sequentially formed on the first patterned insulating layer 13, the second patterned insulating layer 14 and the patterned reflective layer 15, for example, by deposition, sputtering or evaporation.
在阻障層17上形成接合層18,以藉由接合層18和基板19接合。在一實施例中,接合層18可形成於基板19上,再使基板19透過接合層18以和阻障層17接合。在另一實施例
中,接合層18也可部分形成於阻障層17上、部分形成於基板19上,再使此兩部分的接合層18相互接合以使基板19藉由接合層18和阻障層17接合。在一實施例中,阻障層17、接合層18和基板19之接合例如是透過熱壓製程。接著,可透過沉積、濺鍍或蒸鍍等方法,於基板19上形成第二電極結構20。
A bonding layer 18 is formed on the barrier layer 17 to bond with the substrate 19 through the bonding layer 18. In one embodiment, the bonding layer 18 can be formed on the substrate 19, and then the substrate 19 is bonded to the barrier layer 17 through the bonding layer 18. In another embodiment, the bonding layer 18 can also be partially formed on the barrier layer 17 and partially formed on the substrate 19, and then the two parts of the bonding layer 18 are bonded to each other so that the substrate 19 is bonded to the barrier layer 17 through the bonding layer 18. In one embodiment, the barrier layer 17, the bonding layer 18 and the substrate 19 are bonded, for example, through a hot pressing process. Then, the
可透過雷射移除半導體疊層11上的成長基板晶圓。在一實施例中,半導體疊層11包含一未摻雜的半導體底層(圖未示),移除成長基板晶圓後暴露出半導體疊層11的半導體底層。在一實施例中,可透過溼式蝕刻或乾式蝕刻製程移除半導體底層,且進一步移除部分第一型半導體層110以形成粗糙表面,例如是第2圖所示之第一表面110s。可透過圖案化半導體疊層11,移除部分半導體疊層11至暴露出第二圖案化絕緣層14,來形成晶片分離區域,其中晶片分離區域定義出發光元件1之周圍。圖案化半導體疊層11的方式可包含乾式蝕刻或濕式蝕刻。接著,可透過沉積、濺鍍或蒸鍍等方法,在第一表面110s及半導體疊層11的側壁上先形成保護材料層(圖未示),接著透過溼式蝕刻或乾式蝕刻製程來移除部分的保護材料層以暴露出部分的第一表面110s並形成保護層21,然後可透過沉積、濺鍍或蒸鍍等方法,使第一電極結構12形成於第一型半導體層110上。最後,沿著晶片分離區域切割基板19及其上之疊層,分割成多個獨立的發光元件1。在一實施例中,可通過施行上述方法,得到如第1-2圖所述的發光元件1。
The growth substrate wafer on the semiconductor stack 11 can be removed by laser. In one embodiment, the semiconductor stack 11 includes an undoped semiconductor bottom layer (not shown), and the semiconductor bottom layer of the semiconductor stack 11 is exposed after the growth substrate wafer is removed. In one embodiment, the semiconductor bottom layer can be removed by a wet etching or dry etching process, and a portion of the first type semiconductor layer 110 is further removed to form a rough surface, such as the first surface 110s shown in FIG. 2. The chip separation area can be formed by patterning the semiconductor stack 11, removing a portion of the semiconductor stack 11 until the second patterned insulating layer 14 is exposed, wherein the chip separation area defines the periphery of the light-emitting
第7圖及第8圖分別繪示實施例發光元件2及3的剖面示意圖。發光元件2及3之製程及結構和發光元件1類似,類似的製程及結構請參考發光元件1之說明及圖式,不再贅述,後續將針對差異處說明。請參照第7圖,發光元件2與發光元件1的差異在於,發光元件2更包含黏著層15A,發光元件2之反射層15’不同於發光元件1的圖案化反射層15。黏著層15A可設置於第二型半導體層111之第二表面111s上,且延伸設置於外圍部131之表面131s與長條部132之表面132s上,外圍部131之表面131s與長條部132之表面132s背向半導體疊層11。於一實施例中,黏著層15A可覆蓋外圍部131之表面131s與長條部132之表面132s。於另一實施例中,黏著層15A可覆蓋外圍部131之表面131s與長條部132之表面132s,更延伸覆蓋至外圍部131與長條部132之側壁。反射層15’可設置於黏著層15A與反射阻障層16之間,並覆蓋第一圖案化絕緣層13。黏著層15A可用以提升第一圖案化絕緣層13和反射層15’之間的黏著性。在一實施例中,黏著層15A可包含金屬氧化物、金屬氮化物或金屬。在一實施例中,黏著層15A可包含氧化銦錫,且氧化銦錫在Z方向上的厚度為10到300Å。在一實施例中,黏著層15A可包含氮化鈦,且氮化鈦在Z方向上的厚度為10到50Å。在一實施例中,黏著層15A可包含鉻,且鉻在Z方向上的厚度為10到50Å。
FIG. 7 and FIG. 8 are cross-sectional schematic diagrams of the light-emitting elements 2 and 3 of the embodiment, respectively. The manufacturing process and structure of the light-emitting elements 2 and 3 are similar to those of the light-emitting
請參照第8圖,發光元件3與發光元件2的差異在於,發光元件3之黏著層15A’可設置於第一圖案化絕緣層13上, 且未設置於第二型半導體層111之第二表面111s上,發光元件3之反射層15’可直接接觸第二型半導體層111之第二表面111s。在此實施例中,黏著層15A’為一圖案化黏著層,僅對應設置於第一圖案化絕緣層13上,而未設置於第二型半導體層111之第二表面111s上,因此可降低黏著層15A’對主動區域112發出光的吸收率,並提升光提取效率。 Please refer to Figure 8. The difference between the light-emitting element 3 and the light-emitting element 2 is that the adhesive layer 15A' of the light-emitting element 3 can be disposed on the first patterned insulating layer 13, and is not disposed on the second surface 111s of the second type semiconductor layer 111. The reflective layer 15' of the light-emitting element 3 can directly contact the second surface 111s of the second type semiconductor layer 111. In this embodiment, the adhesive layer 15A' is a patterned adhesive layer, which is only disposed on the first patterned insulating layer 13, and is not disposed on the second surface 111s of the second type semiconductor layer 111. Therefore, the absorption rate of the adhesive layer 15A' to the light emitted by the active area 112 can be reduced, and the light extraction efficiency can be improved.
請參照第9圖。第9圖係繪示多個實施例之發光元件與多個比較例之發光元件的功率曲線圖。多個實施例A-E具有如上述第7圖所示之結構,第一圖案化絕緣層13包含如前列舉之對光具有較低吸收率的材料,例如為二氧化矽。多個比較例A-E包含對光具有較高吸收率的二氧化鈦。實施例A、實施例C與實施例E中,第一圖案化絕緣層13在Z方向上的厚度介於700到2500Å。實施例B與實施例D中,第一圖案化絕緣層13在Z方向上的厚度介於100到700Å。比較例A-E分別對應實施例A-E而具有相同的厚度。由第9圖可知,實施例A-E之發光元件的功率均高於比較例A-E之發光元件的功率,因此採用包含對光具有較低低吸收率的材料之反射結構可有效提升發光元件的亮度,例如可使亮度提升1%至3%。此外,由第9圖可知,相較於實施例B與實施例D,實施例A、實施例C與實施例E的亮度更高,因此在一定範圍內提升第一圖案化絕緣層13在Z方向上的厚度有助於提升發光元件的亮度,例如可使亮度提升0.8%至2%。在一實施例中,第一圖案化絕緣層13在Z方向上的厚度T1可為100Å 至2500Å。在一實施例中,第一圖案化絕緣層13在Z方向上的厚度T1可為700Å至2500Å。 Please refer to Figure 9. Figure 9 is a power curve diagram of the light-emitting elements of multiple embodiments and the light-emitting elements of multiple comparative examples. Multiple embodiments A-E have the structure shown in Figure 7 above, and the first patterned insulating layer 13 includes a material with a lower light absorption rate as listed above, such as silicon dioxide. Multiple comparative examples A-E include titanium dioxide with a higher light absorption rate. In Embodiment A, Embodiment C and Embodiment E, the thickness of the first patterned insulating layer 13 in the Z direction is between 700 and 2500Å. In Embodiment B and Embodiment D, the thickness of the first patterned insulating layer 13 in the Z direction is between 100 and 700Å. Comparative Examples A-E correspond to Examples A-E respectively and have the same thickness. As shown in FIG. 9, the power of the light-emitting elements of Examples A-E is higher than that of the light-emitting elements of Comparative Examples A-E. Therefore, the use of a reflective structure comprising a material with a low light absorption rate can effectively improve the brightness of the light-emitting element, for example, the brightness can be increased by 1% to 3%. In addition, as shown in FIG. 9, compared with Examples B and D, Examples A, C and E have higher brightness. Therefore, increasing the thickness of the first patterned insulating layer 13 in the Z direction within a certain range helps to improve the brightness of the light-emitting element, for example, the brightness can be increased by 0.8% to 2%. In one embodiment, the thickness T1 of the first patterned insulating layer 13 in the Z direction can be 100Å to 2500Å. In one embodiment, the thickness T1 of the first patterned insulating layer 13 in the Z direction may be 700Å to 2500Å.
請參照第10圖。第10圖係繪示不同實施例之發光元件第一圖案化絕緣層寬度變化對應功率的曲線圖,其中實施例A與實施例B具有如上述第7圖所示之結構,第一圖案化絕緣層13包含如前列舉之對光具有較低吸收率的材料,例如為二氧化矽。實施例A與實施例B的差異在於,實施例A中的第一圖案化絕緣層13在Z方向上的厚度介於700到2500Å;實施例B中的第一圖案化絕緣層13在Z方向上的厚度介於100到700Å。由第10圖可知,實施例A及實施例B中,當第一圖案化絕緣層13在X方向上的寬度增加,對應的發光元件的電流分散及反射效率相對提升,因此發光元件的功率與亮度愈高。因此在發光元件電性可接受的一定範圍內提升第一圖案化絕緣層13在X方向上的寬度有助於提升發光元件的亮度。在一實施例中,第一圖案化絕緣層13在X方向上的寬度可為20μm至80μm。在一實施例中,第一圖案化絕緣層13在X方向上的寬度可為30μm至80μm。 Please refer to FIG. 10. FIG. 10 is a graph showing the power curves corresponding to the width variation of the first patterned insulating layer of the light-emitting element of different embodiments, wherein Embodiment A and Embodiment B have the structure shown in FIG. 7 above, and the first patterned insulating layer 13 comprises the material with a lower light absorption rate as listed above, such as silicon dioxide. The difference between Embodiment A and Embodiment B is that the thickness of the first patterned insulating layer 13 in Embodiment A in the Z direction is between 700 and 2500 Å; the thickness of the first patterned insulating layer 13 in Embodiment B in the Z direction is between 100 and 700 Å. As can be seen from Figure 10, in Embodiment A and Embodiment B, when the width of the first patterned insulating layer 13 in the X direction increases, the current dispersion and reflection efficiency of the corresponding light-emitting element are relatively improved, so the power and brightness of the light-emitting element are higher. Therefore, increasing the width of the first patterned insulating layer 13 in the X direction within a certain range of acceptable electrical properties of the light-emitting element helps to improve the brightness of the light-emitting element. In one embodiment, the width of the first patterned insulating layer 13 in the X direction can be 20μm to 80μm. In one embodiment, the width of the first patterned insulating layer 13 in the X direction can be 30μm to 80μm.
根據不同的應用,可對發光元件1、2或3進行封裝製程。請參照第11圖,係繪示根據一實施例之發光封裝體200的剖面示意圖。根據實施例的發光器件封裝200可以包含封裝牆205、封裝基板201、安裝在封裝基板201上的外部電極213和214、安裝在封裝牆205中且與外部電極213和214電連接的發光元件1、2或3以及封裝材240(其包括螢光體232以圍繞發光
元件1)。外部電極213和214彼此電性絕緣,並且通過導線230將電力提供給發光元件1、2或3。此外,外部電極213和214可以反射從發光元件1、2或3發射的光以提高出光效率,並且將從發光元件1、2或3發出的熱量排放到外部。發光封裝體200可以應用於背光單元、照明單元、顯示裝置、指示器、電燈、路燈、用於車輛的照明裝置、用於車輛的顯示裝置或智慧手錶,但是不限於此。
According to different applications, the light-emitting
第12圖係繪示根據一實施例之發光裝置300的示意圖。發光裝置300包括一燈罩301、一反射鏡302、一發光模組305、一燈座306、一散熱片307、一連接部308以及一電連接元件309。發光模組305包含一承載部303,以及複數個發光單元304位於承載部303上,其中複數個發光單元304可為前述實施例中的發光元件1、2或3或發光封裝體200。
FIG. 12 is a schematic diagram of a light-emitting
在本揭露之多個實施例中,發光元件包含對光具有較低吸收率的第一圖案化絕緣層13,提升發光元件的出光效率、發光波段、亮度與應用範圍。再藉由第一圖案化絕緣層13與高反射率的反射阻障層16形成之全方位反射結構對於波長介於約200nm至約600nm的光之反射率大於80%,如此可提升第一圖案化絕緣層13與反射阻障層16形成之全方位反射結構對於各種波長的光之反射率。此外,在本揭露之多個實施例中,第一圖案化絕緣層13可同時接觸包含不同材料之黏著層15A、反射層15’與反射阻障層16,如此可提升第一圖案化絕緣層13和其他層之間的附 著力,有效避免附著性不佳而導致的產品良率不佳、減損發光元件之耐用性等問題。 In many embodiments of the present disclosure, the light-emitting element includes a first patterned insulating layer 13 with a low light absorption rate, which improves the light extraction efficiency, light emission wavelength, brightness and application range of the light-emitting element. The reflectivity of the omnidirectional reflective structure formed by the first patterned insulating layer 13 and the high-reflectivity reflective barrier layer 16 for light with a wavelength between about 200nm and about 600nm is greater than 80%, so the reflectivity of the omnidirectional reflective structure formed by the first patterned insulating layer 13 and the reflective barrier layer 16 for light of various wavelengths can be improved. In addition, in many embodiments disclosed herein, the first patterned insulating layer 13 can simultaneously contact the adhesive layer 15A, the reflective layer 15' and the reflective barrier layer 16 comprising different materials, thereby improving the adhesion between the first patterned insulating layer 13 and other layers, effectively avoiding problems such as poor product yield and reduced durability of the light-emitting element caused by poor adhesion.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.
1:發光元件 1: Light-emitting element
11:半導體疊層 11: Semiconductor stacking
12:第一電極結構 12: First electrode structure
13:第一圖案化絕緣層 13: The first patterned insulating layer
14:第二圖案化絕緣層 14: Second patterned insulating layer
14s:絕緣表面 14s: Insulation surface
14sw,16sw:外側邊緣 14sw,16sw:outer edge
15:圖案化反射層 15: Patterned reflective layer
16:反射阻障層 16: Reflection barrier
17:阻障層 17: Barrier layer
18:接合層 18:Joint layer
19:基板 19: Substrate
20:第二電極結構 20: Second electrode structure
21:保護層 21: Protective layer
110:第一型半導體層 110: Type I semiconductor layer
110s:第一表面 110s: First surface
111:第二型半導體層 111: Type II semiconductor layer
111s:第二表面 111s: Second surface
112:主動區域 112: Active area
131:外圍部 131: Outer periphery
132:長條部 132: Long strips
151:反射區 151: Reflexology area
T1,T2,T3:厚度 T1, T2, T3: thickness
X,Y,Z:方向 X,Y,Z: Direction
Claims (22)
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| TW111116475A TWI864391B (en) | 2022-04-29 | 2022-04-29 | Light-emitting element |
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| TW111116475A TWI864391B (en) | 2022-04-29 | 2022-04-29 | Light-emitting element |
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| Publication Number | Publication Date |
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| TW202343833A TW202343833A (en) | 2023-11-01 |
| TWI864391B true TWI864391B (en) | 2024-12-01 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201608735A (en) * | 2014-08-26 | 2016-03-01 | 東芝股份有限公司 | Current limiting LED |
| TW201618328A (en) * | 2014-11-07 | 2016-05-16 | Tekcore Co Ltd | Current block layer structure of light-emitting diode |
| TW201709554A (en) * | 2015-05-22 | 2017-03-01 | 首爾偉傲世有限公司 | High efficiency light-emitting diode |
| TW202015257A (en) * | 2015-02-17 | 2020-04-16 | 新世紀光電股份有限公司 | Light-emitting diode chip |
| US20210336081A1 (en) * | 2020-04-27 | 2021-10-28 | Kaistar Lighting (Xiamen) Co., Ltd. | Semiconductor light-emitting device |
-
2022
- 2022-04-29 TW TW111116475A patent/TWI864391B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201608735A (en) * | 2014-08-26 | 2016-03-01 | 東芝股份有限公司 | Current limiting LED |
| TW201618328A (en) * | 2014-11-07 | 2016-05-16 | Tekcore Co Ltd | Current block layer structure of light-emitting diode |
| TW202015257A (en) * | 2015-02-17 | 2020-04-16 | 新世紀光電股份有限公司 | Light-emitting diode chip |
| TW201709554A (en) * | 2015-05-22 | 2017-03-01 | 首爾偉傲世有限公司 | High efficiency light-emitting diode |
| US20210336081A1 (en) * | 2020-04-27 | 2021-10-28 | Kaistar Lighting (Xiamen) Co., Ltd. | Semiconductor light-emitting device |
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|---|---|
| TW202343833A (en) | 2023-11-01 |
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