TWI870695B - Light-emitting element and method for manufacturing the same - Google Patents

Abstract

A light-emitting element is provided. The light-emitting element includes a support substrate, a semiconductor-stack structure and an electrode structure. The semiconductor-stack structure includes a first conductivity-type semiconductor layer, an active region and a second conductivity-type semiconductor layer stacked sequentially on the support substrate along a vertical direction. The second conductivity-type semiconductor layer includes a first part and a second part connected to the first part. The first part has a first rough upper surface. The second part has a second rough upper surface. The electrode structure is on the first rough upper surface of the first part of the second conductivity-type semiconductor layer and electrically connected to the second conductivity-type semiconductor layer. A first thickness of the first part along the vertical direction is greater than a second thickness of the second part along the vertical direction. A roughness (Ra) of the first rough upper surface is approximately equal to a roughness (Ra) of the second rough upper surface.

Description

Light emitting element and method for manufacturing the same

This application relates to a light-emitting element and a method for manufacturing the same, and in particular to a semiconductor light-emitting element and a method for manufacturing the same.

Semiconductor light-emitting elements, such as light-emitting diodes, have been widely used in various lighting fields. However, semiconductor light-emitting elements still face problems such as low light output efficiency and brightness loss. Therefore, how to propose a new semiconductor light-emitting element that can effectively improve the light output efficiency of semiconductor light-emitting elements is one of the key points of research and development personnel.

According to one embodiment of the present application, the light-emitting element includes a supporting substrate, a semiconductor stack and an electrode structure. The semiconductor stack includes a first type semiconductor layer, an active region and a second type semiconductor layer stacked in sequence on the supporting substrate along a vertical direction. The second type semiconductor layer includes a first region and a second region connected to the first region. The first region has a first rough upper surface. The second region has a second rough upper surface. The electrode structure is formed on the first rough upper surface of the first region of the second type semiconductor layer and is electrically connected to the second type semiconductor layer. The first thickness of the first region in the vertical direction is greater than the second thickness of the second region in the vertical direction. The roughness (Ra) of the first rough upper surface and the second rough upper surface are substantially equal.

According to one embodiment of the present application, a method for manufacturing a light-emitting element includes the following steps. A semiconductor stack is provided, the semiconductor stack including a first type semiconductor layer, a second type semiconductor layer, and an active region between the first type semiconductor layer and the second type semiconductor layer. The second type semiconductor layer is subjected to a first etching process to form a rough region, wherein the rough region includes a first region and a second preparation region connected to the first region. The second preparation region is subjected to a second etching process to remove a portion located in the second preparation region to form a second region surrounded by the first region, wherein a first thickness of the first region in a vertical direction is greater than a second thickness of the second region in a vertical direction, the first region has a first rough upper surface, the second region has a second rough upper surface, and the roughness (Ra) of the first rough upper surface and the second rough upper surface are substantially equal. An electrode structure is formed on the first rough upper surface of the first region of the second type semiconductor layer.

In order to better understand the above and other aspects of this application, the following is a specific example, and the attached drawings are explained in detail as follows:

The ordinal numbers used in this manual, such as "first", "second", "third", etc., are used to modify the components. They do not imply or represent any previous ordinal numbers of the components, nor do they represent the order of one component and another component, or the order of the manufacturing method. These ordinal numbers are used only to make components with the same name clearly distinguishable. In addition, the drawings are simplified to facilitate the clear description of the contents of the embodiments, and the size ratios in the drawings are not drawn in proportion to the actual products. The same or similar component symbols are used to represent the same or similar components.

Please refer to Figures 1-2 at the same time. Figure 1 is a schematic top view of a light-emitting element 1 according to an embodiment, and Figure 2 is a schematic cross-sectional view of the light-emitting element 1 along the section line A-A' shown in Figure 1. In order to facilitate understanding of the relative positional relationship between the second-type semiconductor layer 110 and the electrode structure 12 in the semiconductor stack 11, the schematic top view of the light-emitting element 1 shown in Figure 1 only shows the second-type semiconductor layer 110, the electrode structure 12 and the patterned insulating layer 14, and omits the protective layer 13. Referring to Figure 2, the light-emitting element 1 may include a lower electrode structure 20, a supporting substrate 19, a semiconductor stack 11, and an electrode structure 12 on the semiconductor stack 11. The lower electrode structure 20 and the semiconductor stack 11 are respectively disposed on opposite sides of the supporting substrate 19. The supporting substrate 19 and the electrode structure 12 are respectively disposed on opposite sides of the semiconductor stack 11. The semiconductor stack 11 may include a first type semiconductor layer 111, a second type semiconductor layer 110, and an active region 112 formed between the first type semiconductor layer 111 and the second type semiconductor layer 110. The first type semiconductor layer 111, the active region 112, and the second type semiconductor layer 110 may be stacked in sequence on the supporting substrate 19 along a vertical direction (e.g., a positive Z direction). The electrode structure 12 is electrically connected to the second type semiconductor layer 110.

Referring to FIG. 1-2 , the second type semiconductor layer 110 may include a first region 120 and a second region 130. In one embodiment, the first region 120 of the second type semiconductor layer 110 may surround the second region 130 in a closed manner, and the first region 120 may be a closed ring, such as a square ring or a circular ring; the first region 120 may be formed near each side of the second region 130. In another embodiment, the first region 120 of the second type semiconductor layer 110 may surround the second region 130 in an open manner, and the first region 120 may be an open ring, such as a U-shape or a C-shape; the first region 120 may be formed near part of the side of the second region 130, for example, the first region 120 may be formed near three sides of the second region 130. In another embodiment, the first zone 120 is connected to the second zone 130.

The first region 120 has a thickness T1 in a vertical direction (e.g., Z direction), and the second region 130 has a thickness T2 in a vertical direction (e.g., Z direction). The thickness T1 is not equal to the thickness T2. In one embodiment, the thickness T1 is greater than the thickness T2. In one embodiment, the difference between the thickness T1 and the thickness T2 may be between 1 and 1.5 micrometers (μm). In one embodiment, the area of the first region 120 on a horizontal plane (e.g., XY plane) perpendicular to the vertical direction may be smaller than the area of the second region 130 on the XY plane. In one embodiment, the ratio of the area of the first region 120 on the XY plane to the area of the second region 130 on the XY plane is not less than 0.3 and not more than 0.9. In one embodiment, the ratio of the area of the first region 120 on the XY plane to the area of the second region 130 on the XY plane is not less than 0.4 and not more than 0.8.

The first region 120 of the second type semiconductor layer 110 has a first rough upper surface 120s. The second region 130 has a second rough upper surface 130s. The first rough upper surface 120s of the first region 120 and the second rough upper surface 130s of the second region 130 are, for example, light emitting surfaces of the light emitting element 1. In one embodiment, the first rough upper surface 120s and the second rough upper surface 130s have a plurality of convex portions and concave portions arranged alternately, and the aforementioned thicknesses T1 and T2 are respectively the distances from the lower surface of the second type semiconductor layer 110 close to the active region 112 to the apex of one of the plurality of convex portions of the first region 120 and the apex of one of the plurality of convex portions of the second region 130. In one embodiment, the roughness (Ra) of the first rough upper surface 120s and the second rough upper surface 130s are substantially equal. In one embodiment, the difference in roughness (Ra) between the first rough upper surface 120s and the second rough upper surface 130s is not greater than 0.05 micrometers (μm). In one embodiment, the ratio of the difference in roughness (Ra) between the first rough upper surface 120s and the second rough upper surface 130s to the roughness (Ra) of the first rough upper surface 120s and the second rough upper surface 130s is not greater than 0.2. In one embodiment, the rough patterns of the first rough upper surface 120s and the second rough upper surface 130s may be pyramids or cones. The sizes of the rough patterns may be the same or different. The distribution of the rough patterns may be regular or irregular. The first region 120 of the second type semiconductor layer 110 has a side wall 120w. The side wall 120w may connect the first rough upper surface 120s and the second rough upper surface 130s. In one embodiment, the sidewall 120w of the first region 120 has a rough surface, and the roughness (Ra) of the rough surface is less than the roughness (Ra) of the first rough upper surface 120s of the first region 120 and/or less than the roughness (Ra) of the second rough upper surface 130s of the second region 130. The sidewall 120w of the first region 120 has a rough surface to improve the light extraction efficiency. The electrode structure 12 can be formed on the first rough upper surface 120s of the first region 120 of the second type semiconductor layer 110. In one embodiment, the rough pattern of the rough surface of the sidewall 120w can be a pyramid. The size of the rough pattern can be the same or different. The distribution of the rough pattern can be regularly or irregularly arranged. In one embodiment, the rough pattern of the rough surface of the side wall 120w may be a pyramid having multiple faces, and at least one face of the pyramid may include a non-polar face of a hexagonal crystal structure. In addition, the cross section of the pyramid may be a triangle.

Specifically, the first region 120 of the second type semiconductor layer 110 may include one or more first sub-regions 120a and a peripheral region 120b. In one embodiment, the peripheral region 120b may surround the one or more first sub-regions 120a in a closed manner, and the peripheral region 120b may be a closed ring, such as a square ring or a circular ring. In another embodiment, the peripheral region 120b may surround the one or more first sub-regions 120a in an open manner, and the peripheral region 120b may be an open ring, such as a U-shape or a C-shape. One or more first sub-regions 120a may be arranged at intervals along the horizontal direction (such as the X direction). The second region 130 of the second type semiconductor layer 110 may include a plurality of second sub-regions 130a. The plurality of second sub-regions 130a may be arranged at intervals along the horizontal direction (e.g., the X direction). In one embodiment, the plurality of second sub-regions 130a and one or more first sub-regions 120a may be arranged alternately along the horizontal direction (e.g., the X direction). The electrode structure 12 may include one or more first conductive portions 12a and second conductive portions 12b. In one embodiment, the second conductive portion 12b may surround the one or more first conductive portions 12a in a closed manner, and the second conductive portion 12b may be a closed ring, such as a square ring or a circular ring. In another embodiment, the second conductive portion 12b may surround the one or more first conductive portions 12a in an open manner, and the second conductive portion 12b may be an open ring, such as a U-shape or a C-shape. In one embodiment, one or more first conductive portions 12a of the electrode structure 12 are respectively disposed on one or more first sub-regions 120a of the first region 120 of the second type semiconductor layer 110.

As shown in FIG. 1 , one or all of the one or more first sub-regions 120a of the first region 120 of the second-type semiconductor layer 110 has a width W1 in the horizontal direction (e.g., X direction); one or all of the multiple second sub-regions 130a of the second region 130 of the second-type semiconductor layer 110 has a width W2 in the horizontal direction (e.g., X direction); one or all of the one or more first conductive portions 12a of the electrode structure 12 has a width W3 in the horizontal direction (e.g., X direction). In one embodiment, the width W2 may be greater than the width W1. In one embodiment, the ratio of the width W1 to the width W2 is not less than 0.1 and not more than 0.5. In one embodiment, the ratio of the width W1 to the width W2 is not less than 0.2 and not more than 0.4. In one embodiment, the width W1 may be greater than the width W3. In one embodiment, the difference between the width W1 and the width W3 is not less than 20 micrometers (μm). In one embodiment, the difference between the width W1 and the width W3 is not greater than 40 micrometers (μm).

In one embodiment, the support substrate 19 includes a conductive material or a semiconductor material, and the support substrate 19 can be light-transmissive or light-opaque. The conductive light-transmissive material includes but is not limited to a transparent conductive oxide (TCO), such as zinc oxide (ZnO); the conductive light-opaque material includes but is not limited to a metal material, such as aluminum (Al), copper (Cu), molybdenum (Mo), germanium (Ge) or tungsten (W) or an alloy or a stack of the above materials; the semiconductor material includes silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe), zinc selenide (ZnSe) or indium phosphide (InP). In one embodiment, the supporting substrate 19 may include insulating materials, such as sapphire, diamond, glass, quartz, acrylic, and epoxy.

x1

1，0

x2

1。發光元件1例如為一發光二極體，其所發出之光線的波 長取決於主動區域112之材料組成。具體來說，主動區域112之材料可包含AlInGaAs系列、InGaAsP系列、AlGaInP系列、InGaN系列或AlGaN系列。當主動區域112之材料為AlInGaP系列材料時，可發出波長介於610nm及650nm之間的紅光、或波長介於530nm及570nm之間的綠光。當主動區域112之材料為InGaN系列材料時，可發出波長介於400nm及490nm之間的藍光、波長介於490nm及530nm之間的青色光(Cyan)、或波長介於530nm及570nm之間的綠光。當主動區域112之材料為AlGaN系列或AlInGaN系列材料時，可發出波長介於400nm及250nm之間的紫外光。在一實施例中，主動區域112可包含單異質結構(single heterostructure)、雙異質結構(double heterostructure)或多重量子井結構(multiple quantum wells)。在一實施例中，主動區域112包含多重量子井結構，主動區域112包含在Z方向上一次或多次交替堆疊的一或複數個量子井層(quantum well layer)與一或複數個障蔽層(barrier layer)，且障蔽層的能障大於量子井層以限制載子分布，此外，複數個量子井層彼此之間可以具有相同或不同的材料組成及能障，本申請案對此不加以限制。在一實施例中，主動區域112之材料可以是i型、p型或n型半導體。 In one embodiment, the semiconductor stack 11 is a light-emitting stack, and the first type semiconductor layer 111 and the second type semiconductor layer 110 can be used as confinement layers, carrier supply layers, or contact layers. The active region 112 can be used as a light-emitting structure. The first type semiconductor layer 111 and the second type semiconductor layer 110 can include semiconductor materials of different doping types to supply carriers, for example, the first type semiconductor layer 111 includes an n-type semiconductor layer, and the second type semiconductor layer 110 includes a p-type semiconductor layer to provide electrons and holes, respectively; or the first type semiconductor layer 111 includes a p-type semiconductor layer, and the second type semiconductor layer 110 includes an n-type semiconductor layer to provide holes and electrons, respectively. The first type semiconductor layer 111, the active region 112 and the second type semiconductor layer 110 may include the same series of III-V compound semiconductor materials, such as AlInGaAs series, AlGaInP series, InGaAsP series or AlInGaN series. Among them, the AlInGaAs series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 As, the AlInGaP series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 P, the AlInGaN series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 N, and the InGaAsP series can be expressed as In _x1 Ga _1-x1 As _x2 P _1-x2 , where 0

x1

1,0

x2

1. The light-emitting element 1 is, for example, a light-emitting diode, and the wavelength of the light emitted by the light-emitting element 1 depends on the material composition of the active region 112. Specifically, the material of the active region 112 may include AlInGaAs series, InGaAsP series, AlGaInP series, InGaN series or AlGaN series. When the material of the active region 112 is AlInGaP series material, red light with a wavelength between 610nm and 650nm, or green light with a wavelength between 530nm and 570nm can be emitted. When the material of the active region 112 is InGaN series material, blue light with a wavelength between 400nm and 490nm, cyan light with a wavelength between 490nm and 530nm, or green light with a wavelength between 530nm and 570nm can be emitted. When the material of the active region 112 is AlGaN series or AlInGaN series material, ultraviolet light with a wavelength between 400nm and 250nm can be emitted. In one embodiment, the active region 112 may include a single heterostructure, a double heterostructure or a multiple quantum well structure. In one embodiment, the active region 112 includes a multiple quantum well structure, and the active region 112 includes one or more quantum well layers and one or more barrier layers stacked alternately in the Z direction once or multiple times, and the energy barrier of the barrier layer is greater than that of the quantum well layer to limit carrier distribution. In addition, the multiple quantum well layers may have the same or different material composition and energy barrier, and the present application is not limited thereto. In one embodiment, the material of the active region 112 can be i-type, p-type or n-type semiconductor.

The electrode structure 12 and the lower electrode structure 20 may include conductive materials. The electrode structure 12 and the lower electrode structure 20 may include the same or different materials. The electrode structure 12 and the lower electrode structure 20 may include metal materials or transparent conductive materials; for example, the metal material may include but is not limited to aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), cobalt (Co), rhodium (Rh) or a combination of the above materials. Gold, etc.; the transparent conductive material may include but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), titanium nitride (TiN), diamond-like carbon film (DLC) or graphene. In one embodiment, the electrode structure 12 and the lower electrode structure 20 include a single layer or a multi-layer structure respectively. The electrode structure 12 and the lower electrode structure 20 are arranged on opposite sides of the semiconductor stack 11 to form a vertical light-emitting element. In another embodiment, the electrode structure 12 and the lower electrode structure 20 can be disposed on the same side of the semiconductor stack 11 to form a horizontal light-emitting element. Both the electrode structure 12 and the lower electrode structure 20 can be used to connect to an external power source and evenly diffuse the current into the semiconductor stack 11.

The light-emitting element 1 may further include a patterned insulating layer 14, a reflective layer 15, and a first barrier layer 16. The patterned insulating layer 14 and the reflective layer 15 may be disposed on the surface 111s of the first type semiconductor layer 111. In one embodiment, the patterned insulating layer 14 may directly contact the first type semiconductor layer 111. In one embodiment, the patterned insulating layer 14 may be connected to the reflective layer 15. In one embodiment, the patterned insulating layer 14 may be disposed corresponding to the position of the electrode structure 12. For example, the electrode structure 12 may overlap the patterned insulating layer 14 in the Z direction. The area of the electrode structure 12 on the XY plane may be smaller than the area of the patterned insulating layer 14 on the XY plane to prevent the excessive area of the electrode structure 12 from shielding the light emitted from the active region 112 . In addition, when the first semiconductor layer 111 is a p-type semiconductor layer and the second semiconductor layer 110 is an n-type semiconductor layer, the lateral diffusion speed of electrons in the second semiconductor layer 110 is greater than the lateral diffusion speed of holes in the first semiconductor layer 111. Therefore, the current (holes) injected from the lower electrode structure 20 can be matched with the electrons with faster lateral diffusion through the larger patterned insulating layer 14, and can avoid the light shielding area of the electrode structure 12, and concentrate on the active area 112 outside the light shielding area for composite luminescence, so as to further reduce the light shielding effect of the electrode structure 12. In one embodiment, the reflective layer 15 directly contacts the first type semiconductor layer 111 to form an ohmic contact. In one embodiment, a transparent conductive layer (not shown) is further included between the reflective layer 15 and the first type semiconductor layer 111, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), titanium nitride (TiN), diamond-like carbon film (DLC) or graphene, and the transparent conductive layer directly contacts the first type semiconductor layer 111 to form an ohmic contact. In one embodiment, the reflective layer 15 may be patterned between two adjacent patterned insulating layers 14 or formed between two adjacent patterned insulating layers 14 and extended onto a portion of the patterned insulating layer 14.

The first barrier layer 16 can be disposed on the patterned insulating layer 14 and the reflective layer 15. The first barrier layer 16 and the semiconductor stack 11 are disposed on opposite sides of the patterned insulating layer 14 and/or the reflective layer 15, respectively. The first barrier layer 16 can cover the patterned insulating layer 14 and the reflective layer 15. The first barrier layer 16 can be used to prevent the material of the reflective layer 15 from diffusing during the manufacturing process and destroying the electrical properties of the light-emitting element 1.

The patterned insulating layer 14 may include a material with low light absorption rate, such as silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ) or niobium pentoxide (Nb ₂ O ₅ ). The material selection of the patterned insulating layer 14 can be selected and adjusted according to the wavelength of the light emitted by the active area 112. The reflective layer 15 may include a metal material, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), tungsten (W), rhodium (Rh) or alloys or stacks of the above materials. In one embodiment, the reflective layer 15 may include a multi-layer structure (not shown). For example, the reflective layer 15 may include a multi-layer structure of a stacked first metal layer, a second metal layer, and a third metal layer. The first metal layer, the second metal layer, and the third metal layer may be stacked sequentially along the negative Z direction. The first metal layer may include silver (Ag), the second metal layer may include titanium tungsten (TiW), and the third metal layer may include platinum (Pt).

The first barrier layer 16 may include a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), rhodium (Rh), or an alloy or stack of the above materials. In one embodiment, the first barrier layer 16 may include a multi-layer structure (not shown), for example, the first barrier layer 16 may include a multi-layer structure of a stacked first metal layer, a second metal layer, and a third metal layer, and the first metal layer, the second metal layer, and the third metal layer may be stacked in sequence along the negative Z direction. The metal layer stacking method and material selection of the first barrier layer 16 can be selected and adjusted according to the wavelength of the light emitted by the active area 112. For example, when the light emitted by the active region 112 is UV light, a metal with a higher reflectivity to UV light can be selected as the material of the first barrier layer 16. For example, the first metal layer can include aluminum (Al), the second metal layer can include titanium tungsten (TiW), and the third metal layer can include platinum (Pt). In one embodiment, the first barrier layer 16 can include a multi-layer structure of a stacked first metal layer and a second metal layer. The first metal layer and the second metal layer can be stacked in sequence along the negative Z direction. The first metal layer can include titanium tungsten (TiW), and the second metal layer can include platinum (Pt).

The light-emitting element 1 may also include a second barrier layer 17 and a bonding layer 18 disposed between the first barrier layer 16 and the supporting substrate 19. The second barrier layer 17 and the bonding layer 18 may be disposed on the first barrier layer 16 in sequence along the negative Z direction. The second barrier layer 17 may be used to prevent the material of the bonding layer 18 from diffusing to the first barrier layer 16 and/or the reflective layer 15 during the manufacturing process, thereby affecting the reflectivity and conductive properties of the reflective layer 15 and/or the first barrier layer 16. The bonding layer 18 may be used to bond the supporting substrate 19, the semiconductor stack 11, and the above-mentioned stacked structure formed thereon.

The second barrier layer 17 may include a metal material, such as chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or an alloy or a stack of the above materials. In one embodiment, when the second barrier layer 17 is a metal stack, the second barrier layer 17 may include a structure formed by alternating stacking of two or more metal layers, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, TiW/Pt, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn. When the light-emitting element 1 is a vertical light-emitting element, the bonding layer 18 may include a transparent conductive material or a metal material; the transparent conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cadmium oxide (ICO) , indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials; metal materials include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), indium (In) or alloys or stacks of the above materials. When the light emitting element 1 is a horizontal light emitting element, the bonding layer 18 may include non-conductive materials, such as silicon oxide (SiO ₂ ), benzocyclobutene (BCB), silicon nitride (SiN _x ), bonding adhesive (such as epoxy resin, UV curing adhesive, etc.), or a combination thereof.

The light-emitting element 1 may further include a protective layer 13. The protective layer 13 may be disposed on the first rough upper surface 120s of the first region 120 of the second type semiconductor layer 110 and on the second rough upper surface 130s of the second region 130. The protective layer 13 may cover the second rough upper surface 130s of the second region 130 of the second type semiconductor layer 110, and may cover a portion of the first rough upper surface 120s of the first region 120 of the second type semiconductor layer 110. The protective layer 13 may extend to cover the side surface of the semiconductor stack 11. The protective layer 13 may further cover the patterned insulating layer 14. In the embodiment shown in FIG. 2 , the protective layer 13 has a plurality of openings, and the electrode structure 12 can pass through the openings to contact the second type semiconductor layer 110 of the semiconductor stack 11. In another embodiment, the electrode structure 12 is located on the protective layer 13 and covers a portion of the protective layer 13, and passes through the openings to contact the second type semiconductor layer 110 of the semiconductor stack 11. In one embodiment, the protective layer 13 can conformally cover the rough upper surface of the second type semiconductor layer 110 and extend to cover the electrode structure 12. In one embodiment, the protective layer 13 can conformably cover the rough upper surface of the second type semiconductor layer 110, so the upper surface of the protective layer 13 can include a concave-convex pattern. The protective layer 13 can include an insulating material; the insulating material includes but is not limited to silicon oxide (SiO ₂ ), silicon nitride (SiN _x or Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ) or a combination of the above materials.

The following is an exemplary description of the manufacturing process of the light-emitting element 1 according to this application with reference to Figures 3-9, but this application is not limited thereto.

Please refer to FIG. 3. The semiconductor stack 31 can be grown on the growth substrate wafer 301, for example, by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or sputtering or evaporation plasma deposition to sequentially grow the buffer layer 302, the second type semiconductor layer 310, the active region 112 and the first type semiconductor layer 111 on the growth substrate wafer 301. The second type semiconductor layer 310 is between the buffer layer 302 and the active region 112. The active region 112 is between the first type semiconductor layer 111 and the second type semiconductor layer 310.

Please refer to Figures 4-5. An insulating material layer 314 is formed on the surface 111s of the first type semiconductor layer 111. Then, the insulating material layer 314 is patterned, for example, by removing a portion of the insulating material layer 314 through a wet etching, dry etching or lift-off process to form a patterned insulating layer 14 and expose a portion of the surface 111s (as shown in Figure 5).

Next, as shown in FIG. 6 , a reflective layer 15 is formed on the exposed surface 111s and the patterned insulating layer 14, so that the reflective layer 15 and the first type semiconductor layer 111 are electrically connected. In one embodiment, the reflective layer 15 directly contacts the first type semiconductor layer 111 to form an ohmic contact. In one embodiment, a transparent conductive layer (not shown) is further included between the reflective layer 15 and the first type semiconductor layer 111, and the transparent conductive layer directly contacts the first type semiconductor layer 111 to form an ohmic contact.

Next, as shown in FIG. 7 , a first barrier layer 16 and a second barrier layer 17 are sequentially formed on the patterned insulating layer 14 and the reflective layer 15, for example, by deposition, sputtering or evaporation. A bonding layer 18 is formed on the second barrier layer 17 to bond with the supporting substrate 19 through the bonding layer 18. In one embodiment, the bonding layer 18 may be formed on the supporting substrate 19, and then the supporting substrate 19 is bonded to the second barrier layer 17 through the bonding layer 18. In another embodiment, the bonding layer 18 may be partially formed on the second barrier layer 17 and partially formed on the supporting substrate 19, and then the two portions of the bonding layer 18 are bonded to each other so that the supporting substrate 19 is bonded to the second barrier layer 17 through the bonding layer 18. In one embodiment, the second barrier layer 17, the bonding layer 18 and the supporting substrate 19 are bonded, for example, by a hot pressing process. Then, the lower electrode structure 20 can be formed on the supporting substrate 19 by deposition, sputtering or evaporation.

The growth substrate wafer 301 on the second type semiconductor layer 310 can be removed by laser. The buffer layer 302 is then subjected to a front etching process to remove the buffer layer 302 to expose the second type semiconductor layer 310. The front etching process can be dry etching or wet etching. In one embodiment, the front etching process used to remove the buffer layer 302 is dry etching, for example, inductively coupled plasma (ICP) etching can be used. Then, the second type semiconductor layer 310 is subjected to a first etching process to form a rough area. The rough area includes a first area 120 and a second prepared area (not shown) surrounded by the first area 120. The second preparation area is subjected to a second etching process to remove a portion of the second type semiconductor layer 310 located in the second preparation area, and a second type semiconductor layer 110 including a first area 120 and a second area 130 surrounded by the first area 120 is formed, as shown in FIG. 8 . The first etching process and the second etching process may be performed by dry etching or wet etching. The first etching process and the second etching process may be the same or different. In one embodiment, the first etching process is wet etching, for example, potassium hydroxide (KOH) may be used for wet etching. In one embodiment, the second etching process is dry etching, for example, inductively coupled plasma etching may be used, but is not limited to the above methods. In one embodiment, the roughness (Ra) of the second rough upper surface 130s and the first rough upper surface 120s after the second etching process may be substantially the same or different. In one embodiment, the roughness of the second rough upper surface 130s after the second etching process is less than or greater than the roughness of the first rough upper surface 120s. By adjusting the roughness of the first rough upper surface 120s and the roughness of the second rough upper surface 130s to be different, the light extraction efficiency of the light-emitting element can be improved. By adjusting the first rough upper surface 120s and the second rough upper surface 130s to have the same or similar roughness, the appearance of the upper surface will not cause difficulty in subsequent identification due to the difference in roughness, and the reliability of subsequent processes can be improved. Next, the first type semiconductor layer 111, the active region 112, and the second type semiconductor layer 110 may be patterned, and portions of the first type semiconductor layer 111, the active region 112, and the second type semiconductor layer 110 may be removed to expose portions of the patterned insulating layer 14, thereby forming a chip separation region. The chip separation region defines the periphery of the light-emitting element 1. The method of patterning the first type semiconductor layer 111, the active region 112, and the second type semiconductor layer 110 may include dry etching or wet etching.

Next, a protective material layer (not shown) can be formed on the upper surface and sidewalls of the second semiconductor layer 110, the sidewalls of the active region 112, the sidewalls of the first semiconductor layer 111, and the exposed upper surface of the patterned insulating layer 14 by deposition, sputtering, or evaporation, and then a portion of the protective material layer can be removed by wet etching, dry etching, or a lift-off process to expose a portion of the first region 120 of the second semiconductor layer 110 and form a protective layer 13. Then, a metal film layer or film stack can be formed by deposition, sputtering or evaporation, and then the metal film layer or film stack can be patterned by wet etching, dry etching or lift-off process to form an electrode structure 12, so that the electrode structure 12 is formed on the first area 120 of the second type semiconductor layer 110, as shown in Figure 9. The supporting substrate 19 and the stacked layers thereon can be cut along the chip separation area to separate into multiple independent light-emitting elements 1. In one embodiment, the light-emitting element 1 as described in Figures 1-2 can be obtained by implementing the above method.

According to different applications, the light-emitting element 1 may be packaged. Please refer to FIG. 10, which is a cross-sectional schematic diagram of a light-emitting package 80 according to an embodiment. The light-emitting package 80 according to the embodiment may include a packaging wall 805, a packaging substrate 801, external electrodes 813 and 814 mounted on the packaging substrate 801, a light-emitting element 1 mounted in the packaging wall 805 and electrically connected to the external electrodes 813 and 814, and a packaging material 840 (which may include a phosphor to surround the light-emitting element 1). The external electrodes 813 and 814 are electrically insulated from each other, and provide power to the light-emitting element 1 through the wire 830. In addition, the external electrodes 813 and 814 can reflect the light emitted from the light-emitting element 1 to improve the light extraction efficiency, and discharge the heat emitted from the light-emitting element 1 to the outside. The light-emitting package 80 can be applied to a backlight unit, a lighting unit, a display device, an indicator, a lamp, a street lamp, a lighting device for a vehicle, a display device for a vehicle, or a smart watch, but is not limited thereto.

FIG. 11 is a schematic diagram of a light-emitting device 90 according to an embodiment. The light-emitting device 90 includes a lampshade 901, a reflector 902, a light-emitting module 905, a lamp holder 906, a heat sink 907, a connecting portion 908, and an electrical connecting element 909. The light-emitting module 905 includes a supporting portion 903 and a plurality of light-emitting units 904 located on the supporting portion 903. The plurality of light-emitting units 904 may be the light-emitting element 1 or the light-emitting package 80 in the aforementioned embodiment.

In the embodiment of the present application, the second type semiconductor layer includes a first region and a second region of different thicknesses, and the electrode structure is disposed on the thicker first region, which can effectively reduce the problem of the second type semiconductor layer absorbing light and causing the brightness loss of the light-emitting element, and at the same time avoid the problem of the second type semiconductor layer being broken down and causing a short circuit when the electrode structure is disposed. In addition, the first region and the second region of the second type semiconductor layer have a rough upper surface, which can improve the light extraction efficiency.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.

1: Light-emitting element

11: Semiconductor stacking

12: Electrode structure

12a: First electron conducting part

12b: Second conductive part

13: Protective layer

14: Patterned insulating layer

15: Reflective layer

16: First barrier layer

17: Second barrier layer

18:Joint layer

19: Supporting substrate

20: Lower electrode structure

31: Semiconductor stacking

80: Luminescent package

90: Light-emitting device

110: Type II semiconductor layer

111: Type I semiconductor layer

111s:Surface

112: Active area

120: District 1

120a: First sub-area

120b: Peripheral area

120s: First rough upper surface

120w: side wall

130: District 2

130a: Second sub-area

130s: Second rough upper surface

301: Growth substrate wafer

302: Buffer layer

310: Type II semiconductor layer

314: Insulation material layer

801:Packaging substrate

805: Encapsulation wall

813,814: External electrode

830: Conductor

840:Packaging material

901: Lampshade

902: Reflector

903: Carrying unit

904: Light-emitting unit

905: Light-emitting module

906: Lamp holder

907: Heat sink

908:Connection part

909:Electrical connection element

A-A’: section line

T1, T2: thickness

W1,W2,W3:Width

X,Y,Z: Direction

FIG. 1 is a schematic top view of a light-emitting element 1 according to an embodiment; FIG. 2 is a schematic cross-sectional view of the light-emitting element 1 along the section line A-A' shown in FIG. 1; FIGs. 3-9 are schematic cross-sectional views of some manufacturing steps of the light-emitting element 1 according to an embodiment; FIG. 10 is a schematic cross-sectional view of a light-emitting package 80 according to an embodiment; and FIG. 11 is a schematic view of a light-emitting device 90 according to an embodiment.

1: Light-emitting element

11: Semiconductor stacking

12: Electrode structure

13: Protective layer

14: Patterned insulating layer

15: Reflective layer

16: First barrier layer

17: Second barrier layer

18:Joint layer

19: Supporting substrate

20: Lower electrode structure

110: Type II semiconductor layer

111: Type I semiconductor layer

111s:Surface

112: Active area

120: District 1

120a: First sub-area

120b: Peripheral area

120s: First rough upper surface

120w: side wall

130: District 2

130a: Second sub-area

130s: Second rough upper surface

T1, T2: thickness

X,Y,Z: Direction

Claims (10)

A light-emitting element comprises: a semiconductor stack, comprising a first type semiconductor layer, an active region and a second type semiconductor layer stacked in sequence along a vertical direction, wherein the second type semiconductor layer comprises a first region and a second region connected to the first region, the first region has a first rough upper surface, and the second region has a second rough upper surface; and an electrode structure formed on the first rough upper surface of the first region of the second type semiconductor layer and electrically connected to the second type semiconductor layer; wherein the first region is in the vertical direction. A first thickness of the first region is not equal to a second thickness of the second region in the vertical direction, and the roughness (Ra) of the first rough upper surface and the second rough upper surface are substantially equal; wherein the first region comprises one or more first sub-regions arranged at intervals along a horizontal direction perpendicular to the vertical direction, and the electrode structure comprises one or more first conductive portions respectively arranged on the one or more first sub-regions; wherein a width of one of the one or more first sub-regions in the horizontal direction is greater than a width of one of the one or more first conductive portions in the horizontal direction. A light-emitting element as described in claim 1, wherein the second region is surrounded by the first region. A light-emitting element as described in claim 1, wherein the difference between the first thickness and the second thickness is between 1 and 1.5 micrometers (μm). The light-emitting element as described in claim 1, wherein the first region of the second type semiconductor layer has a sidewall, the sidewall has a rough surface, and the roughness (Ra) of the rough surface is less than the roughness (Ra) of the first rough upper surface of the first region. The light-emitting element as described in claim 1, wherein the first region of the second-type semiconductor layer further includes a peripheral region surrounding the one or more first sub-regions. The light-emitting element as described in claim 1, wherein the second region comprises a plurality of second sub-regions arranged at intervals along the horizontal direction, and the second sub-regions and the one or more first sub-regions are arranged alternately along the horizontal direction. A light-emitting element as described in claim 6, wherein a width of one of the second sub-regions in the horizontal direction is greater than a width of one of the one or more first sub-regions in the horizontal direction. A light-emitting element as described in claim 5, wherein the electrode structure further comprises a second conductive portion surrounding the one or more first conductive portions. The light-emitting element as described in claim 1, wherein the difference between the width of the one or more first sub-regions in the horizontal direction and the width of the one or more first conductive sub-parts in the horizontal direction is not less than 20μm and not more than 40μm. A light-emitting element as described in claim 1, wherein the first thickness is greater than the second thickness.

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