TWI863579B - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, an epitaxy layer, a pair of well regions, a pair of doping regions, a pair of first conductive structure, and a second conductive structure. The epitaxy layer is disposed on the substrate. The pair of the well region is disposed in the epitaxy layer. The pair of the doping region is disposed in the pair of the well region. The pair of the first conductive structure is disposed on a side of the pair of the well regions, respectively. The second conductive structure is disposed on the pair of the well regions.

Description

Semiconductor devices

The present invention relates to a semiconductor device, and in particular to a semiconductor device of a double diffused metal oxide semiconductor field-effect transistor (DMOSFET) combining a planar gate and a trench gate.

High voltage component technology is generally used in high voltage and high power circuits or drive circuits. Currently, structures such as planar gate and trench gate double diffused metal oxide semi-conductor field effect transistors have been developed.

However, the existing structure is still not satisfactory. For example, whether it is a planar gate or a trench gate double diffused metal oxide semi-field effect transistor, the current density in its channel region is still insufficient, resulting in performance that is not as good as expected. Therefore, the industry still needs improved methods to reduce the on-resistance (Ron) and improve performance.

Some embodiments of the present disclosure provide a semiconductor device. A semiconductor device is provided. The semiconductor device includes a substrate, an epitaxial layer, a pair of well regions, a pair of doped regions, a pair of first conductive structures, and a second conductive structure. The epitaxial layer is disposed on the substrate. The pair of well regions is disposed in the epitaxial layer. The pair of doped regions is disposed in the pair of well regions. The pair of first conductive structures are respectively disposed on one side of the pair of well regions. The second conductive structure is disposed on the pair of well regions. The epitaxial layer and the pair of doped regions have a first conductive type. The pair of well regions have a second conductive type different from the first conductive type.

Some embodiments of the present disclosure also provide a semiconductor device. This semiconductor structure includes a substrate, an epitaxial layer, and at least one structural unit. The epitaxial layer is disposed on the substrate. Each structural unit includes: a pair of first conductive structures, a second conductive structure, a pair of well regions, and a pair of doped regions. The pair of first conductive structures are disposed at the outermost side of the structural unit. The second conductive structure is disposed on the epitaxial layer. The pair of well regions are disposed between the pair of first conductive structures. The pair of doped regions are disposed in the pair of well regions. The epitaxial layer and the pair of doped regions have a first conductive type. The pair of well regions have a second conductive type different from the first conductive type. Each structural unit is symmetrical with the second conductive structure as the center.

Some embodiments of the present disclosure also provide a semiconductor device. This semiconductor structure includes a substrate, an epitaxial layer, and at least one structural unit. The epitaxial layer is disposed on the substrate. Each structural unit includes: a well region, a doped region, a first conductive structure, and a second conductive structure. The well region is disposed in the epitaxial layer. The doped region is disposed in the well region. The first conductive structure is disposed in the epitaxial layer. The second conductive structure is disposed on the epitaxial layer. The epitaxial layer and the doped region have a first conductive type. The well region has a second conductive type different from the first conductive type. The well region and the first conductive structure are disposed under both sides of the second conductive structure, respectively.

10,20,30,40,50,60:Semiconductor devices

100: Substrate

200: Epitaxial layer

300,300A,300B: Well area

400: Mixed area

410,410A,410B: First doping area

420,420A,420B: Second doping area

500,500A,500B: First conductive structure

510,510A,510B: first conductor layer

520,520A,520B: first dielectric layer

530,530A,530B: bottom conductor layer

600: Second conductive structure

610,610A,610B: Second conductor layer

620: Second dielectric layer

700: Upper electrode layer

800: Lower electrode layer

900,900A,900B,900M,900C1,900C2: shielding layer

AA’,BB’: section line

AC:Electron Accumulation Layer

CA1, CA2, CB1, CB2: channel area

eA1,eA2,eB1,eB2: current

U1,U2,U3,U4,U5,U6: structural unit

P1,P2,P3,P4,P5,P6: unit spacing

X: First direction

Y: Second direction

Z: height direction

FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of some embodiments of the present invention.

FIG. 1-1 is a top view of a semiconductor device according to the first embodiment of some embodiments of the present invention.

Figure 1-2 is another cross-sectional view of a semiconductor device according to the first embodiment of some embodiments of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of some embodiments of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment of some embodiments of the present invention.

Figure 3-1 is a top view of some components in a semiconductor device according to the third embodiment of some embodiments of the present invention.

Figure 3-2 is a top view of some components in a semiconductor device according to the third embodiment of some embodiments of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device according to the fourth embodiment of some embodiments of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device according to the fifth embodiment of some embodiments of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor device according to the sixth embodiment among some embodiments of the present invention.

The following disclosure provides many different embodiments or examples for implementing different components of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the disclosed embodiments. Of course, these are only examples and are not intended to limit the disclosure. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first component and the second component are directly in contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that they are not directly in contact. In addition, the disclosed embodiments may repeat component symbols and/or characters in different examples. Such repetition is for simplicity and clarity, and is not used to indicate the relationship between the different embodiments and/or patterns discussed.

Some variations of the embodiments are described below. In the different drawings and described embodiments, similar element symbols are used to indicate similar elements. It is understood that additional operations may be provided before, during, or after the method, and some of the described operations may be replaced or deleted for other embodiments of the aforementioned method.

Furthermore, spatially relative terms such as "on", "under", "above", "below" and similar terms include not only the orientation shown in the diagram, but also different orientations of the device in use or operation. When the device is turned to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein may also be interpreted according to the rotated orientation.

The embodiment of the present invention has a double diffused metal oxide semi-conductor field effect transistor (DMOS) (hereinafter referred to as a conductive structure) combining a planar gate and a trench gate to reduce the on-voltage while maintaining the breakdown voltage. In addition, the embodiment of the present invention can further reduce the electric field of the conductive structure and reduce the parasitic capacitance between the gate and the drain by setting a shielding layer at the bottom of the conductive structure. In addition, the embodiment of the present invention can further reduce the electric field at the corner of the conductive structure by covering the bottom edge of the conductive structure with a shielding layer. In addition, the embodiment of the present invention can further reduce the capacitance of the gate to the drain by using a conductive structure with a separated gate, thereby improving the switching characteristics of the semiconductor device. In addition, the embodiment of the present invention further forms an electron accumulation layer on one side of the conductive structure by using an asymmetric semiconductor device to further reduce the on-resistance. As mentioned above, the embodiment of the present invention can increase the switching speed and reduce energy loss, thereby improving the performance of the semiconductor device.

The following describes some variations of the embodiments. In the different drawings and described embodiments, similar reference numbers are used to indicate similar components. In addition, in the following drawings, when the same or similar components are distributed in different regions, the component symbol located on the left side (or -X direction side) of the drawing includes "A", and the component symbol located on the right side (or X direction side) of the drawing includes "B". It should be noted that additional components can be added to the semiconductor devices in the following embodiments. In addition, in different embodiments, some of the components described below can also be moved, deleted or replaced.

[First embodiment]

According to the first embodiment of some embodiments of the present invention, FIG. 1, FIG. 1-1 and FIG. 1-2 respectively show a cross-sectional view of the semiconductor device 10 along the section line AA', a top view, and a cross-sectional view along the section line BB'.

First, please refer to FIG. 1. In the embodiment of FIG. 1, the semiconductor device 10 includes a substrate 100 and an epitaxial layer 200 disposed on the substrate 100. In one example, the semiconductor device 10 further includes a well region 300 disposed in the epitaxial layer 200 and a doping region 400 disposed in the well region 300. The well region 300 may include a pair of well regions 300A and 300B. The doping region 400 may include a pair of first doping regions 410A and 410B. In some embodiments, the semiconductor device 10 further includes a first conductive structure 500 disposed on one side of the well region 300. Specifically, the first conductive structure 500 may include a pair of conductive structures 500A and 500B, which are respectively disposed on one side of the well region 300A and one side of the well region 300B. More specifically, the pair of conductive structures 500A and 500B are disposed on the outer sides of the pair of well regions 300A and 300B. In some embodiments, the semiconductor device 10 further includes a second conductive structure 600 disposed on the well region 300.

In addition, in another example, the semiconductor device 10 further includes at least one structural unit U1. This structural unit includes: a pair of first conductive structures 500A and 500B disposed at the outermost side of the structural unit U1, and a second conductive structure 600 disposed on the epitaxial layer 200. This structural unit further includes: a pair of well regions 300A and 300B disposed between the pair of first conductive structures 500A and 500B, and a pair of first doped regions 410A and 410B disposed in the pair of well regions 300A and 300B. This structural unit U1 is symmetrical with the second conductive structure 600 as the center.

In some embodiments, the structural unit U1 has a spacing P1, which is defined as the distance between the center lines of the first conductive structure 500A and the first conductive structure 500B. The structural unit U1 can be regarded as the smallest functional unit of the semiconductor device 10, for example, it can be regarded as a set of dual gate field effect transistors. That is, the semiconductor device 10 can have a plurality of structural units U1.

Each component in the semiconductor device 10 will be described in detail below.

In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, such as a silicon wafer, a bulk semiconductor, or a wide bandgap semiconductor. In some embodiments, the substrate 100 may be an elemental semiconductor, such as a silicon substrate; the substrate 100 may also be a compound semiconductor, such as a silicon carbide substrate or a gallium nitride substrate. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate. When the substrate 100 is doped, the substrate 100 may be p-type.

In some embodiments, the epitaxial layer 200 has a first conductivity type, such as n-type. In some embodiments, the doping concentration of the epitaxial layer 200 may be approximately 10 ¹⁵ -10 ¹⁷ atoms/cm ³ . In some embodiments, the formation of the epitaxial layer 200 may include performing an epitaxial growth process on the substrate 100, or performing an implantation process on the substrate 100, such as metal organic chemical vapor deposition (MOCVD), plasma-enhanced CVD (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable process methods or combinations thereof. In the embodiment of the present invention, the epitaxial layer 200 having the first conductivity type may be used as a drift region of a semiconductor device.

In some embodiments, the well region 300 (including the well region 300A and the well region 300B) is disposed in the upper region of the epitaxial layer 200. In the embodiment of FIG. 1, in the first direction X, the well region 300A and the well region 300B are separated from each other by the epitaxial layer 200. In the embodiment of FIG. 1, the well region 300 can be used as a channel region of a semiconductor device.

In some embodiments, the well region 300 (including the well region 300A and the well region 300B) has a second conductivity type different from the first conductivity type, such as p-type, and its dopant is, for example, aluminum (Al), boron (B) or other suitable dopant. In some embodiments, the doping concentration of the well region 300 can be greater than the doping concentration of the epitaxial layer 200, for example, the doping concentration of the well region 300 can be about 10 ¹⁷ -5x10 ¹⁸ atoms/cm ³ . In some embodiments, the formation of the well region 300 can include an ion implantation process, etc.

In some embodiments, the doping region 400 includes a first doping region 410 (including a first doping region 410A and a first doping region 410B). In other embodiments, the doping region 400 may further include a second doping region (see FIGS. 1-2 below). In the embodiment of FIG. 1, the first doping region 410A and the first doping region 410B are disposed in the well region 300A and the well region 300B, respectively. That is, the first doping region 410A and the first doping region 410B are separated from each other by the well region 300A, the epitaxial layer 200, and the well region 300B. Thus, the well regions 300A and 300B can be connected to the source through good ohmic contact to reduce the influence of the body effect and stabilize the starting voltage. In the embodiment of FIG. 1, the depth of the first doped region 410A or the first doped region 410B does not exceed the depth of the well region 300A or the well region 300B (for example, the well region 300A covers the bottom surface of the first doped region 410A) to reduce the influence of the body effect.

In some embodiments, the first doped region 410 has a first conductivity type, such as n-type. In some embodiments, the doping concentration of the first doped region 410 may be approximately 10 ¹⁹ -5× ^{10 20} atoms/cm ³ , so as to facilitate the subsequent formation of an ohmic contact interface with a metal thereon.

In some embodiments, a implantation process may be performed on the top surface of the epitaxial layer 200 to obtain the first doped region 410.

In some embodiments, the first conductive structure 500 (including the first conductive structure 500A and the first conductive structure 500B) is disposed on one side of the well region 300. In the embodiment of FIG. 1, the first conductive structure 500A and the first conductive structure 500B are disposed on the outer side of the well regions 300A and 300B. Alternatively, in the first direction X, the first conductive structures 500A and 500B are separated from each other by the well region 300A, the epitaxial layer 200, and the well region 300B. More specifically, the first conductive structure 500A is disposed on the left side (-X direction side) of the well region 300A, and the first conductive structure 500B is disposed on the right side (+X direction side) of the well region 300B.

The first electrode structure 500 (including the first conductive structures 500A and 500B) can be a general trench gate structure (as shown in FIG. 1 ) or a split gate trench structure (as shown in FIG. 5 ). In the embodiment of FIG. 1 , the first conductive structure 500A and the first conductive structure 500B are general trench gate structures, which respectively include a first conductive layer 510A and a first dielectric layer 520A surrounding the first conductive layer 510A, and a first conductive layer 510B and a first dielectric layer 520B surrounding the first conductive layer 510B. In the embodiment of FIG. 1 , the first conductive layer 510A and the first conductive layer 510B themselves can also be regarded as the gate of the semiconductor device 10.

In some embodiments, the first conductive layer 510A or 510B may be a single-layer or multi-layer conductive material, which is formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or a combination of the foregoing materials. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide ( _WSix ). In some embodiments, the first conductive layer 510A or 510B may selectively include a dopant of the second conductivity type, ie, p-type, which may be aluminum (Al), boron (B), boron difluoride (BF ₂ ) or other suitable dopant.

In some embodiments, the formation of the first conductive layer 510A or 510B may include a deposition process, a thermal process (such as an annealing process), a removal process, other suitable processes, etc. In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistive heating evaporation, electron beam evaporation, suitable methods, etc. In some embodiments, the removal process may include a planarization process, an etching process, etc., such as a chemical mechanical polishing (CMP) process, a dry etching process, etc.

In some embodiments, the first dielectric layer 520A or 520B may be silicon oxide, other suitable dielectric materials, or a combination of the foregoing materials. In some embodiments, the formation of the first dielectric layer 520A or 520B may include a conformably deposition process or an oxidation process, other suitable processes, etc. In some embodiments, the oxidation process may be thermal oxidation, or other suitable processes. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma-assisted chemical vapor deposition (PECVD), other suitable processes, or a combination of the foregoing processes.

For example, the formation of the first conductive structure 500A (or 500B) may include the following steps: forming a trench at a predetermined position by an etching process or the like; forming a first dielectric layer 520A (or 520B) in the trench by an oxidation process or the like; forming a conductive material on the shielding dielectric layer by a deposition process or the like; and removing excess conductive material by a removal process or the like to form a first conductive layer 510A (or 510B).

The aforementioned lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination thereof. The aforementioned etching process may include dry etching process, wet etching process, or other suitable etching process. The aforementioned dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching ( RIE), neutral beam etching (NBE), and inductive coupled plasma etching (inductive coupled plasma etch). The aforementioned wet etching may include using an acid solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. In addition, the etching process may also be pure chemical etching, pure physical etching, or any combination thereof.

In some embodiments, the second conductive structure 600 is disposed on the well region 300. In the embodiment of FIG. 1, the second conductive structure 600 is disposed across the well region 300A and the well region 300B, and completely covers the well region 300A and the well region 300B. In addition, the second conductive structure 600 is also disposed across the first doped region 410A and the first doped region 410B, but does not completely cover the first doped region 410A and the first doped region 410B. That is, a portion of the top surface of the first doped region 410A and the first doped region 410B is covered by the second conductive structure 600, while the other portion is exposed. In the embodiment of FIG. 1, in the first direction X, the second conductive structure 600 is disposed between the first conductive structure 500A and the first conductive structure 500B.

The second electrode structure 600 can be a general planar gate structure (as shown in FIG. 1) or a split gate planar gate structure (as shown in FIG. 5). In the embodiment of FIG. 1, the second conductive structure 600 is a general planar gate structure, which includes a second conductive layer 610 and a second dielectric layer 620 surrounding the second conductive layer 610. In the embodiment of FIG. 1, the second conductive layer 610 itself can also be regarded as a gate of the semiconductor device 10.

In some embodiments, the materials and methods of the second conductive layer 610 and the second dielectric layer 620 may be similar to the materials and methods of the first conductive layer 510A or the first conductive layer 510B and the first dielectric layer 520A or 520B, which will not be described in detail herein.

For example, the formation of the second conductive structure 600 may include the following steps: forming a gate oxide layer at a predetermined position by an oxidation process or the like; depositing a conductive material on the gate oxide layer by a deposition process or the like; removing excess conductive material by a removal process or the like to form a second conductive layer 610; and forming a top dielectric layer on the second conductive layer by a deposition process or the like. The shielding dielectric layer and the top dielectric layer are regarded as the second dielectric layer 620.

In some embodiments, the semiconductor device 10 further includes an upper electrode layer 700 and a lower electrode layer 800, which are disposed on the epitaxial layer 200 and below the substrate 100, respectively. That is, the upper electrode layer 700 and the lower electrode layer 800 are respectively located on both sides of the substrate 100. More specifically, the upper electrode layer 700 and the lower electrode layer 800 are respectively located on the substrate 100 (+Z direction side) and below the substrate 100 (-Z direction side). In some embodiments, the upper electrode layer 700 and the lower electrode layer 800 are respectively electrically connected to the source and drain (not shown) of the semiconductor device 10. In the embodiment of FIG. 1, the upper electrode layer 700 and the lower electrode layer 800 themselves can also be regarded as the source and drain of the semiconductor device 10, respectively.

In some embodiments, the upper electrode layer 700 and the lower electrode layer 800 may include the same or different materials, which may be metals or metal nitrides. For example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), beryllium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), niobium (Os), thorium (Th), vanadium (V) or a combination thereof.

In some embodiments, the upper electrode layer 700 and the lower electrode layer 800 can be formed by a deposition process similar to the above-mentioned one, which will not be described in detail here. For example, a device process is performed on one side (e.g., the front side) of the substrate 100 and the upper electrode layer 700 is formed by a deposition process, sputtering, resistive heating evaporation, electron beam evaporation or any other suitable metal plating process, and then the lower electrode layer 800 is provided on the other side (e.g., the back side) of the substrate 100 by a similar method.

As mentioned above, the embodiment of the present invention can increase the electron current flow path and improve the electron current density by combining the first conductive structure 500 (including the first conductive structure 500A and the first conductive structure 500B) with the second conductive structure 600 (i.e., combining the trench gate structure and the planar gate structure).

Specifically, as shown in FIG. 1 , currents eA1 and eB1 are generated on both sides of the second conductive structure 600A. Furthermore, currents eA2 and eB2 are generated on one side (e.g., +X direction side) of the first conductive structure 500A and one side (e.g., -X direction side) of the first conductive structure 500B. That is, the well region 300A has channel regions CA1 and CA2 near the second conductive structure 600 and near the first conductive structure 500A, and the well region 300B has channel regions CB1 and CB2 near the second conductive structure 600 and near the first conductive structure 500B.

In other words, compared to using a trench gate structure or a planar gate structure alone, the embodiment of the present invention can generate twice the current path and twice the current density by combining the two.

Next, please refer to FIG. 1-1 and FIG. 1-2. In the embodiment of FIG. 1-1, the well region 300A and the well region 300B are located on both sides of the epitaxial layer 200. The doping region 400 (including the first doping region 410 and the second doping region 420) is located on both sides of the well regions 300A and 300B. Specifically, the first doping region 410A and the first doping region 410B are located on the left side (-X direction side) of the well region 300A and the right side (+X direction side) of the well region 300B, respectively. The plurality of second doped regions 420A and the plurality of second doped regions 420B are respectively located in the first doped region 410A and the first doped region 410B. More specifically, the plurality of second doped regions 420A are separated from each other by the first doped region 410A, and the plurality of second doped regions 420B are separated from each other by the first doped region 410B.

The difference between FIG. 1-2 and FIG. 1 is that the semiconductor device 10 further includes a second doping region 420 (including a second doping region 420A and a second doping region 420B). In the embodiment of FIG. 1-2, the second doping region 420A and the second doping region 420B are located below the two sides of the second conductive structure 600. In addition, the first doping region 410A is disposed on the two sides of the second doping region 420A, and the first doping region 410B is disposed on the two sides of the second doping region 420B. Specifically, in the first direction X, the second doped region 420A is separated from the well region 300A by the first doped region 410A, and is also separated from the first conductive structure 500A by the first doped region 410A. Similarly, in the first direction X, the second doped region 420B is separated from the well region 300B by the first doped region 410B, and is also separated from the first conductive structure 500B by the first doped region 410B. In this way, the well regions 300A and 300B can be connected to the source via a good ohmic contact to reduce the influence of the body effect and stabilize the starting voltage.

In some embodiments, the second doped region 420 has a second conductivity type, such as p-type. In some embodiments, the doping concentration of the second doped region 420 may be approximately 10 ¹⁹ -10 ²¹ atoms/cm ³ to facilitate subsequent formation of an ohmic contact interface with a metal thereon.

[Second embodiment]

According to a second embodiment of some embodiments of the present invention, FIG. 2 shows a cross-sectional view of a semiconductor device 20 along the section line AA'. The semiconductor device 20 is similar to the semiconductor device 10, and the difference is that the semiconductor device 20 further includes a shielding layer 900 disposed under the first conductive structure 500. That is, the structural unit U2 in the semiconductor device 20 further includes a pair of shielding layers 900A and 900B. Specifically, the shielding layer 900A and the shielding layer 900B are disposed under the first conductive structure 500A and the first conductive structure 500B, respectively. For example, the shielding layer 900A covers the bottom surface of the first conductive structure 500A. In this way, the electric field below the first conductive structure 500 can be further reduced and the parasitic capacitance between the gate and the drain can be reduced.

In some embodiments, the shielding layer 900 may be electrically connected to the source (e.g., may have a ground potential). In some embodiments, the shielding layer 900 has a second conductivity type, such as a p-type. In some embodiments, the doping concentration of the shielding layer 900 may be approximately 5x10 ¹⁶ -5x10 ¹⁷ atoms/cm ³ . In some embodiments, the shielding layer 900 is at a ground potential. In some embodiments, the structural unit U2 has a spacing P2 that is substantially the same as the spacing P1 of the structural unit U1.

[Third embodiment]

According to a third embodiment of some embodiments of the present invention, FIG. 3 shows a cross-sectional view of a semiconductor device 30 along the section line AA'. The semiconductor device 30 is similar to the semiconductor device 20, and the difference is that the semiconductor device 30 further includes a shielding layer 900M disposed in the epitaxial layer 200 and between the shielding layer 900A and the shielding layer 900B. That is, the structural unit U3 in the semiconductor device 30 further includes a shielding layer 900M. In some embodiments, the shielding layer 900M can be connected to or separated from the shielding layer 900A and the shielding layer 900B, and also has a ground potential. In the embodiment of FIG. 3, in the first direction X, the shielding layer 900M is separated from the shielding layer 900A and the shielding layer 900B by the epitaxial layer 200. In some embodiments, the shielding layer 900M can be located at any position between the shielding layer 900A and the shielding layer 900B. In the embodiment of FIG. 3, the shielding layer 900M is located in the middle of the shielding layer 900A and the shielding layer 900B. In some embodiments, in the height direction Z, the shielding layer 900M is separated from the second conductive structure 600 by the epitaxial layer 200. Thereby, the breakdown voltage of the semiconductor device is increased.

In some embodiments, the conductive type and doping concentration of the shielding layer 900M are similar to those of the shielding layer 900A and the shielding layer 900B, and will not be described in detail here. In some embodiments, the structural unit U3 has a spacing P3, which is substantially the same as the spacing P2 of the structural unit U2.

FIG. 3-1 and FIG. 3-2 respectively show top views of different examples of connecting shielding layer 900A, shielding layer 900B, and shielding layer 900M. In the embodiments of FIG. 3-1 and FIG. 3-2, semiconductor device 30 further includes shielding layer 900CA and shielding layer 900CB to respectively connect shielding layer 900A and shielding layer 900M, and shielding layer 900B and shielding layer 900M. That is, structural unit U3 of semiconductor device 30 further includes at least two shielding layers (e.g., shielding layer 900CA and shielding layer 900CB) as connecting bridges of shielding layer 900A, shielding layer 900B, and shielding layer 900C. In this way, the shielding layers 900 can all have the same electrical properties, for example, all are ground potential.

In the embodiment of FIG. 3-1, the shielding layer 900M is symmetrical with the center line. That is, the shielding layer 900CA and the shielding layer 900CB are located on both sides of the shielding layer 900M and overlap in the second direction Y. In addition, the length of the shielding layer 900CA is the same as the length of the shielding layer 900CB. That is, the distance between the shielding layer 900A and the shielding layer 900M is the same as the distance between the shielding layer 900B and the shielding layer 900M. As a result, the current is more stable and the breakdown voltage is also more stable.

In the embodiment of FIG. 3-2, the shielding layer 900M is not symmetrical with respect to the center line. That is, although the shielding layer 900CA and the shielding layer 900CB are located on both sides of the shielding layer 900M, they do not overlap in the second direction Y. Specifically, the shielding layer 900CA is located on the +Y direction side, and the shielding layer 900CB is located on the -Y direction side. Moreover, the length of the shielding layer 900CA is different from the length of the shielding layer 900CB. That is, the distance between the shielding layer 900A and the shielding layer 900M is different from the distance between the shielding layer 900B and the shielding layer 900M. In the embodiment of FIG. 3-2, the length of the shielding layer 900CA is shorter than the length of the shielding layer 900CB.

[Fourth embodiment]

According to the fourth embodiment of some embodiments of the present invention, FIG. 4 shows a cross-sectional view of the semiconductor device 40 along the section line AA'. The semiconductor device 40 is similar to the semiconductor device 30, and the difference is that the shielding layer 900A and the shielding layer 900B in the semiconductor device 40 further cover the bottom corners of the first conductive structure 500A and the first conductive structure 500B. That is, the shielding layer 900A completely covers the bottom surface of the first conductive structure 500A, and the shielding layer 900B completely covers the bottom surface of the first conductive structure 500B. Thereby, the surface electric field at the corner of the first conductive structure 500 can be further reduced, and the problem of thermal runaway can be reduced.

In some embodiments, the shielding layer 900A and the shielding layer 900B may cover a portion of the sidewall of the first conductive structure 500A and a portion of the sidewall of the first conductive structure 500B. In some embodiments, the structural unit U4 has a spacing P4, which is substantially the same as the spacing P3 of the structural unit U3.

[Fifth embodiment]

According to a fifth embodiment of some embodiments of the present invention, FIG. 5 shows a cross-sectional view of a semiconductor device 50 along the section line AA'. The semiconductor device 50 is similar to the semiconductor device 30, except that the first conductive structure 500 of the semiconductor device 50 is a separated trench gate structure and the second conductive structure 600 is a separated planar gate structure. Specifically, the first conductive structure 500A further includes a bottom conductive layer 530A separated from the first conductive layer 510A by a first dielectric layer 520A. The first conductive structure 500B further includes a bottom conductive layer 530B separated from the first conductive layer 510B by a first dielectric layer 520B. The second conductive layer 610 of the second conductive structure 600 includes a pair of second conductive layers 610A and 610B surrounded by a second dielectric layer 620.

In some embodiments, the bottom conductor layer (e.g., bottom conductor layer 530A or 530B) and the first conductor layer (e.g., first conductor layer 510A or 510B) can be electrically connected to the source and gate, respectively, to shield the gate and drift region (e.g., epitaxial layer 200) capacitance charge and discharge path, thereby further reducing the gate-to-drain capacitance (Cgd) and improving the switching characteristics of the semiconductor device. In some embodiments, the bottom conductor layer (e.g., bottom conductor layer 530A) directly contacts the shielding layer (e.g., shielding layer 900A).

In some embodiments, the bottom conductive layer 530A or 530B may include a material similar to the first conductive layer 510A or 510B, which will not be described in detail. In some embodiments, the bottom conductive layer 530A or 530B may selectively include a second conductive type dopant, i.e., p-type, which may be aluminum (Al), boron (B), boron difluoride (BF ₂ ) or other suitable dopant.

In some embodiments, the second conductor layer 610A and the second conductor layer 610B are separated by the second dielectric layer 620, which can reduce the area of the gate electrode covering the current spreading layer and further reduce the gate-to-drain capacitance (Cgd). In some embodiments, the second conductor layer 610A and the second conductor layer 610B are both electrically connected to the gate.

In some embodiments, the second conductive layer 610A and the second conductive layer 610B may include materials similar to the second conductive layer 610, which will not be described in detail here.

In some embodiments, the structural unit U5 has a spacing P5 that is substantially the same as the spacing P3 of the structural unit U3.

[Sixth embodiment]

According to a sixth embodiment of some embodiments of the present invention, FIG. 6 shows a cross-sectional view of a semiconductor device 60 along the section line AA′. The semiconductor device 60 is similar to the semiconductor device 50, and the difference lies in the relative positions of a pair of well regions 300 and a pair of first conductive structures 500 in the semiconductor device 60, and the semiconductor device 60 further includes another second conductive structure 600. Specifically, the well region 300 (corresponding to the well region 300A in FIG. 5 ) is disposed between the first conductive structure 500 (corresponding to the first conductive structure 500A in FIG. 5 ) and another first conductive structure 500 (corresponding to the first conductive structure 500B in FIG. 5 ), and another well region 300 (corresponding to the well region 300B in FIG. 5 ) is disposed outside the first conductive structure 500 and another first conductive structure 500. Specifically, the well region 300 and another first conductive structure 500 are separated by the epitaxial layer 200.

Furthermore, the second conductive structure 600 and another second conductive structure 600 are general planar gate structures. Specifically, the second conductive structure 600 includes a second conductive layer 610 and a second dielectric layer 620 surrounding the second conductive layer 610, and another second conductive structure 600 also includes another second conductive layer 610 and another second dielectric layer 620 surrounding the other second conductive layer 610.

In some embodiments, the second conductive layer 610 and another conductive layer 610 are disposed on the well region 300 and another well region 300, respectively. For example, one side of the second conductive layer 610 is located on the first doped region 410, and the other side is located on the epitaxial layer 200. That is, the second conductive layer 610 spans from the first doped region 410 to the epitaxial layer 200.

In some embodiments, the second conductive structure 600 contacts the first conductive structure 500, and another second conductive structure 600 contacts another first conductive structure 500. For example, the first conductive layer 510 and the first dielectric layer 520 directly contact the second dielectric layer 620.

In the embodiment of FIG. 6 , the structural unit U6 is not symmetrical with respect to the center line of the second conductive structure 600. Specifically, the structural unit U6 includes: a well region 300 disposed in the epitaxial layer 200, a first doped region 410 disposed in the well region 300, a first conductive structure 500 disposed in the epitaxial layer 200, and a second conductive structure 600 disposed on the epitaxial layer 200. In addition, the well region 300 and the first conductive structure 500 are disposed under both sides of the second conductive structure 600, respectively. In some embodiments, the structural unit U6 further includes a shielding layer 900 disposed under the first conductive structure 500, and its material and function are similar to those described above, and will not be described in detail here. In some embodiments, the structural unit U6 further includes an electron accumulation layer AC disposed on one side of the first conductive structure 500. Specifically, the electron accumulation layer AC may cover the entire side surface of the first conductive structure 500. In this way, the current density may be increased and the conduction resistance may be reduced, thereby improving the conduction characteristics of the semiconductor device.

In some embodiments, the structure unit U6 has a spacing P6, which is approximately half of the spacing P5 of the structure unit U5. That is, two structure units U6 can be equivalent to one structure unit U5. This further improves semiconductor performance.

In summary, the embodiment of the present invention combines the first conductive structure and the second conductive structure to reduce the conduction voltage while maintaining the breakdown voltage. Furthermore, the first conductive structure and the second conductive structure in the embodiment of the present invention can reduce the complexity of the process by sharing the well area.

In addition, the embodiment of the present invention can further reduce the electric field of the conductive structure by setting a shielding layer at the bottom of the first conductive structure. In addition, the embodiment of the present invention can increase the breakdown voltage by further setting a shielding layer between a pair of first conductive structures. In addition, the embodiment of the present invention can further reduce the electric field at the corner of the conductive structure by covering the bottom edge of the first conductive structure with a shielding layer. In addition, the embodiment of the present invention can further reduce the electric field at the corner of the conductive structure by setting a separated gate conductive structure. In addition, the embodiment of the present invention can not only reduce the distance between the structural units by using asymmetric structural units, but also form an electron accumulation layer on one side of the conductive structure to further reduce the on-resistance.

The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of this disclosure. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application scope constitutes a separate embodiment, and the scope of protection of this disclosure also includes the combination of each patent application scope and embodiment.

Several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the perspectives of the embodiments disclosed herein. Those with ordinary knowledge in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the disclosure.

10: Semiconductor devices

100: Substrate

200: Epitaxial layer

300,300A,300B: Well area

400: Mixed area

410,410A,410B: First doping area

500,500A,500B: First conductive structure

510A, 510B: first conductor layer

520A, 520B: first dielectric layer

600: Second conductive structure

610: Second conductor layer

620: Second dielectric layer

700: Upper electrode layer

800: Lower electrode layer

AA’: section line

CA1, CA2, CB1, CB2: channel area

eA1,eA2,eB1,eB2: current

U1: Structural unit

P1: Unit spacing

X: First direction

Z: height direction

Claims (18)

A semiconductor device includes: a substrate; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type; a pair of well regions disposed in the epitaxial layer, wherein the pair of well regions have a second conductivity type different from the first conductivity type; a pair of doped regions disposed in the pair of well regions, wherein the pair of doped regions have the first conductivity type; a pair of first conductive structures disposed in the pair of well regions, wherein the first conductive structures are ... second conductive structures are disposed in the pair of well regions, wherein the second conductive structures are disposed in the pair of well regions, wherein the second conductive structures are disposed in the pair of well regions, wherein the second conductive structures are disposed in the pair of well regions. The pair of first conductive structures extend into the epitaxial layer, and each of the pair of first conductive structures includes a first conductive layer and a first dielectric layer surrounding the first conductive layer, wherein the pair of first conductive structures further includes a pair of bottom conductive layers, wherein the pair of bottom conductive layers are separated from the pair of first conductive layers by the pair of first dielectric layers; and a second conductive structure is disposed on the pair of well regions. The semiconductor structure of claim 1 further includes a pair of shielding layers, respectively disposed under the pair of first conductive structures, wherein the pair of shielding layers have the second conductive type. The semiconductor device of claim 1 further includes a shielding layer disposed in the epitaxial layer and separated from the second conductive structure by the epitaxial layer, wherein the shielding layer has the second conductive type. A semiconductor device as claimed in claim 1, wherein the second conductive structure includes a second conductive layer and a second dielectric layer surrounding the second conductive layer. A semiconductor device as claimed in claim 1, wherein the second conductive structure includes a pair of second conductive layers and a second dielectric layer surrounding the pair of second conductive layers. A semiconductor device as claimed in claim 1, wherein the pair of well regions are disposed between the pair of first conductive structures. A semiconductor device as claimed in claim 1, wherein one of the pair of well regions is disposed between the pair of first conductive structures, and the other of the pair of well regions is disposed outside the pair of first conductive structures. The semiconductor device of claim 7 further includes: another second conductive structure, and the second conductive structure and the other second conductive structure include: a pair of second conductive layers disposed on the pair of well regions and a pair of second dielectric layers surrounding the pair of second conductive layers respectively. A semiconductor device as claimed in claim 8, wherein the second conductive structure contacts one of the pair of first conductive structures, and the other second conductive structure contacts the other of the pair of first conductive structures. The semiconductor device of claim 1 further includes an upper electrode layer and a lower electrode layer, which are disposed on the epitaxial layer and under the substrate respectively. A semiconductor device comprises: a substrate; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductive type; at least one structural unit, wherein each structural unit comprises: a pair of first conductive structures disposed at the outermost side of the structural unit, wherein the pair of first conductive structures extend into the epitaxial layer, wherein each of the pair of first conductive structures comprises a first conductive layer and a first dielectric layer surrounding the first conductive layer, wherein the pair of first conductive structures further The invention comprises a pair of bottom conductive layers, wherein the pair of bottom conductive layers are separated from the pair of first conductive layers by the pair of first dielectric layers; a second conductive structure disposed on the epitaxial layer; a pair of well regions disposed between the pair of first conductive structures, wherein the pair of well regions have a second conductive type different from the first conductive type; and a pair of doped regions disposed in the pair of well regions, wherein the pair of doped regions have the first conductive type, wherein each structural unit is symmetrical with respect to the second conductive structure as the center. A semiconductor device as claimed in claim 11, wherein the at least one structural unit further comprises at least two shielding layers, wherein in a top view, the at least two shielding layers are interconnected. A semiconductor device comprises: a substrate; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type; at least one structural unit, wherein each structural unit comprises: a well region disposed in the epitaxial layer, wherein the well region has a second conductivity type different from the first conductivity type; a doped region disposed in the well region, wherein the doped region has the first conductivity type; a first conductive junction A first conductive structure is disposed in the epitaxial layer, wherein the first conductive structure includes a first conductive layer and a first dielectric layer surrounding the first conductive layer, wherein the first conductive structure further includes a bottom conductive layer, wherein the bottom conductive layer is separated from the first conductive layer by the first dielectric layer; and a second conductive structure is disposed on the epitaxial layer, wherein the well region and the first conductive structure are respectively disposed under two sides of the second conductive structure. A semiconductor device as claimed in claim 13, wherein the second conductive structure includes a second conductive layer and a second dielectric layer surrounding the second conductive layer, wherein the first conductive layer and the first dielectric layer directly contact the second dielectric layer. A semiconductor device as claimed in claim 14, wherein the second conductive layer is disposed directly above the well region. A semiconductor device as claimed in claim 13, wherein the first conductive structure is separated from the well region by the epitaxial layer. A semiconductor device as claimed in claim 13, wherein each structural unit further comprises a shielding layer disposed under the first conductive structure, wherein the shielding layer has the second conductive type. A semiconductor device as claimed in claim 13, wherein each structural unit further comprises an electron accumulation layer disposed on one side of the first conductive structure.

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