TWI838121B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a high voltage well and a well region. The high voltage well is disposed in the substrate. The high voltage well has a first conductive type. The well is disposed in the high voltage well. The well has a second conductive type different from the first conductive type. The well extends along a first direction and has at least an opening.

Description

Semiconductor structure

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a Schottky barrier diode.

The integrated diode-complementary metal oxide semiconductor-double diffused metal oxide semiconductor (Bipolar-CMOS-DMOS, BCD) process can provide transistors with higher voltage or higher power output. However, this process is still not satisfactory. For example, it still has a large on-resistance (Ron), which makes the performance not as good as expected. Therefore, the industry still needs to improve methods to reduce the on-resistance (Ron) and improve performance.

Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high-pressure well, and a well region. The high-pressure well is disposed in the substrate. The high-pressure well has a first conductivity type. The well region is disposed in the high-pressure well. The well region has a second conductivity type different from the first conductivity type. The first edge of the well region extends along a first direction and has at least one opening. The at least one opening has a first opening width. The first edge has a first edge width.

Some embodiments of the present disclosure also provide a semiconductor structure. The semiconductor structure includes a substrate, a high-pressure well, a plurality of well regions, and a doped region. The high-pressure well is disposed in the substrate. The high-pressure well has a first conductivity type. A plurality of well regions are disposed in the high-pressure well. The plurality of well regions have a second conductivity type different from the first conductivity type. The plurality of well regions are spaced apart from each other. The doped region is disposed outside the plurality of well regions. The doped region has a first conductivity type.

The following disclosure provides many different embodiments or examples for implementing different components of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to limit the disclosure. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that they are not in direct contact. In addition, the disclosed embodiments may repeat component symbols and/or characters in different examples. Such repetition is for the sake of simplicity and clarity, and is not used to indicate the relationship between the different embodiments and/or aspects discussed.

Some variations of the embodiments are described below. In the different drawings and illustrated embodiments, similar element symbols are used to indicate similar elements. It is understood that additional operations may be provided before, during, or after the method, and some of the described operations may be replaced or deleted for other embodiments of the aforementioned method.

Furthermore, spatially relative terms such as "on", "below", "above", "below" and similar terms include not only the orientation shown in the drawings, but also different orientations of the device in use or operation. When the device is turned to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein can also be interpreted according to the rotated orientation.

The present invention provides a semiconductor structure with a Scottky barrier diode (SBD) to increase the breakdown voltage, reduce the on-state voltage, increase the reverse recovery speed, and improve the driving capability at low current. In addition, the present invention suppresses the leakage current when the device is turned off by setting a well region. In addition, the present invention further reduces the on-resistance (Ron) while maintaining a high breakdown voltage and low leakage current by setting at least one opening at the edge of the well region.

Some variations of the embodiments are described below. In the various drawings and described embodiments, similar reference numerals are used to designate similar elements.

FIG. 1 and FIG. 2 are top views showing semiconductor structures according to some embodiments of the present invention. FIG. 3 and FIG. 5 are schematic cross-sectional views of the semiconductor structure along section lines AA’ and BB’ of FIG. 2. FIG. 4 is an enlarged schematic view of box L in FIG. 3. Since the arrangement of components involves both the perspectives of the top view and the cross-sectional view, the arrangement of the components in FIGS. 1-5 will be summarized below, and the components of the top view will be first described in detail with reference to FIGS. 1-2, and then the components of the cross-sectional view will be described in detail with reference to FIGS. 3-5. It should be noted that additional components may be added to the semiconductor structure in the following embodiments. Furthermore, in different embodiments, some of the components described below may also be moved, deleted or replaced.

Referring to FIGS. 1-5 , a substrate 100 is provided. In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, such as a silicon wafer, a bulk semiconductor, or a wide bandgap semiconductor. In some embodiments, the substrate 100 may be an elemental semiconductor, such as a silicon substrate; the substrate 100 may also be a compound semiconductor, such as a silicon carbide substrate or a gallium nitride substrate. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate. In the case where the substrate 100 is doped, the substrate 100 may be p-type.

Continuing with FIGS. 1-5 , a high pressure well 200 is disposed in the substrate 100. In some embodiments, the high pressure well 200 has a first conductivity type, such as an n-type. In some embodiments, the doping concentration of the high pressure well 200 is about 10 ¹⁵ -10 ¹⁹ atoms/cm ³ . In some embodiments, the formation of the high pressure well 200 may include performing an epitaxial growth process on the substrate 100, or performing an implantation process on the substrate 100, such as metal organic chemical vapor deposition (MOCVD), plasma-enhanced CVD (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable process methods or combinations thereof.

1-5, a well region 300 is disposed in the high pressure well 200. In some embodiments, the well region 300 has a second conductivity type different from the first conductivity type, such as a p-type.

As shown in the top view of FIG. 1 , the well area 300 has a first side E1, which extends along the first direction Y and has a first opening O1 that exposes the high-pressure well 200 below. In addition, the well area 300 also includes a second side E2 relative to the first side E1, which extends along the first direction Y and has a second opening O2 corresponding to the first opening O1. In some embodiments, the first opening O1 and the second opening O2 have the same width, such as the first opening width a. In other embodiments, the first opening O1 and the second opening O2 may also have different widths (not shown). In some embodiments, the first opening O1 and the second opening O2 are located at the same position in the first direction Y. That is, they are aligned with each other. It should be noted that as long as there is at least one first opening O1 and one second opening O2, their number is not limited, for example, they can be two, three, four, etc.

In some embodiments, the first opening width a can be 0.05-3 μm, so as to reduce the current path and increase the surface current concentration without increasing the leakage current, thereby reducing the on-resistance (Ron) and improving the performance of the semiconductor structure. In some embodiments, compared with the case without the first opening (i.e., the first opening width a is 0 μm), the current can be increased by 22.2% when the first opening width a is, for example, 1 μm, the current can be increased by 33.3% when the first opening width a is, for example, 1.8 μm, and the current can be increased by up to 48.1% when the first opening width a is, for example, 2.6 μm. At the same time, the breakdown voltage can also be increased by, for example, 3.4% when the first opening width a is, for example, 2.6 μm.

In addition, as shown in the top view of FIG. 1, the well region 300 also includes a third side E3 and a fourth side E4 adjacent to the first side E1. In some embodiments, the third side E3 and the fourth side E4 extend along a second direction X perpendicular to the first direction Y. That is, the first side E1, the second side E2, the third side E3 and the fourth side E4 are connected to form a rectangular shape. In other embodiments, the well region 300 may also present a shape other than a rectangular shape, such as a square shape, a rectangular shape, a trapezoidal shape, a hexagonal shape, an octagonal shape, and there is no particular limitation as long as the leakage current can be suppressed.

In addition, the first side E1, the second side E2, the third side E3 and the fourth side E4 may have uniform widths, for example, respectively having a first side width PW1, a second side width PW2, a third side width PW3 and a fourth side width PW4. In some embodiments, the first side width PW1, the second side width PW2, the third side width PW3 and the fourth side width PW4 may be the same or different. In some embodiments, the first side width PW1, the second side width PW2, the third side width PW3 and the fourth side width PW4 are the same, so that the degree of suppressing leakage current is more uniform. In some embodiments, the first side width PW1, the second side width PW2, the third side width PW3, and the fourth side width PW4 may be 0.5-2.5 μm, respectively, so as to maintain a desired current density while suppressing leakage current.

In addition, as shown in the top view of FIG. 1, the well region 300 also includes a connecting bar C1 connecting the third side E3 and the fourth side E4. In some embodiments, the number of connecting bars is not limited, for example, it can be 1, 2, 3, etc. In some embodiments, the breakdown voltage can be increased as the number of connecting bars is increased. In the embodiment of FIG. 1, there are three connecting bars C1, C2, and C3, and the connecting bar C1 is symmetrical to the connecting bar C3 with the connecting bar C2 as the center. In the embodiment of the present invention, the well region includes connecting bars, and the surface current is increased while suppressing the leakage current.

In addition, as shown in FIG. 1 , the well region 300 formed by the first side E1, the second side E2, the third side E3, the fourth side E4, and the three connecting strips C1, C2, and C3 can be regarded as a P-type island (P island) to suppress the image-force barrier lowering (IFBL) and reduce the generation of leakage current.

In addition, the first side E1 and the connecting strip C1 may be separated by a distance b. In some embodiments, the distance b may be 0.5-2.5 μm to ensure sufficient current density. In some embodiments, the ratio of the distance b to the first side width PW1 may be 0.1-1, such as 0.5, to achieve the desired type of less leakage current and greater current.

Continuing with reference to FIGS. 1-5 , a doped region 400 is disposed on the top surface of the high-pressure well 200. In some embodiments, the doped region 400 has a first conductivity type, such as an n-type. In some embodiments, the doping concentration of the doped region 400 is about 10 ²⁰ -10 ²¹ atoms/cm ³ , so as to facilitate the subsequent formation of an ohmic contact interface with the metal thereon. As shown in the top view of FIG. 1 , the doped region 400 is disposed outside the well region 300 and surrounds the well region 300.

In some embodiments, the top surface of the high-pressure well 200 is first implanted, and then patterned by a patterning process (lithography and etching process) to obtain the doped region 400. The aforementioned lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes or a combination thereof. The aforementioned etching process may include a dry etching process, a wet etching process, or other suitable etching processes. The aforementioned dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), and inductive coupled plasma etching. The aforementioned wet etching may include using an acid solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. In addition, the etching process may also be pure chemical etching, pure physical etching, or any combination thereof.

Continuing with reference to FIGS. 1-5 , a dielectric layer 500 and a gate electrode 600 are disposed on the high-voltage well 200. As shown in the top view of FIG. 2 (dielectric layer 500 is not shown), the gate electrode 600 surrounds the well region 300 and covers a portion of the edge of the well region 300. In some embodiments, the gate electrode 600 can be used as a field plate.

In some embodiments, the first and second dielectric layers (collectively referred to as dielectric layer 500) may include the same or different dielectric materials, such as oxides. The aforementioned oxides may include silicon oxide, zirconium oxide, aluminum oxide, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate electrode 600 may include a conductive material, such as doped or non-doped amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. The aforementioned metals may include molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or halogenide (Hf). The metal nitride may include molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN) and tantalum nitride (TaN). The metal silicide may include tungsten silicide ( _WSix ). The conductive metal oxide may include ruthenium metal oxide ( _RuO2 ) and indium tin oxide (ITO).

In some embodiments, a first dielectric layer may be formed by a deposition process, a gate electrode may be formed by a deposition and patterning process (lithography and etching process), and then a second dielectric layer may be formed by a deposition process to obtain a dielectric layer 500 and a gate electrode 600 composed of the first and second dielectric layers as shown in the figure. The deposition process may include a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable processes or a combination thereof. The aforementioned CVD process may be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), PECVD, atmospheric pressure chemical vapor deposition (APCVD). The aforementioned patterning process is similar to the above and will not be described in detail here.

Continuing to refer to FIGS. 1-5, a cathode electrode 700 and an anode electrode 800 are disposed on the high-pressure well 200. In the top view (not shown), the anode electrode 800 can be disposed directly above the well region 300 (disposed in the central portion), and the cathode electrode 700 can be disposed directly above the doped region 400 (disposed in the peripheral portion). In some embodiments, the cathode electrode 700 can be disposed directly above a portion of the doped region 400, for example, directly above the doped region near the first side E1 and the second side E2 of the well region 300, but not directly above the third sides E3 and E4.

In some embodiments, the cathode electrode 700 and the anode electrode 800 may include the same or different materials, such as conductive materials, which are similar to those described above and will not be described in detail here. In some embodiments, the dielectric layer 500 may be patterned by a patterning process, and then the conductive material may be deposited by a deposition process, and then the conductive material may be patterned by a patterning process to simultaneously form the cathode electrode 700 and the anode electrode 800. The patterning process and the deposition process are similar to those described above and will not be described in detail here.

Next, the cross-sectional views are described in FIG. 3 and FIG. 5 obtained based on the section lines AA' and BB' of FIG. 2, and the detailed features of the device are described in detail by using the enlarged schematic view of the box L in FIG. 3 as shown in FIG. 4. The difference between FIG. 3 and FIG. 5 lies in the well area 300, which is described in detail as follows.

Please refer to the cross-sectional views of FIG. 3 and FIG. 5 at the same time. In FIG. 3 (section line AA'), the well region 300 includes a first side E1 and a second side E2 and three connecting bars C1, C2, and C3 (sometimes referred to as having a plurality of well regions 300), and are separated from each other by a high-voltage well 200 to reduce leakage current in the closed state. In some embodiments, the first side E1 and the second side E2 are disposed below the gate electrode, and details can be found in the partially enlarged schematic view of FIG. 4 and the subsequent description. In some embodiments, the three connecting bars C1, C2, and C3 are directly disposed directly below the anode electrode 800 and are in direct contact with it.

As shown in FIG. 3 , since the doping concentration of the doping region 400 is greater than the doping concentration of the high-pressure well 200 provided with the well region 300, different junctions with the metal electrodes thereon can be generated. For example, there is a Schottky contact interface S1 between the anode electrode 800 and the well region 300 (or the high-pressure well 200); and there is an Ohmic contact interface S2 between the cathode electrode 700 and the doping region 400. By having a lower junction voltage at the Schottky contact interface S1, the switching speed can be increased when switching from the on state to the off state.

In FIG. 5 (section line BB'), the well region 300 includes three connecting bars C1, C2, and C3, but does not have the first side E1 and the second side E2 (i.e., the first opening O1 corresponding to the first side E1 and the second opening O2 corresponding to the second side E2), thereby reducing the on-resistance.

Next, continue to refer to the cross-sectional views of FIG. 3 and FIG. 5. In FIG. 3 (section line AA'), a pair of gate electrodes 600 are disposed on the outermost first side E1 and second side E2 in the well region 300. That is, one gate electrode 600 is disposed directly above a portion of the first side E1 and separated by the dielectric layer 500; the other gate electrode 600 is disposed directly above a portion of the second side E2 and separated by the dielectric layer 500.

Next, the gate electrode 600 , the well region 300 (the first side E1 ) and the dielectric layer 500 are described in detail by using the enlarged schematic diagram of the box L in FIG. 3 , as shown in FIG. 4 .

As shown in FIG. 4 , the well region 300 (first side E1) has a maximum width W in the second direction X and a maximum depth D in the height direction Z. In some embodiments, the maximum width W may be approximately 1-2 μm. In some embodiments, the maximum depth D may be approximately 1.5-2.5 μm. In addition, the aspect ratio (D/W) calculated by the maximum depth D and the maximum width W may be approximately 0.5-2, thereby reducing leakage current in the off state and increasing current density in the on state to enhance the performance of the semiconductor structure.

As shown in FIG. 4 , the well region 300 and the gate electrode 600 are separated from each other by a dielectric layer 500 therebetween to prevent electrons from flowing directly from the gate electrode into the well region and causing a short circuit.

As shown in FIG. 4 , the well region 300 (first side E1) has an uneven top surface. In some embodiments, the outermost side of the well region 300 (first side E1) (i.e., the side close to the gate electrode) is the farthest from the gate electrode 600 in a vertical distance, while the innermost side of the well region 300 (first side E1) (i.e., the side far from the gate electrode) is the shortest from the gate electrode 600 in a vertical distance. That is, it can be seen that the well region 300 (first side E1) has a gradually rising top surface from the outermost side to the innermost side of the well region 300 (first side E1). In other words, the vertical distance from the outermost side of the well region 300 (the first side E1) to the innermost side of the well region 300 (the first side E1) and the gate electrode 600 becomes closer and closer.

In some embodiments, the top surface of the well region 300 and the bottom surface of the gate electrode 600 have a minimum distance HS1 and a maximum distance HS2. In some embodiments, the maximum distance HS2 may be about 3-4 μm, and the minimum distance HS1 may be about 0.01-0.03 μm. Since the maximum distance HS2 is much greater than the minimum distance HS1, the top surface of the well region 300 is almost in contact with the bottom surface of the gate electrode 600 in FIG. 3 and FIG. 5 .

In some embodiments, as long as the arrangement of the anode electrode 800 is not affected, the thickness HG of the gate electrode 600 is not particularly limited, and may be, for example, about 1-3 μm.

The embodiment of the present invention maintains high breakdown voltage and low leakage current and further reduces on-resistance (Ron) by setting a well region and setting an opening at its edge.

Next, FIGS. 6-9 are top views showing a semiconductor structure having a gate electrode according to other embodiments of the present invention.

First, please refer to FIG. 6 . FIG. 6 is similar to FIG. 2 , except that the third side E3 and the fourth side E4 have a third opening O3 and a fourth opening O4 , respectively; and the three connecting bars C1 , C2 , and C3 also have connecting bar openings OC1 , OC2 , and OC3 .

In some embodiments, the third opening O3 and the fourth opening O4 may be disposed in the third side E3 and the fourth side E4 to provide the current with more directions of flow. In some embodiments, the number of the third opening O3 and the fourth opening O4 is not particularly limited and may be set according to actual needs, for example, it may be the number of connecting strips or one more than the number of connecting strips. In some embodiments, the third opening O3 and the fourth opening O4 may correspond to each other, for example, be aligned with each other. In the embodiment of FIG. 6, the third opening O3 corresponds to the fourth opening O4. That is, the third opening O3 is aligned with the fourth opening O4. In the embodiment of FIG. 6, the number of the third opening O3 and the fourth opening O4 is both 4, and the number of connecting strips is 3. In some embodiments, the width of the third opening O3 and the fourth opening O4 may be the same as the distance b. In the embodiment of FIG. 6 , the widths of the third opening O3 and the fourth opening O4 are respectively a distance b, and the third opening O3 can be connected to the fourth opening O4.

In some embodiments, the connection bar openings OC1, OC2, OC3 can be respectively arranged in the three connection bars C1, C2, C3 to further increase the surface current. In some embodiments, the number of the connection bar openings OC1, OC2, OC3 is not particularly limited and can be set according to actual needs, for example, they can be the same as or different from the number of the first opening O1. In the embodiment of FIG. 6, the number of the connection bar openings OC1, OC2, OC3 is the same as the number of the first opening O1, which is 3.

In some embodiments, the first opening O1 is aligned with the connecting bar openings OC1, OC2 and OC3. That is, the first opening O1 can be connected to the second opening O2 through the connecting bar openings OC1, OC2 and OC3. The first opening O1 has a first opening width a1, and the connecting bar openings OC1 and OC2 of the connecting bars C1 and C2 can have connecting bar opening widths a2 and a3. In the embodiment of FIG. 6, the first opening width a1 is the same as the connecting bar opening widths a2 and a3.

Next, please refer to FIG. 7, which is similar to FIG. 6, except that the number of first openings O1 of the first side E1 of the well area 300 is greater than the number of connecting bar openings OC1 of the connecting bar C1, and also greater than the number of connecting bar openings OC2 of the connecting bar C2. For example, in the embodiment of FIG. 7, the number of first openings O1, the number of connecting bar openings OC1, and the number of connecting bar openings OC2 are 3, 2, and 1, respectively.

In some embodiments, the first opening O1 is aligned with the connecting bar opening OC1, but is offset from the connecting bar opening OC2. That is, one first opening O1 overlaps with the connecting bar opening OC1 in the first direction Y, but does not overlap with the connecting bar opening OC2. In other words, one first opening O1 reaches the side wall of the connecting bar C2 via the connecting bar opening OC1.

Next, please refer to FIG. 8, which is similar to FIG. 6, except that the number of first openings O1 of the first side E1 of the well area 300 is less than the number of connecting bar openings OC1 of the connecting bar C1, and is also less than the number of connecting bar openings OC2 of the connecting bar C2. For example, in the embodiment of FIG. 8, the number of first openings O1, the number of connecting bar openings OC1, and the number of connecting bar openings OC2 are 1, 2, and 3, respectively.

In addition, the first opening width a1 is different from the connecting strip opening width a2 and the connecting strip opening width a3. In the embodiment of FIG. 8, the first opening width a1 is greater than the connecting strip opening width a2 and also greater than the connecting strip opening width a3 (ie, a1>a2>a3).

In some embodiments, the first opening O1 is staggered with the connecting bar opening OC1 and the connecting bar opening OC2. That is, the first opening O1 does not overlap with the connecting bar opening OC1 or the connecting bar opening OC2 in the first direction Y. In other words, the connecting bar opening OC1 is offset from the first opening O1 in the first direction Y.

Next, please refer to FIG. 9, which is similar to FIG. 2, except that the well area 300 is an octagon and includes two connecting strips C1 and C2. Specifically, the well area 300 includes a first side E1 extending in a first direction Y and a second side E2 opposite to the first side E1, and a third side E3 extending in a second direction X and a fourth side E4 opposite to the third side E3. The well area 300 further includes a fifth side E5 and a sixth side E6 connecting the first side E1, the third side E3 and the fourth side E4, and a seventh side E7 and an eighth side E8 connecting the second side E2, the third side E3 and the fourth side E4. In some embodiments, the fifth side E5 is parallel to the eighth side E8, and the sixth side E6 is parallel to the seventh side E7.

In summary, the embodiment of the present invention can suppress leakage current by setting a well region. Furthermore, the embodiment of the present invention uses a connecting strip in the well region to increase the surface current while suppressing leakage current. Moreover, the embodiment of the present invention further reduces the on-resistance (Ron) by setting an opening at the edge of the well region. Moreover, the embodiment of the present invention further increases the surface current and improves the breakdown voltage by having an opening width of approximately 0.05~3μm. In addition, the embodiment of the present invention provides multi-directional flow of current by setting openings on all sides of the well region. In addition, the embodiment of the present invention provides a Schottky contact interface by having a lower doping concentration in the high-pressure well near the well region than in the doping region, thereby further reducing the occurrence of leakage current.

The scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods, and steps from the disclosure of some embodiments of the present disclosure. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the aforementioned processes, machines, manufactures, material compositions, devices, methods, and steps. In addition, each patent application constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each patent application and embodiment.

Several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the perspectives of the embodiments disclosed herein. Those with ordinary knowledge in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the disclosure, and that they can make various changes, substitutions and replacements without violating the spirit and scope of the disclosure.

100: substrate 200: high pressure well 300: well area 400: doping area 500: dielectric layer 600: gate electrode 700: cathode electrode 800: anode electrode AA’, BB’: section line a, a1: first opening width a2, a3: connecting strip width b: distance C1, C2, C2: connecting strip D: maximum depth E1: first side E2: second side E3: third side E4: fourth side E5: fifth side E6: sixth side E7: seventh side E8: eighth side HG: (gate electrode) width HS1: minimum distance HS2: maximum distance L: box O1: first opening O2: second opening O3: third opening O4: fourth opening OC1, OC2, OC3: connection strip openings PW1: first side width PW2: second side width PW3: third side width PW4: fourth side width S1: Schottky contact surface S2: Ohm contact surface W: maximum width X: second direction Y: first direction Z: height direction

FIG. 1 is a top view showing a semiconductor structure according to some embodiments of the present invention. FIG. 2 is a top view showing a semiconductor structure having a gate electrode according to some embodiments of the present invention. FIG. 3 is a schematic cross-sectional view of the semiconductor structure along the section line AA' of FIG. 2. FIG. 4 is an enlarged schematic view of the box L in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor structure along the section line BB' of FIG. 2. FIG. 6 is a top view showing a semiconductor structure having a gate electrode according to other embodiments of the present invention. FIG. 7 is a top view showing a semiconductor structure having a gate electrode according to other embodiments of the present invention. FIG. 8 is a top view showing a semiconductor structure having a gate electrode according to still other embodiments of the present invention. FIG. 9 is a top view showing a semiconductor structure having a gate electrode according to still other embodiments of the present invention.

100: Substrate

200: High-pressure well

300: Well area

400: Mixed area

a: First opening width

b: Distance

C1,C2,C3: Connecting strips

E1: First side

E2: Second side

E3: The third side

E4: The fourth side

O1: First opening

O2: Second opening

PW1: First side width

PW2: Second side width

PW3: Third side width

PW4: Fourth side width

X: Second direction

Y: First direction

Claims (19)

A semiconductor structure comprises: a substrate; a high-pressure well disposed in the substrate, wherein the high-pressure well has a first conductivity type; and a well region disposed in the high-pressure well, wherein the well region has a second conductivity type different from the first conductivity type; wherein in a top view, a first side of the well region extends along a first direction and has at least one first opening, wherein the at least one first opening has a first opening width, the first side has a first side width, wherein the at least one first opening exposes the high-pressure well below. A semiconductor structure as claimed in claim 1, wherein in the top view, the well region further includes: a second side relative to the first side, which has at least one second opening corresponding to the at least one first opening. A semiconductor structure as claimed in claim 1, wherein in the top view, the well region further includes: a third side and a fourth side adjacent to the first side, wherein the third side and the fourth side extend along a second direction perpendicular to the first direction, respectively. The semiconductor structure of claim 3 further includes: at least one connecting strip connecting the third side and the fourth side. A semiconductor structure as claimed in claim 4, wherein the at least one connecting strip has a connecting strip opening corresponding to the first opening, which has a connecting strip opening width that is the same as the first opening width. A semiconductor structure as claimed in claim 4, wherein the at least one connecting strip has a connecting strip opening having a connecting strip opening width different from the first opening width. A semiconductor structure as claimed in claim 4, wherein the at least one connecting strip has a connecting strip opening offset from the first opening in the first direction. As in claim 4, the semiconductor structure, wherein the at least one connecting strip is separated from the first side by a distance, and the ratio of the distance to the width of the first side is 0.1-1. A semiconductor structure as claimed in claim 1, wherein in the top view, the well region further includes: a third side and a fourth side adjacent to the first side, each having at least one third opening and at least one fourth opening. A semiconductor structure as claimed in claim 1, wherein the first opening width is 0.05-3μm. The semiconductor structure of claim 1 further includes a gate electrode, wherein in the top view, the gate electrode surrounds the well region and covers a portion of the edge of the well region. The semiconductor structure of claim 1 further includes: an anode electrode disposed on the well region, wherein a Schottky contact interface is provided between the anode electrode and the well region. The semiconductor structure of claim 1 further includes: a cathode electrode disposed on the high-voltage well and a doped region disposed between the high-voltage well and the cathode electrode, wherein an ohmic contact interface is provided between the cathode electrode and the doped region. The semiconductor structure of claim 1, wherein in the top view, the well region is square, rectangular, trapezoidal, hexagonal, or octagonal. A semiconductor structure includes: a substrate; a high-pressure well disposed in the substrate, wherein the high-pressure well has a first conductivity type; a plurality of well regions disposed in the high-pressure well, wherein the plurality of well regions have a second conductivity type different from the first conductivity type, wherein the plurality of well regions are spaced apart from each other; and a doped region disposed outside the plurality of well regions, wherein the doped region has the first conductivity type. The semiconductor structure of claim 15 further includes: a pair of gate electrodes disposed on a pair of outermost well regions among the plurality of well regions. A semiconductor structure as claimed in claim 15, wherein the outermost well region among the plurality of well regions has a top surface that gradually rises from the outermost side to the innermost side. As in claim 15, the plurality of well regions are separated from each other by a distance of 0.5 to 2.5 μm. A semiconductor structure as claimed in claim 15, wherein each of the plurality of well regions has a maximum depth and a maximum width, and the aspect ratio calculated by the maximum depth and the maximum width is 0.5 to 2.

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