TWI862946B - Pixel circuit, OLED display device and information processing device - Google Patents

Abstract

The present invention mainly discloses a pixel circuit, which is used to form an OLED pixel unit with an OLED element, and includes: a data driving unit, a storage capacitor, a first switch unit, and a second switch unit, wherein the data driving unit is coupled to the capacitor, the first switch unit, and the second switch unit. In particular, the present invention uses six TFT elements to form the data driving unit, uses an LTPO TFT element as the first switch unit, and uses another LTPO TFT element as the second switch unit. According to this design, the pixel circuit of the present invention can improve the phenomenon of uneven screen display caused by inconsistent Vth voltage. At the same time, in the low refresh stage, the present invention ensures the brightness uniformity and stability of the screen display by coordinating the reset voltage change and adjusting the duty cycle of the light control signal.

Description

Pixel circuit, OLED display device and information processing device

The present invention relates to the technical field of OLED display devices, and in particular to a pixel circuit that is used together with an OLED element to form a pixel unit.

It is known that flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays. Liquid crystal displays are a type of non-self-luminous flat panel displays that have been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays that are currently in mainstream applications.

FIG1 is a block diagram of a known OLED display. As shown in FIG1 , the structure of the OLED display 1a mainly includes: an OLED display panel 11a and at least one display driver chip 12a, wherein the OLED display panel 11a includes M×N OLED pixel units, and each of the OLED pixel units is composed of a pixel circuit 111a and an OLED element 112a.

In recent years, indium gallium zinc oxide (IGZO) thin film transistor (TFT) and low temperature polysilicon (LTPS) thin film transistor are widely used to form the pixel circuit 111a. In more detail, LTPS TFT elements have advantages such as high carrier mobility (~ ^100cm2 /V.s) and high stability, but due to high manufacturing costs, they are mainly used in medium and small sized OLED display panels 11a. At present, for mobile electronic devices such as smart phones, smart watches and tablet computers, low power consumption is always the most important. Practical experience shows that low frame rate operation can effectively reduce the power consumption of OLED display 1a. Unfortunately, LTPS TFT elements generally have a high off-current, thereby limiting the lower limit of the frame rate of the OLED display 1a including the pixel circuit 111a formed using the LTPS TFT elements.

On the other hand, IGZO TFT elements have good uniformity and good mobility (10~ ^50cm2 /V.s), so they are suitable for large-sized OLED display panels 11a. Although the stability and mobility of IGZO TFT elements are not high enough, they still have unique element characteristics, that is, the cut-off current is very low. Therefore, a new thin film transistor combining the advantages of LTPS TFT and IGZO TFT was proposed and named Low Temperature Polycrystalline Oxide (LTPO) thin film transistor. For example, Chinese Patent Publication No. CN113192458A discloses a pixel circuit composed of LTPS TFT elements and LTPO TFT elements. In low refresh rate applications such as 1 Hz (i.e., refresh once every 1 second) or even lower than 0.1 Hz (i.e., refresh once every 10 seconds), the pixel circuit ensures that the storage capacitor can stably maintain the voltage value during the data writing stage.

Unfortunately, the known pixel circuit 111a still has the problem of uneven brightness of the OLED element 112a caused by the difference in threshold voltage, which eventually causes the so-called Mura phenomenon in some blocks of the OLED display panel 11a. On the other hand, practical experience shows that due to the hysteresis effect of the TFT element of the pixel circuit 111a, the OLED display panel 11a may have a short-term afterimage phenomenon. After the short-term afterimage phenomenon occurs, the display screen of the OLED display panel 11a needs a certain amount of time to return to normal. Unfortunately, the pixel circuit of the known technology cannot solve the problem of short-term afterimage phenomenon.

From the above description, it can be seen that a new type of pixel circuit is urgently needed in this field.

The main purpose of the present invention is to provide a pixel circuit for forming an OLED pixel unit with an OLED element, and M×N OLED pixel units form an OLED panel. The pixel circuit of the present invention adopts an 8T1C architecture, which can compensate for the difference in threshold voltage between the 8 TFT elements, so that each OLED element emits light with uniform brightness, ensuring that the OLED display panel will not have the so-called Mura phenomenon during the image display process. In addition, the 8 TFT elements include 6 LTPS TFT elements and 6 LTPO TFT elements, so the pixel circuit of the present invention can improve the short-term residual image of the OLED display panel during the initialization stage. At the same time, in the low refresh stage, the present invention ensures the brightness uniformity and stability of the screen display by coordinating the reset voltage change and adjusting the duty cycle of the light control signal.

To achieve the above-mentioned object, the present invention proposes an embodiment of the pixel circuit, which includes: a data driving unit, having a first electrical terminal, a first control terminal, a second control terminal, a second electrical terminal, a third electrical terminal, a third control terminal, a fourth control terminal, a fourth electrical terminal, a fifth electrical terminal, a sixth electrical terminal, and a fifth control terminal, wherein the first electrical terminal is coupled to a first driving voltage, the first control terminal is coupled to a light-emitting control signal, the second control terminal is coupled to a first gate control signal, the second electrical terminal is coupled to a display data signal, the third electrical terminal is coupled to a first reset signal, the third control terminal is coupled to the light-emitting control signal, the fourth control terminal is coupled to a second gate control signal, the fourth electrical terminal is coupled to a second reset signal, and the fifth electrical terminal is used to couple to an OLED element; a storage capacitor having a first end and a second end, wherein the first end is coupled to a first common point between the first electrical end of the data drive unit and the first drive voltage, and the second end is coupled to the fifth control end of the data drive unit; a first switch unit having a control end, a first end and a second end, wherein the control end is coupled to a third gate control signal, and the first end is coupled to the A second common point between the fifth control terminal of the data driving unit 1D and the second terminal of the storage capacitor, and the second terminal is coupled to the sixth electrical terminal of the data driving unit; and a second switch unit, which also has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a fourth gate control signal, the first terminal is coupled to the second common point, and the second terminal is coupled to a third reset signal.

In one embodiment, the first switch unit includes a first TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the first switch unit.

In one embodiment, the second switch unit includes a second TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the second switch unit.

In one embodiment, the data drive unit includes: a third TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fourth control terminal of the data drive unit, and the second electrical terminal serves as the third electrical terminal of the data drive unit; a fourth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the second control terminal of the data drive unit, and the first electrical terminal serves as the third electrical terminal of the data drive unit; as the second electrical terminal of the data drive unit, and the second electrical terminal is coupled to the first electrical terminal of the third TFT element; a fifth TFT element, which has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal of the data drive unit, the second electrical terminal serves as the sixth electrical terminal of the data drive unit, and the first electrical terminal is coupled to the second electrical terminal of the fourth TFT element and the first electrical terminal of the third TFT element. a third common point between the first and second electrical terminals; a sixth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the first control terminal of the data drive unit, the first electrical terminal serves as the first electrical terminal of the data drive unit, and the second electrical terminal is coupled to the third common point; a seventh TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the first control terminal of the data drive unit, the first electrical terminal serves as the first electrical terminal of the data drive unit, and the second electrical terminal is coupled to the third common point; A third control terminal, the second electrical terminal serving as the fifth electrical terminal of the data drive unit, and the first electrical terminal coupled to the second electrical terminal of the fifth TFT element; and an eighth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal is coupled to the gate terminal of the third TFT element, the first electrical terminal serving as the fourth electrical terminal of the data drive unit, and the second electrical terminal coupled to the second electrical terminal of the seventh TFT element.

The present invention also provides an OLED display device, which includes a display driver circuit and an OLED display panel, wherein the OLED display panel includes M×N pixel units, and each pixel unit is composed of a pixel circuit and an OLED element; the pixel circuit includes: a data driver unit having a first electrical terminal, a first control terminal, a second control terminal, a second electrical terminal, a third electrical terminal, a third control terminal The first control terminal is coupled to a first driving voltage, the first control terminal is coupled to a light-emitting control signal, the second control terminal is coupled to a first gate control signal, the second control terminal is coupled to a display data signal, the third control terminal is coupled to a first reset signal, the third control terminal is coupled to the light-emitting control signal, the fourth control terminal is coupled to a second gate control signal, a control signal, the fourth electrical terminal is coupled to a second reset signal, and the fifth electrical terminal is used to couple to an OLED element; a storage capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to a first common point between the first electrical terminal of the data drive unit and the first drive voltage, and the second terminal is coupled to the fifth control terminal of the data drive unit; a first switch unit, having a control terminal, a first terminal and a second terminal, wherein the control terminal A third gate control signal is coupled, the first end is coupled to a second common point between the fifth control end of the data drive unit 1D and the second end of the storage capacitor, and the second end is coupled to the sixth electrical terminal of the data drive unit; and a second switch unit, which also has a control end, a first end and a second end, wherein the control end is coupled to a fourth gate control signal, the first end is coupled to the second common point, and the second end is coupled to a third reset signal.

In one embodiment, the first switch unit includes a first TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the first switch unit.

In one embodiment, the second switch unit includes a second TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the second switch unit.

In one embodiment, the data drive unit includes: a third TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fourth control terminal of the data drive unit, and the second electrical terminal serves as the third electrical terminal of the data drive unit; a fourth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the second control terminal of the data drive unit, and the first electrical terminal serves as the third electrical terminal of the data drive unit; as the second electrical terminal of the data-driven unit, and the second electrical terminal is coupled to the first electrical terminal of the third TFT element; a fifth TFT element, which has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal of the data-driven unit, the second electrical terminal serves as the sixth electrical terminal of the data-driven unit, and the first electrical terminal is coupled to the second electrical terminal of the fourth TFT element and the first electrical terminal of the third TFT element. a third common point between the first and second electrical terminals; a sixth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the first control terminal of the data drive unit, the first electrical terminal serves as the first electrical terminal of the data drive unit, and the second electrical terminal is coupled to the third common point; a seventh TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the first control terminal of the data drive unit, the first electrical terminal serves as the first electrical terminal of the data drive unit, and the second electrical terminal is coupled to the third common point; A third control terminal, the second electrical terminal serving as the fifth electrical terminal of the data drive unit, and the first electrical terminal coupled to the second electrical terminal of the fifth TFT element; and an eighth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal is coupled to the gate terminal of the third TFT element, the first electrical terminal serving as the fourth electrical terminal of the data drive unit, and the second electrical terminal coupled to the second electrical terminal of the seventh TFT element.

The present invention also provides an information processing device having the OLED display device of the present invention as described above.

In one embodiment, the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

1a:OLED display

11a: OLED display panel

111a: Pixel circuit

112a: OLED element

12a: Display driver chip

1:OLED display device

11: OLED display panel

111: Pixel circuit

112: OLED components

12: Display driver chip

1D: Data drive unit

Cst: Storage capacitor

S1: First switch unit

S2: Second switch unit

1DT1: First end

1DT2: Second terminal

1DT3: The third terminal

1DT4: Fourth terminal

1DT5: Fifth terminal

1DT6: Sixth terminal

1DC1: First control terminal

1DC2: Second control terminal

1DC3: The third control terminal

1DC4: Fourth control terminal

1DC5: Fifth control terminal

M1: first TFT element

M2: Second TFT element

M3: The third TFT element

M4: the fourth TFT element

M5: Fifth TFT element

M6: Sixth TFT element

M7: Seventh TFT element

M8: The eighth TFT element

FIG. 1 is a block diagram of a known OLED display; FIG. 2 is a block diagram of an OLED display device including a pixel circuit of the present invention; FIG. 3 is a circuit topology diagram of a pixel circuit of the present invention; and FIG. 4 is a working timing diagram of multiple signals used to control the pixel circuit of the present invention.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

The present invention provides a pixel circuit for forming an OLED pixel unit with an OLED element, and M×N OLED pixel units form an OLED panel. The pixel circuit of the present invention adopts an 8T1C architecture, which can compensate for the difference in threshold voltage between 8 TFT elements, so that each OLED element emits light with uniform brightness, ensuring that the OLED display panel will not have the so-called Mura phenomenon during the image display process. In addition, the 8 TFT elements include 6 LTPS TFT elements and 6 LTPO TFT elements, so the pixel circuit of the present invention can improve the short-term residual image of the OLED display panel during the initialization stage.

FIG2 is a block diagram of an OLED display device including a pixel circuit of the present invention. As shown in FIG2, the structure of the OLED display device 1 mainly includes: an OLED display panel 11 and at least one display driver chip 12, wherein the OLED display panel 11 includes M×N OLED pixel units, and each of the OLED pixel units is composed of an OLED element 112 and a pixel circuit 111 of the present invention. FIG3 is a circuit topology diagram of a pixel circuit of the present invention. As shown in FIG3, the pixel circuit 111 of the present invention mainly includes: a data driver unit 1D, a storage capacitor Cst, a first switch unit S1, and a second switch unit S2.

As shown in FIG3 , the data driving unit 1D has a first electrical terminal 1DT1, a first control terminal 1DC1, a second control terminal 1DC2, a second electrical terminal 1DT2, a third electrical terminal 1DT3, a third control terminal 1DC3, a fourth control terminal 1DC4, a fourth electrical terminal 1DT4, a fifth electrical terminal 1DT5, a sixth electrical terminal 1DT6, and a fifth control terminal 1DC5. According to the design of the present invention, the first electrical terminal 1DT1 is coupled to a first driving voltage ELVDD, the first control terminal 1DC1 is coupled to a light-emitting control signal EM(n), the second control terminal 1DC2 is coupled to a first gate control signal P_Gate(n), the second electrical terminal 1DT2 is coupled to a display data signal Data, the third electrical terminal 1DT3 is coupled to a first reset signal RES_P, the third control terminal 1DC3 is coupled to the light-emitting control signal EM(n), the fourth control terminal 1DC4 is coupled to a second gate control signal P_Gate(n-1), the fourth electrical terminal 1DT4 is coupled to a second reset signal RES_N, and the fifth electrical terminal 1DT5 is used to couple to an OLED element 112.

To explain in more detail, the storage capacitor Cst has a first terminal and a second terminal, wherein the first terminal is coupled to a first common point CN1 between the first electrical terminal 1DT1 of the data driving unit 1D and the first driving voltage ELVDD, and the second terminal is coupled to the fifth control terminal 1DC5 of the data driving unit 1D. On the other hand, the first switch unit S1 has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a third gate control signal N_Gate(n), the first terminal is coupled to a second common point CN2 between the fifth control terminal 1DC5 of the data driving unit 1D and the second terminal of the storage capacitor Cst, and the second terminal is coupled to the sixth electrical terminal 1DT6 of the data driving unit 1D. Furthermore, the second switch unit S2 also has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a fourth gate control signal N_Gate(n-1), the first terminal is coupled to the second common point CN2, and the second terminal is coupled to a third reset signal RES_X.

As shown in FIG3 , the first switch unit S1 includes a first TFT element M1, which has a gate terminal, a first element electrical terminal and a second element electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the first switch unit S1. On the other hand, the second switch unit S2 includes a second TFT element M2, which has a gate terminal, a first element electrical terminal and a second element electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the second switch unit S2. Electronic engineers familiar with the design and manufacture of LCD and/or OLED pixel circuits will certainly know that a TFT element is a symmetrical element, whose gate terminal is the element control terminal and whose two terminals are two electrical terminals, which are determined as a source terminal and a drain terminal according to the flow direction of the current. Simply put, when one electrical end is the source end, the other end is the drain end, and vice versa.

It is worth noting that the present invention uses low temperature polycrystalline oxide (LTPO) thin film transistors as the first TFT element M1 and the second TFT element M2. Further, according to FIG. 3 , the data drive unit 1D includes: a third TFT element M3, a fourth TFT element M4, a fifth TFT element M5, a sixth TFT element M6, a seventh TFT element M7, and an eighth TFT element M8. As shown in FIG. 3 , the third TFT element M3 has a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal serves as the fourth control terminal 1DC4 of the data drive unit 1D, and the second electrical terminal serves as the third electrical terminal 1DT3 of the data drive unit 1D. Furthermore, the fourth TFT element M4 has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the second control terminal 1DC2 of the data driving unit 1D, the first electrical terminal serves as the second electrical terminal 1DT2 of the data driving unit 1D, and the second electrical terminal is coupled to the first electrical terminal of the third TFT element M3. Furthermore, the fifth TFT element M5 has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal 1DC5 of the data driving unit 1D, the second electrical terminal serves as the sixth electrical terminal 1DT6 of the data driving unit 1D, and the first electrical terminal is coupled to a third common point CN3 between the second electrical terminal of the fourth TFT element M4 and the first electrical terminal of the third TFT element M3.

To explain in more detail, the sixth TFT element M6 has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the first control terminal 1DC1 of the data-driven unit 1D, the first electrical terminal serves as the first electrical terminal 1DT1 of the data-driven unit 1D, and the second electrical terminal is coupled to the third common point CN3. Furthermore, the seventh TFT element M7 has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the third control terminal 1DC3 of the data-driven unit 1D, the second electrical terminal serves as the fifth electrical terminal 1DT5 of the data-driven unit 1D, and the first electrical terminal is coupled to the second electrical terminal of the fifth TFT element M5. Furthermore, the eighth TFT element M8 has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal is coupled to the gate terminal of the third TFT element M3, the first electrical terminal serves as the fourth electrical terminal 1DT4 of the data driving unit 1D, and the second electrical terminal is coupled to the second electrical terminal of the seventh TFT element M7.

FIG4 is a working timing diagram of multiple signals used to control the pixel circuit of the present invention. As shown in FIG3 and FIG4, in the T1 stage, since the fourth gate control signal N_Gate(n-1) is at a high level, the second TFT element M2 is turned on, so that the third reset signal RES_X

The node N1 is reset. At the same time, the second gate control signal P_Gate(n-1) is at a low level, so the third TFT element M3 and the eighth TFT element M8 are turned on, so that the voltage of the first reset signal RES_P is transmitted to the node N2. In this case, the gate-source voltage V _GS of the fifth TFT element M5 = V _{RES _ X} - V _{RES _ P} , thus ensuring that before the voltage of the display data signal Data is written into the current frame, the fifth TFT elements M5 of all pixel circuits 111 have the same V _GS voltage, thereby improving the short-term residual image defects of the OLED panel 11 caused by the hysteresis effect of the TFT elements. It should be noted that the conduction of the eighth TFT element M8 enables the voltage of the second reset signal RES_N to complete the reset of the anode of the OLED element 112.

As shown in FIG. 3 and FIG. 4 , in the T2 stage, the first gate control signal P_Gate(n) is at a low level, so the fourth TFT element M4 is turned on, so that the voltage of the display data signal Data (i.e., Vdata) is transmitted to the node N2. At the same time, the third gate control signal N_Gate(n) is at a high level, so the first TFT element M1 is turned on, so that Vdata charges the storage capacitor Cst through the fourth TFT element M4, the fifth TFT element M5, and the first TFT element M1 until the node voltage of the node N1 is charged to Vdata+Vth_M5, where Vth_M5 is the threshold voltage of the fifth TFT element M5. When the node voltage of node N1 is equal to Vdata+Vth_M5, the fifth TFT element M5 is turned off, thereby stopping charging the storage capacitor Cst and completing the data voltage writing and Vth compensation.

Continuing to refer to FIG. 3 and FIG. 4 , in the T3 stage (i.e., the light emitting stage), the light emitting control signal EM(n) is at a low level, so the fifth TFT element M5, the sixth TFT element M6 and the seventh TFT element M7 are turned on, while the other TFT elements (M1 to M4, M8) are turned off, so that the OLED element 112 emits light in the T3 stage. Furthermore, according to the transistor saturation region current formula, the following mathematical operation can be performed:

From the above mathematical calculation results, it can be seen that Vth is offset, and the driving current of the OLED element 112 has nothing to do with Vth. Therefore, the pixel circuit 111 of the present invention can improve the phenomenon of uneven screen display caused by inconsistent Vth voltage. At the same time, the pixel circuit 111 of the present invention can improve the short-term afterimage of the OLED display panel during the initialization stage.

It is additionally explained that in FIG. 4 , the Active Frame is a valid data writing or updating stage within a frame, so that the storage capacitor Cst in each of the pixel circuits 111 of all rows of the OLED panel 11 completes the data updating action. On the other hand, the Skip Frame is a low refresh rate stage, and the data information of the storage capacitor Cst will not be updated in this stage but will continue to maintain the data value written in the Active Frame stage. Taking a 1Hz refresh rate as an example, the duration of the Skip Frame stage is 59 frames, and the Active Frame is 1 frame, so the data must be maintained for 59 frames and cannot change. If the data value changes, the screen will flicker.

In order to ensure that the display screen does not flicker during the Skip Frame stage, the pixel circuit 111 of the present invention is coupled to a third reset signal RES_X. In one embodiment, the voltage of the third reset signal RES_X is -3V during the Active Frame stage. Further, after entering the Skip Frame stage, as shown in FIG. 4 , the voltage of the third reset signal RES_X rises to 2V. At this time, since the fourth gate control signal is at a low level and its voltage is -6V (for closing the second TFT element M2), and the range of Vdata is generally 2~5V, it can be calculated that the VGS of the second TFT element M2 is -6V-2V=-8V. Obviously, the -8V voltage has a stronger closing degree for the second TFT element, making its leakage smaller, thereby ensuring that the storage capacitor Cst can stably maintain the data written in the Active Frame stage in the Skip Frame stage (i.e., the low refresh rate stage). At the same time, the voltage of the third reset signal RES_X is 2V in the Skip Frame stage, which is close to the white screen data voltage value, so it can ensure that the VDS voltage difference of the second TFT element M2 is smaller.

Although the leakage of the LTPO TFT element (i.e., the second TFT element M2) is very low, as the number of frames increases (time becomes longer), the voltage of the second TFT element M2 still changes during the Skip Frame stage. Practical experience shows that if the data written into the storage capacitor during the Active frame stage is Vdata data close to the black screen, once the data changes during the Skip Frame stage, the human eye feedback is very sensitive. For example, if the Vdata data of the black screen is 5V, if it is reduced to 4.9V, the result reflected in the brightness of the screen is that it becomes brighter, which is easy to produce flickering and be noticed by the human eye.

Therefore, the difference in brightness can be compensated by changing the luminance modulation signal EM(n). As shown in FIG4 , when the Skip Frame reaches the 2Nth frame, the duty cycle of the luminance modulation signal EM(n) can be adjusted (i.e., the high-level width is extended by a time) to offset the increase in screen brightness caused by leakage of the LTPO TFT element (i.e., the second TFT element M2) when the low-brightness screen is displayed. As the number of frames increases (such as when it reaches the XN Frame), the high-level width can be further extended by b time (b>a) to adjust the duty cycle of the luminance modulation signal EM(n), thereby offsetting the further increase in the brightness of the low-brightness screen, thereby ensuring the effect and quality of the screen display. On the contrary, if the brightness of the picture becomes darker as the number of frames increases, the brightness loss when displaying low-brightness pictures can be improved by adjusting the duty cycle of the luminance modulation signal EM(n) (i.e., shortening the high-level width by a time). Moreover, when the number of frames increases (such as when it reaches XN Frame), the high-level width can be further shortened by b time (b>a) to adjust the duty cycle of the luminance modulation signal EM(n), thereby offsetting the brightness loss of low-brightness pictures and ensuring the effect and quality of picture display.

Thus, the above has completely and clearly described a pixel circuit of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a pixel circuit for forming an OLED pixel unit with an OLED element, comprising: a data driving unit, a storage capacitor, a first switch unit, and a second switch unit, wherein the data driving unit is coupled to the capacitor, the first switch unit, and the second switch unit. In particular, the present invention uses six TFT elements to form the data driving unit, uses an LTPO TFT element as the first switch unit, and uses another LTPO TFT element as the second switch unit. According to this design, the pixel circuit of the present invention can improve the uneven display phenomenon caused by inconsistent Vth voltage. The pixel circuit of the present invention can improve the short-term afterimage of the OLED display panel during the initialization stage. At the same time, in the low refresh stage, the present invention ensures the brightness uniformity and stability of the screen display by coordinating the reset voltage change and adjusting the duty cycle of the light control signal.

(2) The present invention also provides an OLED display device, which includes at least one display driving circuit and an OLED display panel, wherein the OLED display panel includes M×N OLED pixel units, and is characterized in that each of the OLED pixel units is composed of an OLED element and a pixel circuit of the present invention.

(3) The present invention also provides an information processing device having the OLED display device of the present invention as described above. Furthermore, the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are different from the known technology, and it is the first invention that is practical and meets the patent requirements for invention. We sincerely ask the review committee to examine it and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

111: Pixel circuit

112: OLED components

1D: Data drive unit

Cst: Storage capacitor

S1: First switch unit

S2: Second switch unit

1DT1: First end

1DT2: Second terminal

1DT3: The third terminal

1DT4: Fourth terminal

1DT5: Fifth terminal

1DT6: Sixth terminal

1DC1: First control terminal

1DC2: Second control terminal

1DC3: The third control terminal

1DC4: Fourth control terminal

1DC5: Fifth control terminal

M1: first TFT element

M2: Second TFT element

M3: The third TFT element

M4: the fourth TFT element

M5: Fifth TFT element

M6: Sixth TFT element

M7: Seventh TFT element

M8: The eighth TFT element

Claims (10)

A pixel circuit includes: a first switch unit, including a first TFT element, and the first TFT element has a gate terminal, a first element electrical terminal and a second element electrical terminal; a second switch unit, including a second TFT element, and the second TFT element also has a gate terminal, a first element electrical terminal and a second element electrical terminal; a data drive unit, composed of a third TFT element, a fourth TFT element, a fifth TFT element, a sixth TFT element, a seventh TFT element, and an eighth TFT element, and having a first electrical terminal coupled to a first driving voltage, a second electrical terminal coupled to a display data signal, a third electrical terminal coupled to a first reset signal, and a third electrical terminal coupled to a second reset signal. a fourth electrical terminal coupled to a signal, a fifth electrical terminal coupled to an OLED element, a first control terminal coupled to a light-emitting control signal, a second control terminal coupled to a first gate control signal, a third control terminal coupled to the light-emitting control signal, a fourth control terminal coupled to a second gate control signal, a sixth electrical terminal, and a fifth control terminal; and a storage capacitor having a first terminal and a second terminal respectively coupled to the first electrical terminal and the fifth control terminal of the data-driving unit; wherein the third TFT element, the fourth TFT element, the fifth TFT element, the sixth TFT element, the seventh TFT element, and the eighth TFT element all have a gate terminal, a first element electrical terminal, and a second element electrical terminal; wherein the sixth TFT element, the fifth TFT element and the seventh TFT element are stacked, the fourth TFT element is coupled to a first stacking point between the sixth TFT element and the fifth TFT element at its second element electrical end, and the eighth TFT element is coupled to a common point between the second element electrical end of the seventh TFT element and the OLED element at its second element electrical end; wherein the third TFT element is coupled to the second element electrical end of the fourth TFT element at its first element electrical end, and is coupled to the gate end of the eighth TFT element at its gate end; wherein the first TFT element is coupled to a third gate control signal, the sixth electrical end and the gate end at its gate end, the first element electrical end and the second element electrical end, respectively; The fifth control terminal, and the second TFT element is coupled with a fourth gate control signal, the fifth control terminal and a third reset signal by its gate terminal, the first element electrical terminal and the second element electrical terminal; wherein the first element electrical terminal and the gate terminal of the sixth TFT element are respectively used as the first electrical terminal and the first control terminal, the first element electrical terminal and the gate terminal of the fourth TFT element are respectively used as the second electrical terminal and the second control terminal, the first element electrical terminal of the third TFT element is used as the third electrical terminal, the second element electrical terminal and the gate terminal of the seventh TFT element are respectively used as the fifth electrical terminal and the third control terminal, and the first element electrical terminal and the gate terminal of the eighth TFT element are respectively used as the fourth electrical terminal and the fourth control terminal. A pixel circuit as described in claim 1, wherein, in an active display frame, the fourth gate control signal and the second gate control signal are respectively at a high level and a low level in a first time period. The pixel circuit as described in claim 2, wherein, in the effective display frame, the first gate control signal and the third gate control signal are respectively at a low level and a high level in a second time interval following the first time interval. The pixel circuit as described in claim 3, wherein, in the effective display frame, the first gate control signal and the second gate control signal are both high level in a third time interval following the second time interval, and the third gate control signal and the fourth gate control signal are both low level in the third time interval. An OLED display device includes a display driving circuit and an OLED display panel, wherein the OLED display panel includes M×N pixel units, and each of the pixel units is composed of a pixel electrode and an OLED element; the pixel circuit includes: a first switch unit, including a first TFT element, and the first TFT element has a gate terminal, a first element electrical terminal and a second element electrical terminal; a second switch unit, including a second TFT element, and the second TFT element also has a gate terminal, a first element electrical terminal and a second element electrical terminal; a data driving unit, composed of a third TFT element, a fourth TFT element, a fifth TFT element, a sixth TFT element, a seventh TFT element, and an eighth TFT element; The data driving unit comprises a first electrical terminal coupled to a first driving voltage, a second electrical terminal coupled to a display data signal, a third electrical terminal coupled to a first reset signal, a fourth electrical terminal coupled to a second reset signal, a fifth electrical terminal coupled to an OLED element, a first control terminal coupled to a light-emitting control signal, a second control terminal coupled to a first gate control signal, a third control terminal coupled to the light-emitting control signal, a fourth control terminal coupled to a second gate control signal, a sixth electrical terminal, and a fifth control terminal; and a storage capacitor having a first terminal and a second terminal respectively coupled to the first electrical terminal and the fifth control terminal of the data driving unit; wherein the third TFT element, the fourth TFT element, the fifth TFT element, the sixth TFT element, the seventh TFT element The TFT element and the eighth TFT element each have a gate terminal, a first element electrical terminal and a second element electrical terminal; wherein the sixth TFT element, the fifth TFT element and the seventh TFT element are stacked, the fourth TFT element is coupled to a first stacking point between the sixth TFT element and the fifth TFT element with its second element electrical terminal, and the eighth TFT element is coupled to a common point between the second element electrical terminal of the seventh TFT element and the OLED element with its second element electrical terminal; wherein the third TFT element is coupled to the second element electrical terminal of the fourth TFT element with its first element electrical terminal, and is coupled to the gate terminal of the eighth TFT element with its gate terminal, the first element electrical terminal and the second element electrical terminal; wherein the first TFT element is coupled to the gate terminal of the eighth TFT element with its gate terminal, the first element electrical terminal and the second element electrical terminal; wherein the fourth TFT element is coupled to a first stacking point between the sixth TFT element and the fifth TFT element with its second element electrical terminal, and the eighth TFT element is coupled to a common point between the second element electrical terminal of the seventh TFT element and the OLED element with its second element electrical terminal; wherein the third TFT element is coupled to the second element electrical terminal of the fourth TFT element with its first element electrical terminal, and is coupled to the gate terminal of the eighth TFT element with its gate terminal, the first element electrical terminal and the second element electrical terminal; wherein the fourth TFT element is coupled to a first stacking point between the sixth TFT element and the fifth TFT element with its ... fifth TFT element is coupled to a first stacking point between the sixth TFT element and the fifth TFT element with its second element electrical terminal. The first element electrical terminal and the gate terminal of the second TFT element are respectively coupled to a third gate control signal, the sixth electrical terminal and the fifth control terminal, and the second TFT element is respectively coupled to a fourth gate control signal, the fifth control terminal and a third reset signal through its gate terminal, the first element electrical terminal and the second element electrical terminal; wherein the first element electrical terminal and the gate terminal of the sixth TFT element are respectively used as the first electrical terminal and the first control terminal, the first element electrical terminal and the gate terminal of the fourth TFT element are respectively used as the second electrical terminal and the second control terminal, the first element electrical terminal of the third TFT element is respectively used as the third electrical terminal, the second element electrical terminal and the gate terminal of the seventh TFT element are respectively used as the fifth electrical terminal and the third control terminal, and the first element electrical terminal and the gate terminal of the eighth TFT element are respectively used as the fourth electrical terminal and the fourth control terminal. An OLED display device as described in claim 5, wherein, in an active display frame, the fourth gate control signal and the second gate control signal are respectively at a high level and a low level in a first time period. The OLED display device as described in claim 6, wherein, in the effective display frame, the first gate control signal and the third gate control signal are respectively at a low level and a high level in a second time interval following the first time interval. An OLED display device as described in claim 7, wherein, in the effective display frame, the first gate control signal and the second gate control signal are both high level in a third time interval following the second time interval, and the third gate control signal and the fourth gate control signal are both low level in the third time interval. An information processing device, characterized in that it has at least one OLED display device as described in any one of claim 5 to claim 8. The information processing device as described in claim 9, wherein the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

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