TWI862101B - Semiconductor package and fabricating method thereof - Google Patents

Abstract

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Description

Semiconductor package and method for manufacturing the same

The present invention relates to a semiconductor package and a method of manufacturing a semiconductor package. CROSS-REFERENCE TO RELATED APPLICATIONS / INCORPORATED BY REFERENCE

This application is a continuation-in-part of U.S. Patent Application No. 15/707,646, filed on September 18, 2017, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” which is a continuation-in-part of U.S. Patent Application No. 15/594,313, filed on May 12, 2017, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” which is a continuation-in-part of U.S. Patent Application No. 15/594,313, filed on July 11, 2016 ... METHOD THEREOF" (now U.S. Patent No. 9,653,428), U.S. Patent Application No. 15/207,186 cited "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD" filed on January 27, 2016 THEREOF)", each of which is hereby incorporated by reference in its entirety.

This application is related to U.S. Patent Application No. 14/686,725, filed on April 14, 2015, entitled “SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH”; U.S. Patent Application No. 14/823,689, filed on August 11, 2015 (now U.S. Patent Application No. 9,543,242), entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”; U.S. Patent Application No. 14/823,689, filed on August 11, 2015, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF ..., entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”; U.S. Patent Application No. 14/823,689, filed on August 11, 2015, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”; U.S. Patent Application No. 14/823,689, filed on August 11, 2015, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD and U.S. Patent Application No. 15/400,041, filed on March 10, 2016, entitled “SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF,” each of which is hereby incorporated by reference in its entirety.

Current semiconductor packages and methods for forming semiconductor packages are inadequate, for example resulting in excessive cost, reduced reliability, or excessive package size. Further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure as described in the remainder of this application with reference to the accompanying drawings.

Various aspects of the present disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present disclosure provide various semiconductor package structures and methods for manufacturing the same, the semiconductor package structure including a connection die that sends electrical signals along specific routes between multiple other semiconductor dies.

The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of the various aspects of the present disclosure is not necessarily limited by any particular features of the examples provided. In the following discussion, the terms "for example" and "exemplary" are non-limiting and are generally synonymous with "by way of example and not limitation," "for example and not limitation," etc.

As used herein, "and/or" refers to any one or more items in a list connected by "and/or". For example, "x and/or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and/or y" means "one or both of x and y". As another example, "x, y, and/or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y, and/or z" means "one or more of x, y, and z".

The terms used herein are for the purpose of describing specific examples only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that the terms "include", "comprising", "having", etc., when used in this specification, indicate the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part. Similarly, various spatial terms, such as "upper," "lower," "side," etc., may be used to distinguish one element from another in a relative manner. However, it should be understood that components may be oriented in different ways, for example, without departing from the teachings of this disclosure, a semiconductor device or package may be turned sideways so that its "top" surface faces horizontally and its "side" surface faces vertically.

Various aspects of the present disclosure provide a semiconductor device or package and a method of manufacturing the same that can reduce cost, increase reliability and/or improve the manufacturability of the semiconductor device or package.

The above and other aspects of the present disclosure will be described in the following description of various example embodiments and will be apparent from the following description of various example embodiments. Various aspects of the present disclosure will now be presented with reference to the accompanying drawings so that those skilled in the art can easily practice various aspects.

FIG. 1 shows a flow chart of an example method 100 for manufacturing an electronic device (e.g., a semiconductor package, etc.). Example method 100 may, for example, share any or all features with any other example method discussed herein (e.g., example method 300 of FIG. 3 , example method 500 of FIG. 5 , example method 700 of FIG. 7 , etc.). The cross-sectional views shown in FIGS. 2A to 2Q show example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices in various aspects according to the present disclosure. FIGS. 2A to 2Q may, for example, show example electronic devices with the blocks (or steps) of method 100 of FIG. 1 . FIG. 1 and FIGS. 2A to 2Q will now be discussed together. It should be noted that the order of the example blocks of method 100 may be varied without departing from the scope of the present disclosure.

Example method 100 may begin execution at block 105. Method 100 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, when parts and/or manufacturing materials used during the execution of method 100 arrive, method 100 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. For another example, method 100 may begin execution in response to an operator command to start. In addition, for example, method 100 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

The example method 100 may include receiving, manufacturing, and/or preparing a plurality of functional dies at block 110. Block 110 may include receiving, manufacturing, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 110 may share any or all features with any of the functional die receiving, manufacturing, and/or preparing operations discussed herein. Various example aspects of block 110 are presented in FIG. 2A.

Block 110 may, for example, include receiving multiple functional dies (or any portion thereof) from an upstream manufacturing process at the same facility or geographic location. Block 110 may also, for example, include receiving a functional die (or any portion thereof) from a supplier (eg, from a foundry, etc.).

The received, manufactured and/or prepared functional die may include any of a variety of features. For example, although not shown, the received die may include multiple different die on the same wafer (e.g., a multi-project wafer (MPW)). An example of such a configuration is shown in example 210A of FIG. 2A of U.S. Patent Application No. 15/594,313, which is hereby incorporated by reference in its entirety for all purposes. In such an MPW configuration, the wafer may include multiple different types of functional die. For example, a first die may include a processor, and a second die may include a memory chip. For another example, a first die may include a processor, and a second die may include a co-processor. In addition, for example, both the first die and the second die may include a memory chip. Typically, the die may include an active semiconductor circuit. Although the various examples presented herein typically place or attach singulated functional dies, such dies may also be connected to each other prior to placement (eg, as part of the same semiconductor wafer, as part of a reconstituted wafer, etc.).

Block 110 may, for example, include receiving functional die in one or more corresponding wafers dedicated to a single type of die. For example, as shown in FIG. 2A , example 200A-1 illustrates a wafer of a whole wafer dedicated to die 1, an example die of which is shown by element symbol 211, and example wafer 200A-3 illustrates a wafer of a whole wafer dedicated to die 2, an example die of which is shown by element symbol 212. It should be understood that although the various examples shown herein generally involve first and second functional die (e.g., die 1 and die 2), the scope of the present disclosure extends to any number of functional die of the same or different types (e.g., three die, four die, etc.). For example, in addition to or in lieu of functional semiconductor die, the scope of the present disclosure also extends to passive electronic components (e.g., resistors, capacitors, inductors, etc.).

Functional die 211 and 212 may include die interconnect structures. For example, as shown in FIG. 2A , the first functional die 211 includes a first set of one or more die interconnect structures 213, and a second set of one or more die interconnect structures 214. Similarly, the second functional die 212 may include such structures. The die interconnect structures 213 and 214 may include any of a variety of die interconnect structure features, non-limiting examples of which are provided herein.

The first die interconnect structure 213 may include, for example, a metal (eg, copper, aluminum, etc.) pillar or land. The first die interconnect structure 213 may also include, for example, a conductive bump (eg, C4 bump, etc.) or ball, lead, pillar, etc.

The first die interconnect structure 213 may be formed in any of a variety of ways. For example, the first die interconnect structure 213 may be plated on a die pad of the functional die 211. For another example, the first die interconnect structure 213 may be printed and reflowed, wire bonded, etc. It should be noted that in some example embodiments, the first die interconnect structure 213 may be a die pad of the first functional die 211.

The first grain interconnect structure 213 may, for example, be capped. For example, the first grain interconnect structure 213 may be capped by solder. As another example, the first grain interconnect structure 213 may be capped by a metal layer (e.g., a metal layer other than solder that forms a substitutional solid solution or an intermetallic compound with copper). For example, the first grain interconnect structure 213 may be formed and/or connected as explained in U.S. Patent Application No. 14/963,037, filed on December 8, 2015, entitled “Transient Interface Gradient Bonding for Metal Bonds,” the entire contents of which are hereby incorporated herein by reference. Additionally, for example, the first die interconnect structure 213 may be formed and/or connected as explained in U.S. Patent Application No. 14/989,455, filed on January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” the entire contents of which are hereby incorporated herein by reference.

The first die interconnect structure 213 may, for example, include any of a variety of dimensional features. For example, in an example embodiment, the first die interconnect structure 213 may include a pitch (e.g., center-to-center spacing) of 30 microns and a diameter (or width, minor axis or major axis width, etc.) of 17.5 microns. For another example, in an example embodiment, the first die interconnect structure 213 may include a pitch in the range of 20 to 40 (or 30 to 40) microns and a diameter (or width, minor axis or major axis width, etc.) in the range of 10 to 25 microns. The first die interconnect structure 213 may, for example, be 15 to 20 microns high.

The second die interconnect structures 214 may, for example, share any or all features with the first die interconnect structures 213. Some or all of the second die interconnect structures 214 may, for example, be substantially different from the first die interconnect structures 213.

The second die interconnect structure 214 may, for example, include a metal (e.g., copper, aluminum, etc.) pillar or connection pad. The second die interconnect structure 214 may also, for example, include a conductive bump (e.g., C4 bump, etc.) or a ball, a lead, etc. The second die interconnect structure 214 may, for example, be the same general type of interconnect structure as the first die interconnect structure 213, but need not be so. For example, the first die interconnect structure 213 and the second die interconnect structure 214 may both include copper pillars. For another example, the first die interconnect structure 213 may include a metal connection pad, and the second die interconnect structure 214 may include a copper pillar.

The second die interconnect structure 214 may be formed in any of a variety of ways. For example, the second die interconnect structure 214 may be plated on the die pad of the functional die 211. For another example, the second die interconnect structure 214 may be printed and reflowed, wire bonded, etc. The second die interconnect structure 214 may be formed in the same process steps as the first die interconnect structure 213, but such die interconnect structures 213 and 214 may also be formed in separate steps and/or in overlapping steps.

For example, in a first example scenario, a first portion (e.g., a first half, a first third) of each of the second die interconnect structures 214 can be formed in the same first plating operation as the first die interconnect structures 213. Continuing with the first example scenario, a second portion (e.g., a second half, a remaining two thirds, etc.) of each of the second die interconnect structures 214 can then be formed in a second plating operation. For example, during the second plating operation, the first die interconnect structures 213 can be inhibited from additional plating (e.g., by a dielectric or protective mask layer formed thereon, by removing a plating signal, etc.). In another example scenario, the second die interconnect structure 214 may be formed in a second plating process that is completely independent of the first plating process used to form the first die interconnect structure 213, during which the first die interconnect structure may be covered by a protective mask layer, for example.

The second die interconnect structure 214 may be, for example, uncapped. For example, the second die interconnect structure 214 may not be capped by solder. In an example scenario, the first die interconnect structure 213 may be capped (e.g., capped by solder, capped by a metal layer, etc.), while the second die interconnect structure 214 is not capped. In another example scenario, both the first die interconnect structure 213 and the second die interconnect structure 214 are not capped.

The second die interconnect structure 214 may, for example, include any of a variety of dimensional characteristics. For example, in an example embodiment, the second die interconnect structure 214 may include a pitch (e.g., center-to-center spacing) of 80 microns and a diameter (or width) of 25 microns or more. For another example, in an example embodiment, the second die interconnect structure 214 may include a pitch in the range of 50 to 80 microns and a diameter (or width, minor axis or major axis width, etc.) in the range of 20 to 30 microns. Additionally, for example, in an example embodiment, the second die interconnect structure 214 may include a pitch in the range of 80 to 150 (or 100 to 150) microns and a diameter (or width, minor axis or major axis width, etc.) in the range of 25 to 40 microns. The second die interconnect structure 214 may be, for example, 40 to 80 microns high.

It should be noted that the functional die (eg, in wafer form, etc.) may be received already having one or more die interconnect structures 213 / 214 (or any portion thereof) formed thereon.

It should also be noted that the functional die (e.g., in wafer form) may be thinned from its original die thickness (e.g., by grinding, mechanical and/or chemical thinning, etc.) at this point, but need not be so. For example, the functional die wafer (e.g., the wafer shown in Examples 200A-1, 200A-2, 200A-3, and/or 200A-4) may be a full thickness wafer. For another example, the functional die wafer (e.g., the wafer shown in Examples 200A-1, 200A-2, 200A-3, 200A-4, etc.) may be at least partially thinned to reduce the thickness of the resulting package while still achieving safe handling of the wafer.

Generally, block 110 may include receiving, manufacturing and/or preparing a plurality of functional dies. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of such receiving and/or manufacturing, nor by any particular characteristics of such functional dies.

The example method 100 may include receiving, manufacturing, and/or preparing a connection die at block 115. Block 115 may include receiving, manufacturing, and/or preparing a plurality of connection dies in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 115 are presented in examples 200B-1 to 200B-7 shown in FIG. 2B-1 and FIG. 2B-2.

Block 115 may, for example, include receiving a plurality of connected dies from an upstream manufacturing process at the same facility or geographic location. Block 115 may also, for example, include receiving connected dies from a supplier (eg, from a foundry, etc.).

The received, manufactured and/or prepared connection die may include any of a variety of features. For example, the received, manufactured and/or prepared die may include multiple connection die on a wafer (e.g., a silicon or other semiconductor wafer, a glass wafer or panel, a metal wafer or panel, etc.). For example, as shown in Figure 2B-1, example 200B-1 includes an entire wafer of connection die, and the example connection die of the connection die is shown with element symbol 216a. It should be understood that although the various examples shown herein generally involve the use of a single connection die in a package, multiple connection die (e.g., multiple connection die with the same or different designs) can be used in a single electronic device package. Non-limiting examples of such configurations are provided herein.

In the examples shown herein (e.g., 200B-1 to 200B-4), the connection die may, for example, only include electrical routing circuits (e.g., without active semiconductor components and/or passive components). However, it is noted that the scope of the present disclosure is not limited to this. For example, the connection die shown herein may include passive electronic components (e.g., resistors, capacitors, inductors, integrated passive devices (IPDs), etc.) and/or active electronic components (e.g., transistors, logic circuits, semiconductor processing components, semiconductor memory components, etc.) and/or optical components, etc.

The connecting die may include a connecting die interconnect structure. For example, the example connecting die 216a shown in FIG. 200B-1 includes a connecting die interconnect structure 217. The connecting die interconnect structure 217 may include any of a variety of interconnect structure features, non-limiting examples of which are provided herein. Although this discussion generally presents all connecting die interconnect structures 217 as being the same as each other, they may also be different from each other. For example, referring to FIG. 2B-1, the left side portion of the connecting die interconnect structure 217 may be the same as or different from the right side portion of the connecting die interconnect structure 217.

The connecting die interconnect structure 217 and/or its formation may share any or all features with the first die interconnect structure 213 and/or the second die interconnect structure 214 and/or its formation discussed herein. In an example embodiment, a first portion of the connecting die interconnect structure 217 may include spacing, layout, shape, size and/or material features that provide for fitting such first portion to a corresponding first die interconnect structure 213 of a first functional die 211, and a second portion of the connecting die interconnect structure 217 may include spacing, layout, shape, size and/or material features that provide for fitting such second portion to a corresponding first die interconnect structure 213 of a second functional die 212.

The connecting die interconnect structure 217 may include, for example, a metal (eg, copper, aluminum, etc.) column or a connecting pad. The connecting die interconnect structure 217 may also include, for example, a conductive bump (eg, a C4 bump, etc.) or a ball, a lead, a column, etc.

The connecting die interconnect structure 217 can be formed in any of a variety of ways. For example, the connecting die interconnect structure 217 can be plated on the die pad of the connecting die 216a. For another example, the connecting die interconnect structure 217 can be printed and reflowed, wire bonded, etc. It should be noted that in some example embodiments, the connecting die interconnect structure 217 can be the die pad of the connecting die 216a.

The connecting grain interconnect structure 217 can, for example, be capped. For example, the connecting grain interconnect structure 217 can be covered by solder. As another example, the connecting grain interconnect structure 217 can be capped by a metal layer (e.g., a metal layer that forms a substitutional solid solution or an intermetallic compound with copper). For example, the connecting grain interconnect structure 217 can be formed and/or connected as explained in U.S. Patent Application No. 14/963,037, filed on December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," the entire contents of which are hereby incorporated by reference herein. Additionally, for example, the connecting die interconnect structure 217 may be formed and/or connected as explained in U.S. Patent Application No. 14/989,455, filed on January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” the entire contents of which are hereby incorporated herein by reference.

The connecting die interconnect structure 217 may, for example, include any of a variety of dimensional features. For example, in an example embodiment, the connecting die interconnect structure 217 may include a pitch (e.g., center-to-center spacing) of 30 microns and a diameter (or width, minor axis or major axis width, etc.) of 17.5 microns. For another example, in an example embodiment, the connecting die interconnect structure 217 may include a pitch in the range of 20 to 40 (or 30 to 40) microns and a diameter (or width, minor axis or major axis width, etc.) in the range of 10 to 25 microns. The connecting die interconnect structure 217 may, for example, be 15 to 20 microns high.

In an example scenario, the connecting die interconnect structure 217 may include a copper pillar that cooperates with the corresponding first die interconnect structure 213 (eg, metal connection pads, conductive bumps, copper pillars, etc.) of the first functional die 211 and the second functional die 212 .

The connecting die 216a (or its wafer 200B-1) can be formed in any of a variety of ways, non-limiting examples of which are discussed herein. For example, referring to FIG. 2B-1, the connecting die 216a (e.g., shown in example 200B-3) or its wafer (e.g., shown in example 200B-1) can, for example, include a support layer 290a (e.g., a silicon or other semiconductor layer, a glass layer, a metal layer, a plastic layer, etc.). A redistribution (RD) structure 298 can be formed on the support layer 290. The RD structure 298 can, for example, include a base dielectric layer 291, a first dielectric layer 293, a first conductive trace 292, a second dielectric layer 296, a second conductive trace 295, and a connecting die interconnect structure 217.

The base dielectric layer 291 may be, for example, on the support layer 290. The base dielectric layer 291 may, for example, include an oxide layer, a nitride layer, any of a variety of inorganic dielectric materials, etc. The base dielectric layer 291 may, for example, be formed according to specifications and/or may be natural. The base dielectric layer 291 may be referred to as a passivation layer. The base dielectric layer 291 may be or include, for example, a silicon dioxide layer formed using a low pressure chemical vapor deposition (LPCVD) process. In other example embodiments, the base dielectric layer 291 may be formed of any of a variety of organic dielectric materials, many examples of which are provided herein.

The connecting die 216a (e.g., shown in example 200B-3) or its wafer (e.g., shown in example 200B-1) may also include, for example, a first conductive trace 292 and a first dielectric layer 293. The first conductive trace 292 may, for example, include a deposited conductive metal (e.g., copper, aluminum, tungsten, etc.). The first conductive trace 292 may, for example, be formed by sputtering, electroplating, electroless plating, etc. The first conductive trace 292 may, for example, be formed at a sub-micron or sub-two-micron pitch (or center-to-center spacing). The first dielectric layer 293 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It should be noted that in various embodiments, the first dielectric layer 293 can be formed before the first conductive trace 292, for example, by forming a hole and then filling the hole with the first conductive trace 292 or a portion thereof. In example embodiments including copper conductive traces, for example, the traces can be deposited using a dual damascene process.

In alternative assemblies, the first dielectric layer 293 may include an organic dielectric material. For example, the first dielectric layer 293 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzo cyclo butene (BCB), polybenz oxazole (PBO), epoxy resin, and equivalents thereof and compounds thereof, but the aspects of the present disclosure are not limited thereto. The organic dielectric material may be formed in any of a variety of ways, such as chemical vapor deposition (CVD). In such alternative assemblies, the first conductive traces 292 may, for example, be at a pitch (or center-to-center spacing) of 2 to 5 microns.

The connection die 216a (e.g., shown in example 200B-3) or its wafer 200B-1 (e.g., shown in example 200B-1) may also, for example, include a second conductive trace 295 and a second dielectric layer 296. The second conductive trace 295 may, for example, include a deposited conductive metal (e.g., copper, etc.). The second conductive trace 295 may, for example, be connected to a corresponding first conductive trace 292 through a corresponding conductive via 294 or hole (e.g., in the first dielectric layer 293). The second dielectric layer 296 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In alternative assemblies, the second dielectric layer 296 may include an organic dielectric material. For example, the second dielectric layer 296 may include bismaleimide triazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin and equivalents thereof and compounds thereof, but the aspects of the present disclosure are not limited thereto. The second dielectric layer 296 may be formed, for example, using a CVD process, but the scope of the present disclosure is not limited thereto. It should be noted that the various dielectric layers (e.g., the first dielectric layer 293, the second dielectric layer 296, etc.) may be formed from the same dielectric material and/or formed using the same process, but this is not required. For example, the first dielectric layer 293 may be formed from any inorganic dielectric material discussed herein, and the second dielectric layer 296 may be formed from any organic dielectric material discussed herein, and vice versa.

Although two sets of dielectric layers and conductive traces are shown in FIG. 2B-1, it should be understood that the RD structure 298 connecting the die 216a (e.g., as shown in example 200B-3) or the wafer thereof (e.g., as shown in example 200B-1) may include any number of such layers and traces. For example, the RD structure 298 may include only one dielectric layer and/or one set of conductive traces, three sets of dielectric layers and/or conductive traces, etc.

A connecting die interconnect structure 217 (e.g., a conductive bump, a conductive ball, a conductive post or pillar, a conductive connection pad or liner, etc.) can be formed on the surface of the RD structure 298. Examples of such connecting die interconnect structures 217 are shown in FIGS. 2B-1 and 2B-2, where the connecting die interconnect structures 217 are shown as being formed on the front (or top) surface of the RD structure 298 and electrically connected to the corresponding second conductive traces 295 through conductive vias in the second dielectric layer 296. Such connecting die interconnect structures 217 can be used, for example, to couple the RD structure 298 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.), including, for example, the first functional die 211 and the second functional die 212 discussed herein.

The connecting die interconnect structure 217 may, for example, include any one of various conductive materials (e.g., any one or combination of copper, nickel, gold, etc.). The connecting die interconnect structure 217 may also, for example, include solder. For another example, the connecting die interconnect structure 217 may include solder balls or bumps, multi-ball solder pillars, elongated solder balls, metal (e.g., copper) core balls with a solder layer on a metal core, plated pillar structures (e.g., copper pillars, etc.), lead structures (e.g., wire bonding leads), etc.

Referring to FIG. 2B-1, an example 200B-1 showing a wafer of connecting die 216a can be thinned, for example, to produce a thin connecting die wafer of thin connecting die 216b as shown in example 200B-2. For example, a thin connecting die wafer (e.g., as shown in example 200B-2) can be thinned (e.g., by grinding, chemical and/or mechanical thinning, etc.) to a degree that still allows safe handling of the thin connecting die wafer and/or its individual thin connecting die 216b but provides a low profile. For example, referring to FIG. 2B-1, in an example embodiment in which the support layer 290 includes silicon, the thin connecting die 216b can still include at least a portion of the silicon support layer 290. For example, the bottom surface (or back surface) of the thin connecting die 216b may include sufficient non-conductive support layer 290, base dielectric layer 291, etc. to prohibit the bottom surface of the remaining supporting layer 290 from conductively contacting the conductive layer on the top surface. In other examples, the thin connecting die 216b can be thinned to substantially or completely remove the supporting layer 290. In such examples, the conductive contact of the bottom surface of the connecting die 216b can still be blocked by the base dielectric 291.

For example, in an example embodiment, the thin-connected die wafer (e.g., as shown in example 200B-2) or its thin-connected die 216b can have a thickness of 50 microns or less. In another example embodiment, the thin-connected die wafer (or its thin-connected die 216b) can have a thickness in the range of 20 to 40 microns. As will be discussed herein, the thickness of the thin-connected die 216b can be less than the length of the second die interconnect structure 214 of the first die 211 and the second die 212, for example, so that the thin-connected die 216b can be assembled between the carrier and the functional die 211 and 212.

Two example connected die implementations, labeled "Connected Die Example 1" and "Connected Die Example 2," are shown at 200B-5 of FIG. 2B-2. Connected Die Example 1 can, for example, utilize an inorganic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in an RD structure 298 and a semiconductor support layer 290. Connected Die Example 1 can, for example, be produced using Amkor Technology's Silicon-Free Integrated Module (SLIM™) technology. The semiconductor support layer can, for example, be 30 to 100 μm (e.g., 70 μm) thick, and each level (or sub-layer or layer) of the RD structure (e.g., including at least a dielectric layer and a conductive layer) can, for example, be 1 to 3 μm (e.g., 3 μm, 5 μm, etc.) thick. The total thickness of the example resulting structure can be, for example, in the range of 33 to 109 μm (eg, <80 μm, etc.) It should be noted that the scope of the present disclosure is not limited to any particular dimensions.

Connected die example 2 may, for example, utilize an organic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in RD structure 298 and semiconductor support layer 290. Connected die example 2 may, for example, be produced using Amkor Technology's Silicon Wafer Integrated Fan-Out (SWIFT™) technology. The semiconductor support layer may, for example, be 30 to 100 μm (e.g., 70 μm) thick, and each level (or sub-level or layer) of the RD structure (e.g., including at least a dielectric layer and a conductive layer) may, for example, be 4 to 7 μm thick, 10 μm thick, etc. The total thickness of the resulting structure of the example may, for example, be in the range of 41 to 121 μm (e.g., <80 μm, 100 μm, 110 μm, etc.). It should be noted that the scope of the present disclosure is not limited to any particular dimensions. It should also be noted that in various example implementations, the support layer 290 of the bonding die example 2 can be thinned (eg, relative to the bonding die example 1) to achieve the same or similar overall thickness.

The example embodiments presented herein generally relate to single-sided connection die, which may, for example, have interconnect structures on only one side. However, it should be noted that the scope of the present disclosure is not limited to such single-sided structures. For example, as shown in examples 200B-6 and 200B-7, the connection die 216c may include interconnect structures on both sides. An example embodiment of such a connection die 216c (e.g., as shown in example 200B-7) and its wafer (e.g., as shown in example 200B-6), which may also be referred to as a double-sided connection die, is shown in FIG. 2B-2. The example wafer (e.g., example 200B-6) may, for example, share any or all features with the example wafers shown in FIG. 2B and discussed herein (e.g., examples 200B-1 and/or 200B-2). For another example, example connecting die 216c can share any or all features with example connecting die 216a and/or 216b shown in FIG. 2B-1 and discussed herein. For example, connecting die interconnect structure 217b can share any or all features with connecting die interconnect structure 217 shown in FIG. 2B-1 and discussed herein. For another example, any or all of the redistribution (RD) structure 298b, the base dielectric layer 291b, the first conductive trace 292b, the first dielectric layer 293b, the conductive via 294b, the second conductive trace 295b, and the second dielectric layer 296b may share any or all features with the redistribution (RD) structure 298, the base dielectric layer 291, the first conductive trace 292, the first dielectric layer 293, the conductive via 294, the second conductive trace 295, and the second dielectric layer 296, respectively, shown in FIG. 2B-1 and discussed herein. The example connecting die 216c also includes a second set of connecting die interconnect structures 299 received and/or fabricated on a side of the connecting die 216c opposite the connecting die interconnect structures 217b. Such second connecting die interconnect structures 299 may share any or all features with the connecting die interconnect structures 217. In an example embodiment, the second connecting die interconnect structures 299 may be first formed when the RD structures 298b are accumulated on a support structure (e.g., similar to the support structure 290), and then removed or thinned or planarized (e.g., by grinding, peeling, stripping, etching, etc.).

Similarly, any or all of the example methods and structures shown in U.S. Patent Application No. 15/594,313, which is hereby incorporated by reference herein in its entirety, may be implemented by any such connected dies 216a, 216b, and/or 216c.

It should be noted that one or more or all of the second connecting die interconnect structures 299 can be isolated from other circuits of the connecting die 216c, which can also be referred to herein as dummy structures (e.g., dummy pillars, etc.), anchoring structures (e.g., anchoring pillars, etc.). For example, any one or all of the second connecting die interconnect structures 299 can be formed only to anchor the connecting die 216c to a carrier or RD structure or metal pattern in a later step. It should also be noted that one or more or all of the second connecting die interconnect structures 299 can be electrically connected to electrical traces, which can, for example, be connected to electronic device circuits of a die attached to the connecting die 216c. Such structures can, for example, be referred to as active structures (e.g., active pillars, etc.), etc.

Generally, block 115 may include receiving, manufacturing and/or preparing a connection die. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of such receiving, manufacturing and/or preparing or any particular characteristics of such connection die.

The example method 100 may include receiving, manufacturing, and/or preparing a first carrier at block 120. Block 120 may include receiving, manufacturing, and/or preparing a carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 120 may, for example, share any or all features with other carrier receiving, manufacturing, and/or preparing steps discussed herein. Various example aspects of block 120 are presented at example 200C of FIG. 2C.

Block 120 may, for example, include receiving the carrier from an upstream manufacturing process at the same facility or geographic location. Block 120 may also, for example, include receiving the carrier from a supplier (e.g., from a foundry, etc.).

The received, manufactured and/or prepared carrier 221 may include any of a variety of features. For example, the carrier 221 may include a semiconductor wafer or panel (e.g., a typical semiconductor wafer, a lower-grade semiconductor wafer using lower-grade silicon than the functional die discussed herein, etc.). For another example, the carrier 221 may include metal, glass, plastic, etc. The carrier 221 may be, for example, reusable or destructible (e.g., single use, multiple use, etc.).

The carrier 221 may include any of a variety of shapes. For example, the carrier may be wafer-shaped (e.g., circular, etc.), panel-shaped (e.g., square, rectangular, etc.), etc. The carrier 221 may have any of a variety of lateral dimensions and/or thicknesses. For example, the carrier 221 may have the same or similar lateral dimensions and/or thickness of the functional die and/or wafers connecting the die discussed herein. For another example, the carrier 221 may have the same or similar thickness as the functional die and/or wafers connecting the die discussed herein. The scope of the present disclosure is not limited by any particular carrier feature (e.g., material, shape, size, etc.).

The example 200C shown in FIG2C includes a layer of adhesive material 223. The adhesive material 223 may include any of various types of adhesives. For example, the adhesive may be a liquid, a paste, a tape, etc.

The adhesive 223 may include any of a variety of sizes. For example, the adhesive 223 may cover the entire top surface of the first carrier 221. For another example, the adhesive may cover the central portion of the top surface of the first carrier 221 while leaving the outer edges of the top surface of the first carrier 221 uncovered. For another example, the adhesive may cover the corresponding portion of the top surface of the first carrier 221 that corresponds in position to the future position of the functional die of a single electronic package.

The thickness of the adhesive 223 may be greater than the height of the second die interconnect structure 214 , and thus also greater than the height of the first die interconnect structure 213 (eg, 5% greater, 10% greater, 20% greater, etc.).

The example carrier 221 may share any or all features with any of the carriers discussed herein. For example, but not limited to, the carrier may not have a signal distribution layer, but may also include one or more signal distribution layers. Examples of such structures and their formation are shown in example 600A of FIG. 6A and discussed herein.

Generally, block 120 may include receiving, manufacturing and/or preparing a carrier. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular conditions for receiving a carrier, any particular manner for manufacturing a carrier, and/or any particular manner for preparing such a carrier for use.

Example method 100 may include coupling (or mounting) a functional die to a carrier (e.g., coupled to a top surface of a non-conductive carrier, coupled to a metal pattern on a top surface of a carrier, coupled to an RD structure on a top surface of a carrier, etc.) at block 125. Block 125 may include performing such coupling in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 125 may, for example, share any or all features with other die mounting steps discussed herein. Various example aspects of block 125 are presented in example 200D shown in FIG. 2D.

For example, the functional dies 201-204 (e.g., any one of the functional dies 211 and 212) can be received as individual dies. For another example, one or more functional dies 201-204 can be received on a single wafer, one or more of the functional dies 201-204 can be received on multiple corresponding wafers (e.g., as shown in examples 200A-1 and 200A-3, etc.), etc. In the case where one or two of the functional dies are received in wafer form, the functional dies can be cut from the wafer. It should be noted that if any of the functional dies 201-204 are received on a single MPW, such functional dies can be cut from the wafer as an attachment device (e.g., connected to bulk silicon).

Block 125 may include placing functional die 201-204 in adhesive layer 223. For example, second die interconnect structure 214 and first die interconnect structure 213 may be fully (or partially) inserted into adhesive layer 223. As discussed herein, adhesive layer 223 may be thicker than the height of second die interconnect structure 214, such that when the bottom surface of die 201-204 contacts the top surface of adhesive layer 223, the bottom end of second die interconnect structure 214 does not contact carrier 221. However, in alternative embodiments, the adhesive layer 223 may be thinner than the height of the second die interconnect structure 214 , but still thick enough to cover at least a portion of the first die interconnect structure 213 when the dies 201 - 204 are placed on the adhesive layer 223 .

Block 125 may include placing functional dies 201 - 204 using, for example, a die pick and place machine.

It should be noted that although the illustrations herein generally set the size and shape of the functional dies 201-204 (and their interconnect structures) to be similar, such symmetry is not required. For example, the functional dies 201-204 can have different corresponding shapes and sizes, can have different types and/or numbers of interconnect structures, etc. It should also be noted that the functional dies 201-204 (or any so-called functional dies discussed herein) can be semiconductor dies, but can also be any of a variety of electronic components, such as passive electronic components, active electronic components, bare dies, packaged dies, etc. Therefore, the scope of the present disclosure should not be limited to the characteristics of the functional dies 201-204 (or any so-called functional dies discussed herein).

Typically, block 125 may include coupling (or mounting) a functional die to a carrier. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such coupling or any particular characteristics of such functional die, interconnect structure, carrier, attachment member, etc.

Example method 100 may include encapsulation at block 130. Block 130 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 130 are presented in example 200E shown in FIG. 2E. Block 130 may, for example, share any or all features with other encapsulations discussed herein.

Block 130 may, for example, include performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to cutting the individual modules. Referring to the example embodiment 200E shown in FIG. 2E , encapsulation material 226 ′ may cover the top surface of adhesive 223, the top surface of functional die 201-204, at least a portion (or all) of the side surfaces of functional die 201-204, etc. Encapsulation material 226 ′ may also, for example, cover any portion of second die interconnect structure 214, first die interconnect structure 213, and the bottom surface of functional die 201-204 exposed from 223 (if any such components are exposed).

The encapsulation material 226' may include any of a variety of types of encapsulation materials, such as a molding material, any dielectric material presented herein, and the like.

Although encapsulation material 226 ′ (as shown in FIG. 2E ) is shown covering top surfaces of functional dies 201 - 204 , any or all such top surfaces (or any corresponding portions of such top surfaces) may be exposed from encapsulation material 226 (as shown in FIG. 2F ). Block 130 may, for example, include initially forming an encapsulation material 226 in which the top surface of the die is exposed (e.g., using a film-assisted molding technique, a die-sealed molding technique, etc.); forming an encapsulation material 226', followed by a thinning process (e.g., performed at block 135) to thin the encapsulation material 226' sufficiently to expose the top surface of any or all of the functional die 201-204; forming an encapsulation material 226', followed by a thinning process (e.g., performed at block 135) to thin the encapsulation material but still retain a portion of the encapsulation material 226' covering the top surface of any or all of the functional die 201-204 (or any corresponding portion thereof); etc.

Generally, block 130 may include encapsulation. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or by the characteristics of any particular type of encapsulation material or its configuration.

Example method 100 can include grinding the encapsulation material at block 135. Block 135 can include performing such grinding (or any thinning or planarization) in any of a variety of ways, non-limiting examples of which are provided herein. Block 135 can, for example, share any or all features with other grinding (or thinning) blocks (or steps) discussed herein. Various example aspects of block 135 are presented in example 200F shown in FIG. 2F.

As discussed herein, in various example embodiments, the encapsulation material 226' may be initially formed to a thickness greater than that ultimately desired. In such example embodiments, block 135 may be performed to grind (or otherwise thin or planarize) the encapsulation material 226'. In the example 200F shown in FIG. 2F , the encapsulation material 226' has been grinded to form the encapsulation material 226. The top surface of the grinded (or thinned or planarized) encapsulation material 226 is coplanar with the top surface of the functional die 201-204, and thus, the functional die is exposed from the encapsulation material 226. It should be noted that in various example embodiments, one or more of the functional die 201-204 may be exposed, while one or more of the functional die 201-204 may remain covered by the encapsulation material 226. It should be noted that such grinding operations, if performed, need not expose the top surfaces of the functional die 201-204.

In an example embodiment, block 135 may include grinding (or thinning or planarizing) the encapsulation material 226 ′ and the backsides of any or all of the functional dies 201 - 204 to achieve coplanarity of the top surface of the encapsulation material 226 with one or more of the functional dies 201 - 204 .

Typically, block 135 may include a polishing encapsulation material. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such polishing (or thinning or planarization).

Example method 100 may include attaching a second carrier at block 140. Block 140 may include attaching a second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 140 may share any or all features with any carrier attachment discussed herein. FIG. 2G illustrates various example aspects of block 140.

As shown in example 200G of FIG. 2G , a second carrier 231 may be attached to the top surface of the encapsulation material 226 and/or the top surface of the functional die 201-204. It should be noted that the assembly may still be in wafer (or panel) form at this time. The second carrier 231 may include any of a variety of features. For example, the second carrier 231 may include a glass carrier, a silicon (or semiconductor) carrier, a metal carrier, a plastic carrier, etc. The block 140 may include attaching (or coupling or mounting) the second carrier 231 in any of a variety of ways. For example, the block 140 may include attaching the second carrier 231 using an adhesive, using a mechanical attachment mechanism, using vacuum attachment, etc.

Typically, block 140 may include attaching a second carrier. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of attaching a carrier or the features of any particular type of carrier.

Example method 100 may include removing the first carrier at block 145. Block 145 may include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 145 may share any or all features with any carrier removal process discussed herein. Various example aspects of block 145 are presented in example 200H shown in FIG. 2H.

For example, example 200H of FIG. 2H shows that first carrier 221 is removed (e.g., compared to example 200G of FIG. 2G ). Block 145 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, stripping, shearing, thermal release or laser release, etc.).

As another example, block 145 may include removing an adhesive layer 223 used at block 125 to couple the functional die 201-204 to the first carrier 221. For example, such an adhesive layer 223 may be removed in a single or multi-step process along with the first carrier 221. For example, in an example embodiment, block 145 may include pulling the first carrier 221 out of the functional die 201-204 and the encapsulation material 226, wherein the adhesive (or a portion thereof) is removed along with the first carrier 221. For another example, block 145 may include removing the adhesive layer 223 (e.g., the entire adhesive layer 223 and/or any portion of the adhesive layer 223 remaining after removing the first carrier 221, etc.) from the functional dies 201-204 (e.g., from the bottom surface of the functional dies 201-204, from the interconnect structure of the first die 213 and/or the second die 214, etc.) and the encapsulation material 226 using a solvent, heat energy, light energy, or other cleaning techniques.

Typically, block 145 may include removing the first carrier. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of removing the carrier or the features of any particular type of carrier.

Example method 100 may include attaching (or coupling or mounting) a connection die to a functional die at block 150. Block 150 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 150 may, for example, share any or all features with any die attach process discussed herein. Various example aspects of block 150 are presented at FIG. 2I.

For example, the die interconnect structures 217 of the first connecting die 216 b (eg, any or all of such connecting die) may be mechanically and electrically connected to the corresponding first die interconnect structures 213 of the first functional die 201 and the second functional die 202 .

Such interconnect structures can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In an example embodiment, the first die interconnect structure 213 and/or the connecting die interconnect structure 217 can include a solder cap (or other solder structure) that can be reflowed to perform the connection. Such solder caps can be reflowed, for example, by mass reflow, thermal compression bonding (TCB), etc. In another example embodiment, the connection can be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without the use of solder. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, filed on December 8, 2015, entitled “Transient Interface Gradient Bonding for Metal Bonds,” and U.S. Patent Application No. 14/989,455, filed on January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” each of which is hereby incorporated by reference in its entirety. The first die interconnect structure 213 may be attached to the connecting die interconnect structure 217 using any of a variety of techniques (eg, mass reflow, thermal compression bonding (TCB), direct metal-to-metal metal bonding, conductive adhesives, etc.).

As shown in example 200I, the first die interconnect structure 213 of the first connecting die 201 is connected to the corresponding connecting die interconnect structure 217 of the connecting die 216b, and the first die interconnect structure 213 of the second connecting die 202 is connected to the corresponding connecting die interconnect structure 217 of the connecting die 216b. When connected, the connecting die 216b provides electrical connection between the various die interconnect structures of the first functional die 201 and the second functional die 202 via the RD structure 298 (for example, as shown in example 200B-3 of FIG. 2B-1, etc.).

In the example 200I shown in FIG2I, the height of the second die interconnect structure 214 can be, for example, greater than (or equal to) the combined height of the first die interconnect structure 213, the connecting die interconnect structure 217, the RD structure 298, and any supporting layer 290b of the connecting die 216b. Such a height difference can, for example, provide space for a buffer material (e.g., bottom filler, etc.) between the connecting die 216b and another substrate (e.g., as shown in the example 200N of FIG2N and discussed herein).

It should be noted that although the example connection die (216b) is shown as a single-sided connection die (e.g., similar to the example connection die 216b of FIG. 2B-1), the scope of the present disclosure is not limited thereto. For example, any or all of such example connection die 216b may be double-sided (e.g., similar to the example connection die 216c of FIG. 2B-2).

Typically, block 150 may include attaching (or coupling or mounting) a connection die to a functional die. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment or the features of any particular type of attachment structure.

Example method 100 may include bottom filling the connection die at block 155. Block 155 may include performing such bottom filling in any of a variety of ways, non-limiting examples of which are provided herein. Block 155 may, for example, share any or all features with any bottom filling process discussed herein. Various example aspects of block 155 are presented in example 200J shown in FIG. 2J.

It should be noted that an underfill may be applied between the connecting die 216b and the functional die 201-204. In the context of utilizing a pre-applied underfill (PUF), such a PUF may be applied to the functional die 201-204 and/or to the connecting die 216b prior to coupling the connecting die interconnect structure 217 to the first die interconnect structure 213 of the functional die 201-204 (e.g., at block 150).

After the attachment performed at block 150, block 155 may include forming an underfill (e.g., a capillary underfill, etc.). As shown in example embodiment 200J of FIG. 2J, an underfill material 223 (e.g., any underfill material discussed herein, etc.) may fully or partially cover a bottom surface of the connecting die 216b (e.g., in the orientation shown in FIG. 2J), and/or at least a portion (if not all) of a side surface of the connecting die 216b. The underfill material 223 may also, for example, surround the connecting die interconnect structure 217, and surround the first die interconnect structure 213 of the functional die 201-204. The underfill material 223 may additionally cover the top surface of the functional die 201-204 (in the orientation shown in FIG. 2J), for example, in an area corresponding to the first die interconnect structure 213.

It should be noted that in various example implementations of example method 100, the underfill performed at block 155 may be skipped. For example, underfilling the connection die may be performed at another block (e.g., at block 175, etc.). As another example, such underfill may be omitted entirely.

Typically, block 155 may include underfilling the connection die. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or the characteristics of any particular type of underfill.

Example method 100 may include removing the second carrier at block 160. Block 160 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 160 may share any or all features with any carrier removal process discussed herein (e.g., with respect to block 145, etc.). Example 200K shown in FIG. 2K presents various example aspects of block 160.

For example, the example embodiment 200K shown in Figure 2K does not include the second carrier 231 of the example embodiment 200J shown in Figure 2J. It should be noted that such removal may include, for example, cleaning the surface, removing the adhesive (if used), etc.

Typically, block 160 may include removing the second carrier. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such carrier removal or the characteristics of any particular type of carrier or carrier material being removed.

The example method 100 may include a singulation cut at block 165. Block 165 may include performing such a singulation cut in any of a variety of ways, non-limiting examples of which are discussed herein. Block 165 may, for example, share any or all features with any singulation cut discussed herein. The example 200L shown in FIG. 2L presents various example aspects of block 165.

As discussed herein, the example components shown herein can be formed on a wafer or panel containing multiple such components (or modules). For example, the example 200K shown in FIG. 2K has two components (left and right) joined together by an encapsulation material 226. In such example embodiments, the wafer or panel can be singulated (or diced) to form individual components (or modules). In the example 200L of FIG. 2L, the encapsulation material 226 is sawed (or cut, broken, stretched, diced, or otherwise cut, etc.) into two encapsulation material portions 226a and 226b, each portion corresponding to a corresponding electronic device.

In the example embodiment 200L shown in FIG. 2L , only the encapsulation material 226 needs to be trimmed. However, the block 165 may include trimming any of the various materials if present along the singulation cut lines (or trim lines). For example, the block 165 may include trimming underfill material, carrier material, functional and/or connection die material, substrate material, etc.

Typically, block 165 may include singulation. Therefore, the scope of the present disclosure should not be limited by any particular manner of singulation.

Example method 100 may include mounting to a substrate at block 170. Block 170 may, for example, include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 170 may share any or all features with any mounting (or attachment) steps discussed herein (e.g., attaching interconnect structures, attaching backside of a die, etc.). Various example aspects of block 170 are presented in example 400M shown in FIG. 4M.

Substrate 288 may include any of a variety of features, non-limiting examples of which are provided herein. For example, substrate 288 may include a packaging substrate, an interposer, a motherboard, a printed wiring board, a functional semiconductor die, a stacked weight distribution structure of another device, etc. Substrate 288 may, for example, include a coreless substrate, an organic substrate, a ceramic substrate, etc. Substrate 288 may, for example, include one or more dielectric layers (e.g., organic and/or inorganic dielectric layers) and/or conductive layers formed on a semiconductor (e.g., silicon, etc.) substrate, a glass or metal substrate, a ceramic substrate, etc. Substrate 288 may, for example, share any or all features with RD structure 298 of FIG. 2B-1, RD structure 298b of FIG. 2B-2, any RD structure discussed herein, etc. Substrate 288 may, for example, include a single package substrate, or may include multiple substrates that are coupled together (eg, in a panel or wafer) and may be subsequently diced.

In example 200M shown in FIG. 2M , block 170 may include welding (e.g., using mass reflow, thermocompression bonding, laser welding, etc.) the second die interconnect structure 214 of the functional die 201 - 202 to a corresponding pad (e.g., a bonding pad, a trace, a connection pad, etc.) or other interconnect structures (e.g., pillars, posts, balls, bumps, etc.) of the substrate 288 .

It should be noted that in example embodiments where connecting die 216b is a double-sided connecting die similar to connecting die 216c, block 170 may also include a corresponding pad or other interconnect structure connecting the second set of connecting die interconnect structures 299 to substrate 288. However, in example 200M of FIG. 2M, connecting die 216b is a single-sided connecting die. It should be noted that, as discussed herein, because the second die interconnect structure 214 of the functional die 201-202 is taller than the combined height of the first die interconnect structure 213, the connecting die interconnect structure 217, and the supporting layer 290b of the connecting die 216b, a gap exists between the back side of the connecting die 216b (below the connecting die 216b in FIG. 2M ) and the top surface of the substrate 288. This gap may be filled with an underfill as shown in FIG. 2N .

Typically, block 170 includes mounting (or attaching or coupling) the components (or modules) singulated at block 165 to a substrate. Therefore, the scope of the present disclosure should not be limited by the features of any particular type of mounting (or attachment) or the features of any particular mounting (or attachment) structure.

Example method 100 may include performing underfill between a substrate and a component (or module) mounted thereto at block 170 at block 175. Block 175 may include performing underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 175 may, for example, share any or all features with any underfill (or encapsulation) process discussed herein (e.g., with respect to block 155, etc.). Various aspects of block 175 are presented in example 200N shown in FIG. 2N.

Block 175 may, for example, include performing a capillary underfill or injected underfill process after performing the mounting at block 170. As another example, in a scenario utilizing a pre-applied underfill (PUF), such PUF may be applied to a substrate, a metal pattern of a substrate, and/or its interconnect structures prior to such mounting. Block 175 may also include performing such underfill utilizing a molded underfill process.

As shown in the example embodiment 200N of FIG. 2N , a bottom fill material 291 (e.g., any bottom fill material discussed herein, etc.) can completely or partially cover the top surface of the substrate 288. The bottom fill material 291 can also, for example, surround the second die interconnect structure 214 (and/or corresponding substrate pad) of the functional die 201-202. The bottom fill material 291 can, for example, cover the bottom surface of the functional die 201-202, the bottom surface of the connecting die 216b, and the bottom surface of the encapsulation material 226a. The bottom fill material 291 can also, for example, cover the side surfaces of the connecting die 216b and/or the exposed lateral surfaces of the bottom fill 223 between the connecting die 216b and the functional die 201-202. The underfill material 291 may, for example, cover the encapsulation material 226 a and/or side surfaces (eg, all or a portion) of the functional dies 201 - 202 .

In example embodiments in which the underfill 223 is not formed, the underfill material 291 may be formed instead of the underfill 223. For example, referring to the example 200N, the underfill material 223 may be replaced with more underfill material 291 in the example 200N.

In an example embodiment in which the underfill 223 is formed, the underfill material 291 may be a different type of underfill material than the underfill material 223. In another example embodiment, both the underfill materials 223 and 291 may be the same type of material.

As with block 155, block 175 may also be skipped, for example leaving space at another block to be filled with another underfill (eg, molded underfill, etc.).

Typically, block 175 includes an underfill. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular type of underfill or the characteristics of any particular underfill material.

Example method 100 may include executing a continuation process at block 190. Such continuation process may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 190 may include returning the execution flow of example method 100 to any block thereof. For another example, block 190 may include directing the execution flow of example method 100 to any other method block (or step) discussed herein (e.g., example method 300 with respect to FIG. 3 , example method 500 with respect to FIG. 5 , etc.).

For example, block 190 may include interconnect structures 299 (eg, conductive balls, bumps, pillars, etc.) formed on a bottom surface of substrate 288 .

For another example, as shown in example 200O of FIG. 2O , block 190 may include forming encapsulation material 225. Such encapsulation material 225 may, for example, cover the top surface of substrate 288, the side surface of bottom filler 224, the side surface of encapsulation material 226a, and/or the side surface of functional die 201-202. In example 200O shown in FIG. 2O , the top surface of encapsulation material 225, the top surface of encapsulation material 226a, and/or the top surface of functional die 201-202 may be coplanar.

As discussed herein, an underfill 224 may not be formed (e.g., as formed at block 175). In this case, an encapsulation material 225 may replace the underfill. An example 200P of such a structure and method is provided at FIG. 2P. Relative to the example embodiment 200O shown in FIG. 20, in the example embodiment 200P, the underfill 224 of the example embodiment 200O is replaced with an encapsulation material 225 as the underfill.

As discussed herein, underfill 223 (e.g., as formed at block 155) and underfill 224 may not be formed. In this case, encapsulation material 225 may replace them. An example embodiment 200Q of such a structure and method is provided at FIG. 2Q. Relative to example embodiment 200P shown in FIG. 2P, in example embodiment 200Q, underfill 223 of example embodiment 200P is replaced by encapsulation material 225.

It should be noted that in any of the example embodiments 200O, 200P, and 200Q shown in FIGS. 2O, 2P, and 2Q, the sides of the encapsulation material 225 and the substrate 288 may be coplanar.

In the example method 100 shown in Figures 1 and 2A-2Q, various die interconnect structures (e.g., first die interconnect structure 213, second die interconnect structure 214, connecting die interconnect structure 217 (and/or 299), etc.) are typically formed during the receiving, manufacturing and/or preparation process of the die. For example, such various die interconnect structures can typically be formed before their corresponding die is integrated into the assembly. However, the scope of the present disclosure should not be limited by the timing of such example implementation schemes. For example, any or all of the various die interconnect structures can be formed after their corresponding die is integrated into the assembly. An example method 300 showing the formation of die interconnect structures at different stages will now be discussed.

FIG. 3 shows a flow chart of an example method 300 for manufacturing an electronic device (e.g., a semiconductor package, etc.). Example method 300 may, for example, share any or all features with any other example method discussed herein (e.g., example method 100 of FIG. 1 , example method 500 of FIG. 5 , example method 700 of FIG. 7 , etc.). The cross-sectional views shown in FIGS. 4A-4N show example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices in various aspects according to the present disclosure. FIGS. 4A-4N may, for example, show example electronic devices with the various blocks (or steps) of method 300 of FIG. 3 . FIGS. 3 and 4A-4N will now be discussed together. It should be noted that the order of the example blocks of method 300 may be varied without departing from the scope of the present disclosure.

The example method 300 may begin execution at block 305. The method 300 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, the method 300 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, etc. For another example, the method 300 may begin execution in response to an operator command to start. Additionally, for example, the method 300 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 300 may include receiving, manufacturing, and/or preparing a plurality of functional dies at block 310. Block 310 may include receiving, manufacturing, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 310 may share any or all features with block 110 of example method 100 shown in FIG. 1 and discussed herein. Various aspects of block 310 are presented in examples 400A-1 through 400A-4 shown in FIG. 4A.

Block 310 may, for example, include receiving a plurality of functional dies from an upstream manufacturing process at the same facility or geographic location. Block 310 may also, for example, include receiving a functional die from a supplier (e.g., from a foundry, etc.). Block 310 may also, for example, include forming any or all features of the plurality of functional dies.

In an example embodiment, block 310 may share any or all features with block 110 of example method 100 of FIG. 1 , but without first die interconnect structure 213 and second die interconnect structure 214. It will be appreciated that such die interconnect structures may be formed later in example method 300 (e.g., at block 347, etc.). Although not shown in FIG. 4A , each of functional dies 411-412 may include, for example, a die pad and/or under bump metallization structure on which such die interconnect structures may be formed.

The functional die 411-412 shown in FIG4A may, for example, share any or all features with the functional die 211-212 shown in FIG2A (e.g., not having the first die interconnect structure 213 and the second die interconnect structure 214). For example, but not limited to, the functional die 411-412 may include features of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare die or components, packaged die or components, etc.).

In general, block 310 may include receiving, manufacturing and/or preparing a plurality of functional dies. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such receiving, manufacturing and/or preparing, nor by any particular characteristics of such functional dies.

Example method 300 may include receiving, manufacturing, and/or preparing a connection die at block 315. Block 315 may include receiving, manufacturing, and/or preparing one or more connection dies in any of a variety of ways, non-limiting examples of which are provided herein. Block 315 may, for example, share any or all features with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example aspects of block 315 are presented in examples 400B-1 and 400B-2 shown in FIG. 4B.

The connecting die 416a and/or 416b (or wafers thereof) may, for example, include a connecting die interconnect structure 417. The connecting die interconnect structure 417 may include any of a variety of features. For example, the connecting die interconnect structure 417 and/or the formation of any aspect thereof may have any or all of the features of the connecting die interconnect structure 217 and/or its formation shown in FIGS. 2B-1 to 2B-2 and discussed herein.

The connecting dies 416a and/or 416b (or wafers thereof) may be formed in any of a variety of ways, non-limiting examples of which are provided herein, for example, with respect to the connecting dies 216a, 216b, and/or 216c of FIGS. 2B-1 to 2B-2.

Generally, block 315 may include receiving, manufacturing and/or preparing a connection die. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such receiving, manufacturing and/or preparing, nor by any particular characteristics of such connection die.

The example method 300 may include receiving, manufacturing, and/or preparing a first carrier at block 320. Block 320 may include receiving, manufacturing, and/or preparing a first carrier in any of a variety of ways, non-limiting examples of which are provided herein. Block 320 may, for example, share any or all features with other carrier receiving, manufacturing, and/or preparing steps discussed herein (e.g., with block 120 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 320 are presented in example 400C shown in FIG4C. For example, carrier 421 may share any or all features with carrier 221 of FIG2C. For another example, adhesive 423 may share any or all features with adhesive 223 of FIG2C. However, it should be noted that since adhesive 423 does not receive the die interconnect structure of the functional die (e.g., at block 325), adhesive 423 does not have to be as thick as adhesive 223.

Generally, block 320 may include receiving, manufacturing and/or preparing a first carrier. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular conditions for receiving a carrier, any particular manner for manufacturing a carrier, and/or any particular manner for preparing such a carrier for use.

The example method 300 may include coupling (or mounting) a functional die to a carrier (e.g., coupled to a top surface of a non-conductive carrier, coupled to a metal pattern on a top surface of a carrier, coupled to an RD structure on a top surface of a carrier, etc.) at block 325. Block 325 may include performing such coupling in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 325 may, for example, share any or all features with other die mounting steps discussed herein (e.g., at block 125 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 325 are presented in example 400D shown in FIG4D . Example 400D may share any or all features with example 200D of FIG2D . For example, functional dies 401-404 (e.g., examples of dies 411 and/or 412 ) may share any or all features with functional dies 201-204 (e.g., examples of dies 211 and/or 212 ) of FIG2D (e.g., die interconnect structures 213 and 214 do not extend into adhesive 223 ).

In example 400D, the respective active surfaces of the functional die 401-404 are shown coupled to the adhesive 423, but the scope of the present disclosure is not limited to such an orientation. In alternative embodiments, the respective inactive surfaces of the functional die 401-404 can be mounted to the adhesive 423 (e.g., where the functional die 404-404 can have through silicon vias or other structures to later connect to a connection die, etc.).

Typically, block 325 may include coupling the functional die to a carrier. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such coupling.

Example method 300 may include encapsulation at block 330. Block 330 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 330 may share any or all features with other encapsulations discussed herein (e.g., with block 130 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 330 are presented in example 400E shown in Figure 4E. For example, encapsulation material 426' (and/or its formation) can share any or all features with encapsulation material 226' (and/or its formation) of Figure 2E.

Typically, block 330 may include encapsulation. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 300 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 335. Block 335 may include performing such grinding (or any thinning or planarizing process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 335 may share any or all features with other grinding (or thinning or planarizing) discussed herein (e.g., with block 135 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 335 are presented in example 400F shown in Figure 4F. Example ground (or thinned or planarized, etc.) encapsulation material 426 (and/or its formation) may share any or all features with encapsulation material 226 (and/or its formation) of Figure 2F.

Typically, block 335 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such grinding (or thinning or planarizing).

The example method 300 may include attaching a second carrier at block 340. Block 340 may include attaching a second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 340 may share any or all features with any carrier attachment discussed herein (e.g., with block 140 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 340 are shown in example 400G shown in Figure 4G. The second carrier 431 (and/or its attachment) may, for example, share any or all features with the second carrier 231 of Figure 2G.

Typically, block 340 may include attaching a second carrier. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such attachment and/or the characteristics of any particular type of second carrier.

The example method 300 may include removing the first carrier at block 345. Block 345 may include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 345 may share any or all features with any carrier removal discussed herein (e.g., with block 145 of the example method 100 shown in FIG. 1 , etc.).

4H-1 shows various example aspects of block 345. For example, relative to example 400G, first carrier 421 has been removed.

Typically, block 345 may include removing the first carrier. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such removal.

The example method 300 may include forming an interconnect structure at block 347. Block 347 may include forming an interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 347 may share any or all features with other interconnect structure forming processes (or steps or blocks) discussed herein (e.g., block 110 of the example method 100 shown in FIG. 1 and discussed herein, etc.).

Various example aspects of block 347 are shown at example 400H-2 of FIG4H-2. The first die interconnect structure 413 (and/or its formation) of FIG4H-2 may share any or all features with the first die interconnect structure 213 (and/or its formation) of FIG2A. Similarly, the second die interconnect structure 414 (and/or its formation) of FIG4H-2 may share any or all features with the second die interconnect structure 214 (and/or its formation) of FIG2A.

Example embodiment 400H-2 includes a passivation layer 417 (or a repassivation layer). Although not shown in the example embodiment of FIG. 2A and/or other example embodiments presented herein, such example embodiments may also include such a passivation layer 417 (e.g., between functional dies and die interconnect structures and/or around the base of the die interconnect structures, between connecting dies and connecting die interconnect structures and/or around the base of the connecting die interconnect structures, etc.). For example, if such a passivation layer 417 has not been formed before block 347, block 347 may include forming such a passivation layer 417. It should be noted that passivation layer 417 may also be omitted.

In example embodiments, such as where the functional die are received or formed by an external inorganic dielectric layer, the passivation layer 417 may include an organic dielectric layer (eg, including any of the organic dielectric layers discussed herein).

The passivation layer 417 (and/or its formation) may include features of any passivation (or dielectric) layer (and/or its formation) discussed herein. The first die interconnect structure 413 and the second die interconnect structure 414 may be electrically connected to the functional dies 401 - 404 , for example, through corresponding holes in the passivation layer 417 .

Although the passivation layer 417 is shown on the molding layer 426 and the functional die 401-404, the passivation layer 417 may also be formed only on the functional die 401-404 (e.g., at block 310). In such example embodiments, an outer surface of the passivation layer 417 (e.g., an upward-facing surface of the passivation layer 417 in FIG. 4H-2) may be coplanar with a corresponding surface of the encapsulation material 426 (e.g., an upward-facing surface of the encapsulation material 426 in FIG. 4H-2).

Typically, block 347 may include forming an interconnect structure. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of such formation or any particular features of the interconnect structure.

The example method 300 may include attaching (or coupling or mounting) a connection die to a functional die at block 350. Block 350 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 350 may, for example, share any or all features with any die attachment discussed herein (e.g., with block 150 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 350 are presented in example 400I shown in FIG4I. Connecting die 416b, functional die 401-404, and/or connections between such die can, for example, share any or all features with connecting die 216b, functional die 201-204, and/or connections between such die of example 200I shown in FIG2I.

Typically, block 350 may include attaching a connection die to a functional die. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment and/or the features of any particular structure for performing such attachment.

The example method 300 may include underfilling the connection die at block 355. Block 355 may include performing such underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 355 may, for example, share any or all features with any underfill discussed herein (e.g., with block 155 and/or block 175 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 355 are presented in example 400J shown in FIG4J. For example, the underfill 423 (and/or its formation) of FIG4J may share any or all features with the underfill 223 (and/or its formation) of FIG2J. It should be noted that, as with any underfill discussed herein, various example embodiments may omit performing such an underfill.

Typically, block 355 may include underfilling the connection die. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or the characteristics of any particular type of underfill material.

The example method 300 may include removing the second carrier at block 360. Block 360 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 360 may share any or all features with any carrier removal discussed herein (e.g., with block 145 and/or block 160 of the example method 100 of FIG. 1 , with block 345, etc.).

Various example aspects of block 360 are presented in example 400K shown in Figure 4K. For example, comparing Figure 4K with Figure 4J, the second carrier 431 has been removed.

Typically, block 360 may include removing the second carrier. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such removal.

The example method 300 may include a singulation cut at block 365. Block 365 may include performing such a singulation cut in any of a variety of ways, non-limiting examples of which are discussed herein. Block 365 may, for example, share any or all features with any singulation cut discussed herein (e.g., as discussed with respect to block 165 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 365 are presented in example 400L shown in Figure 4L. The singulated cut structure (e.g., corresponding to the two encapsulation material portions 426a and 426b) can, for example, share any or all features with the singulated cut structure of Figure 2L (e.g., corresponding to the two encapsulation material portions 226a and 226b).

Typically, block 365 may include singulation. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of singulation.

The example method 300 may include mounting to a substrate at block 370. Block 370 may, for example, include performing such mounting (or coupling or attachment) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 370 may share any or all features with any mounting (or coupling or attachment) discussed herein (e.g., block 170 of the example method 100 shown in FIG. 1 , etc.).

Various example aspects of block 370 are presented in example 400M shown in Figure 4M. For example, substrate 488 (and/or attachment to such substrate 288) can share any or all features with substrate 288 (and/or attachment to such substrate 288) of example 200M of Figure 2M.

Typically, block 370 may include mounting to a substrate. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of mounting to a substrate or the features of any particular type of substrate.

The example method 300 may include, at block 375, performing an underfill between a substrate and a component (or module) mounted thereon at block 370. Block 375 may include performing the underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 375 may, for example, share any or all features with any of the underfill (or encapsulation) processes discussed herein (e.g., with respect to block 355, with respect to blocks 155 and 175 of the example method 100 of FIG. 1, etc.).

Various aspects of block 375 are presented in example 400N shown in FIG4N. Underfill 424 (and/or its formation) may, for example, share any or all features with example underfill 224 (and/or its formation) shown in example 200N of FIG2N. It should be noted that, as with any underfill discussed herein, underfill of block 375 may be skipped or may be performed at a different point in the method.

Typically, block 375 may include bottom filling between the substrate and the components mounted to the substrate. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of mounting to the substrate or the characteristics of any particular type of substrate.

The example method 300 may include performing a continued process at block 390. Such continued process may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 390 may share any or all features with block 190 of the example method 100 of FIG. 1 discussed herein.

For example, block 390 may include returning the execution flow of the example method 300 to any of its blocks. For another example, block 390 may include directing the execution flow of the example method 300 to any other method block (or step) discussed herein (e.g., example method 100 of FIG. 1 , example method 500 of FIG. 5 , example method 700 of FIG. 7 , etc.).

For example, block 390 may include interconnect structures 499 (eg, conductive balls, bumps, pillars, etc.) formed on a bottom surface of substrate 488 .

As another example, as shown in example 200O of FIG. 2O , example 200P of FIG. 2P , and example 200Q of FIG. 2Q , block 390 may include forming an encapsulation material and/or an underfill (or skipping forming an encapsulation material and/or an underfill).

In various example embodiments discussed herein, the functional die is mounted to a carrier before the connection die is attached to the functional die. The scope of the present disclosure is not limited to such an order of mounting. A non-limiting example will now be presented in which the connection die is mounted to a carrier before the connection die is attached to the functional die.

FIG. 5 shows a flow chart of an example method 500 for manufacturing an electronic device according to various aspects of the present disclosure. Example method 500 may, for example, share any or all features with any other example method discussed herein (e.g., example method 100 of FIG. 1 , example method 300 of FIG. 3 , example method 700 of FIG. 7 , etc.). The cross-sectional views shown in FIGS. 6A-6M show example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to various aspects of the present disclosure. FIGS. 6A-6M may, for example, show example electronic devices with the various blocks (or steps) of method 500 of FIG. 5 . FIGS. 5 and 6A-6M will now be discussed together. It should be noted that the order of the example blocks of method 500 may be varied without departing from the scope of the present disclosure.

Example method 500 may begin execution at block 505. Method 500 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, method 500 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, etc. For another example, method 500 may begin execution in response to an operator command to start. Additionally, for example, method 500 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 500 may include receiving, manufacturing and/or preparing multiple functional dies at block 510. Block 510 may include receiving, manufacturing and/or preparing multiple functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 510 may share any or all features with block 310 of example method 300 shown in FIG. 3 and discussed herein. Various aspects of block 510 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A. It should be noted that block 510 may also share any or all features with block 110 of example method 100 shown in FIG. 1 and discussed herein, for example.

Functional dies 611a and 612a (and/or their formations) as shown in many of FIGS. 6A-6M may, for example, share any or all features with functional dies 411 and 412 (and/or their formations) of FIG. 4A , with functional dies 211-212 (and/or their formations) of FIG. 2A , etc. For example, but not limited to, functional dies 611 and 612 may include features of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Generally, block 510 may include receiving, manufacturing and/or preparing a plurality of functional dies. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such receiving and/or manufacturing, nor by any particular characteristics of such functional dies.

Example method 500 may include receiving, manufacturing and/or preparing connection die at block 515. Block 515 may include receiving and/or manufacturing multiple connection die in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 515 may share any or all features with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example aspects of block 515 are presented in examples 200B-1 and 200B-7 shown in FIGS. 2B-1 to 2B-2. It should be noted that block 515 may also share any or all features with block 315 of example method 300 shown in FIG. 3 and discussed herein.

The connecting die 616b and connecting die interconnect structures 617 (and/or their formation) as shown in many of FIGS. 6A-6M may, for example, share any or all features with the connecting die 216b and connecting die interconnect structures 217 (and/or their formation) of FIGS. 2B-1 to 2B-2.

It should be noted that the connecting die interconnect structure 617 (and/or its formation) may, for example, share any or all features with the first die interconnect structure 213 (and/or its formation). For example, in an example embodiment, instead of forming a first die interconnect structure such as the first die interconnect structure 213 of FIG. 2A on the functional die 211/212, the same or similar connecting die interconnect structure 617 may be formed on the connecting die 616b.

Generally, block 515 may include receiving, manufacturing and/or preparing a connection die. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of such receiving, manufacturing and/or preparing or any particular characteristics of such connection die.

The example method 500 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure (or distribution structure) thereon at block 520. Block 520 may include performing such receiving, manufacturing, and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 520 may, for example, share any or all features with any or all carrier receiving, manufacturing, and/or preparation discussed herein (e.g., block 120 of example method 100 of FIG. 1 , block 320 of example method 300 of FIG. 3 , etc.). Various example aspects of block 520 are provided in example 600A of FIG. 6A .

As discussed herein, any or all of the carriers discussed herein may, for example, include only bulk material (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all of such carriers may also include a signal redistribution (RD) structure on (or in place of) the bulk material. Block 520 provides an example of receiving, manufacturing, and/or preparing such a carrier.

Block 520 may include forming RD structure 646a on block carrier 621a in any of a variety of ways, non-limiting examples of which are presented herein. In an example embodiment, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to a second die interconnect structure 614 (formed later), which will ultimately connect to functional die 611 and 612 (connected later).

6A shows an example in which the RD structure 646a includes three dielectric layers 647 and three conductive layers 648. Such number of layers is merely an example, and the scope of the present disclosure is not limited thereto. In another example embodiment, the RD structure 646a may include only a single dielectric layer 647 and a single conductive layer 648, two dielectric layers and two conductive layers, etc. The example redistribution (RD) structure 646a is formed on a bulk carrier 621a material.

The dielectric layer 647 may be formed of any of a variety of materials (e.g., Si ₃ N ₄ , SiO ₂ , SiON, PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 647 may be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 647 may be patterned, for example, to expose various surfaces (e.g., to expose the underlying traces or pads of the conductive layer 648, etc.).

The conductive layer 648 may be formed of any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 648 may be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 646a may, for example, include a conductor exposed at an outer surface thereof (e.g., exposed at a top surface of the example 600A). Such exposed conductors may, for example, be used for attachment (or formation) of a die interconnect structure (e.g., at block 525, etc.). In such embodiments, the exposed conductors may include a pad and may, for example, include an under bump metal (UBM) formed thereon to enhance attachment (or formation) of the die interconnect structure. Such under bump metal may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

Example redistributed structures and/or their formation are provided in U.S. Patent Application No. 14/823,689, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” filed on August 11, 2015; and U.S. Patent Application No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF,” each of which is hereby incorporated by reference in its entirety.

The redistribution structure 646a may, for example, perform fan-out redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the die interconnect structures 614 (to be formed) to a position outside the footprint of the functional dies 611 and 612 to be attached via such die interconnect structures 614. For another example, the redistribution structure 646a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the die interconnect structures 614 (to be formed) to a position within the footprint of the connection die 616b (to be connected) and/or to a position inside the footprint of the functional dies 611 and 612 (to be connected). The redistribution structure 646a may also, for example, provide connectivity for various signals between the functional die 611 and 612 (eg, in addition to the connections provided by the connection die 616b).

In various example embodiments, block 520 may include forming only a first portion 646a of the entire RD structure 646, wherein a second portion 646b of the entire RD structure 646 may be formed later (eg, at block 570).

Generally, block 520 may include receiving, manufacturing and/or preparing a carrier having a signal redistribution (RD) structure thereon. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of manufacturing such carriers and/or signal redistribution structures or any particular characteristics of such carriers and/or signal redistribution structures.

The example method 500 may include forming a high-grain interconnect structure on the RD structure (eg, as provided at block 520) at block 525. Block 525 may include forming a high-grain interconnect structure on the RD structure in any of a variety of ways, non-limiting examples of which are provided herein.

Block 525 may, for example, share any or all features (e.g., second die interconnect structure formation features, etc.) with any or all functional die reception, fabrication, and/or preparation discussed herein (e.g., block 110 and the formation of the second die interconnect structure 214 and/or the formation of the first die interconnect structure 213 with respect to the example method 100 of FIG. 1 , block 347 and the formation of the second die interconnect structure 414 with respect to the example method 347 of FIG. 3 , etc.).

Various example aspects of block 525 are provided in example 600B of Figure 6B. The high interconnect structure 614 (and/or its formation) can share any or all features with the second die interconnect structure 214 (and/or its formation) of Figure 2A and/or with the second die interconnect structure 414 (and/or its formation) of Figure 4H-2.

In general, block 525 may include forming a high-grain interconnect structure on an RD structure (e.g., as provided at block 520). Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of forming such a high-grain interconnect structure and/or the features of any particular type of high interconnect structure.

Example method 500 may include mounting a connection die to an RD structure (e.g., as provided at block 520) at block 530. Block 530 may include performing such mounting (or attachment or coupling) in any of a variety of ways, non-limiting examples of which are provided herein. Block 530 may, for example, share any or all features with any die attachment discussed herein (e.g., block 325 of example method 300 shown in FIG. 3 and discussed herein, block 125 of example method 100 shown in FIG. 1 and discussed herein, etc.). Various example aspects of block 530 are presented in example 600C shown in FIG. 6C.

Block 530 may, for example, include attaching the back side of the connection die 616b to the RD structure 646a using a die attach adhesive (e.g., tape, liquid, paste, etc.). Although the connection die 616b is shown in FIG. 6C as being coupled to a dielectric layer of the RD structure 646a, in other example embodiments, the back side of the connection die 616b may be coupled to a conductive layer (e.g., to enhance heat dissipation, provide additional structural support, etc.).

In addition, as discussed herein, any connection die discussed herein can be double-sided. In such example embodiments, the backside interconnect structure can be electrically connected to a corresponding interconnect structure (e.g., pad, connection pad, bump, etc.) of the RD structure 646a.

Generally, block 530 may include mounting a connection die to an RD structure (eg, as provided at block 520). Thus, the scope of the present disclosure should not be limited by the features of any particular manner of mounting a connection die.

Example method 500 may include encapsulation at block 535. Block 535 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Block 535 may, for example, share any or all features with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of example method 100 of FIG. 1 , with block 330 of example method 300 of FIG. 3 , etc.). Various example aspects of block 535 are presented at FIG. 6D .

Block 535 may, for example, include performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to singulation of the individual modules. Referring to example embodiment 600D shown in FIG. 6D , encapsulation material 651′ may cover at least a portion (or all) of the top surface of RD structure 646a, tall pillars 614, connecting die interconnect structures 617, the top surface (or active surface or front face) of connecting die 616b, and the side surface of connecting die 616b.

Although encapsulation material 651' (as shown in FIG. 6D) is shown as covering the top ends of tall interconnect structures 614 and the top ends of connecting die interconnect structures 617, any or all of these ends may be exposed from encapsulation material 651' (as shown in FIG. 6E). Block 535 may, for example, include initially forming encapsulation material 651' with the top ends of various interconnects exposed or protruding (e.g., using film-assisted molding techniques, die-seal molding techniques, etc.). Alternatively, block 535 may include forming encapsulation material 651' followed by a thinning (or planarization or grinding) process (e.g., performed at block 540) to thin encapsulation material 651' sufficiently to expose the top surfaces of any or all of tall interconnect structures 614 and connecting die interconnect structures 617, etc.

In general, block 535 may include encapsulation. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or the characteristics of any particular type of encapsulation material or its configuration.

Example method 500 may include grinding encapsulation materials and/or various interconnect structures at block 540. Block 540 may include performing such grinding (or any thinning or planarization) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 540 are presented in example 600E shown in FIG. 6E. Block 540 may, for example, share any or all features with other grinding (or thinning or planarization) blocks (or steps) discussed herein.

As discussed herein, in various example embodiments, the encapsulation material 651' may be initially formed to a thickness greater than that ultimately desired, and/or the tall interconnect structures 614 and the connecting die interconnect structures 617 may be initially formed to a thickness greater than that ultimately desired. In such example embodiments, block 540 may be performed to grind (or otherwise thin or planarize) the encapsulation material 651', the tall interconnect structures 614, and/or the connecting die interconnect structures 617. In the example 600E shown in FIG6E, the encapsulation material 651, the tall interconnect structures 614, and/or the connecting die interconnect structures 617 have been ground to produce the encapsulation material 651 and the interconnect structures 613 and 617 (as shown in FIG6E). The top surface of the ground encapsulation material 651, the top surface of the high interconnect structure 614, and/or the top surface of the connecting die interconnect structure 617 can be, for example, coplanar.

It should be noted that in various example embodiments, the top surface of the high interconnect structure 614 and/or the top surface of the connecting die interconnect structure 617 can protrude from the top surface of the encapsulation material 651, such as by utilizing a chemical or mechanical process that thins the encapsulation material 651 more than the interconnect structures 614 and/or 617, utilizing a film-assisted and/or sealing molding process at block 535, etc.

Typically, block 540 may include grinding (or thinning or planarizing) encapsulation materials and/or various interconnect structures. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 500 may include attaching (or coupling or mounting) a functional die to a high interconnect structure and connecting the die interconnect structure at block 545. Block 545 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 545 may, for example, share any or all features with any die attach process discussed herein. Various example aspects of block 545 are presented in example 600F shown in FIG. 6F.

For example, the die interconnect structures (e.g., pads, bumps, etc.) of the first functional die 611a can be mechanically and electrically connected to the corresponding high interconnect structures 614 and to the corresponding connecting die interconnect structures 617. Similarly, the die interconnect structures (e.g., pads, bumps, etc.) of the second functional die 612a can be mechanically and electrically connected to the corresponding high interconnect structures 614 and to the corresponding connecting die interconnect structures 617.

Such interconnect structures can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In an example embodiment, the high-grain interconnect structure 614, the connecting grain interconnect structure 617 and/or the corresponding interconnect structures of the first functional grain 611a and the second functional grain 612a can include a solder cap (or other solder structure) that can be reflowed to perform the connection. Such solder caps can be reflowed, for example, by mass reflow, thermal compression bonding (TCB), etc. In another example embodiment, the connection can be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without using solder. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, filed on December 8, 2015, entitled “Transient Interface Gradient Bonding for Metal Bonds,” and U.S. Patent Application No. 14/989,455, filed on January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” each of which is hereby incorporated by reference in its entirety. The functional die interconnect structures may be attached to the high interconnect structures 614 and the connecting die interconnect structures 617 using any of a variety of techniques (eg, mass reflow, thermal compression bonding (TCB), direct metal-to-metal metal bonding, conductive adhesives, etc.).

As shown in example embodiment 600F, the first connecting die interconnect structure 617 of the connecting die 616b is connected to the corresponding interconnect structure of the first functional die 611a, and the second connecting die interconnect structure 617 of the connecting die 616b is connected to the corresponding interconnect structure of the second functional die 612a. When connected, the connecting die 616b provides electrical connection between the various die interconnect structures of the first functional die 611a and the second functional die 612a via the RD structure 298 of the connecting die 616b (e.g., as shown in example 200B-4 of FIG. 2B-1, etc.).

In the example 600F shown in FIG. 6F , the height of the high interconnect structure 614 may be, for example, equal to (or greater than) the combined height of the connecting die interconnect structure 217 and the supporting layer 290 b of the connecting die 616 b and the adhesive or other member used to attach the connecting die 616 b to the RD structure 646 a.

In general, block 545 may include attaching (or coupling or mounting) a functional die to a high interconnect structure and connecting die interconnect structures. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment or the features of any particular type of attachment structure.

Example method 500 may include bottom filling the functional die at block 550. Block 550 may include performing such bottom filling in any of a variety of ways, non-limiting examples of which are provided herein. Block 550 may, for example, share any or all features with any bottom filling discussed herein (e.g., with block 155 and/or block 175 of example method 100 of FIG. 1 , with block 355 and/or block 375 of example method 300 of FIG. 3 , etc.). Various example aspects of block 550 are presented in example 600G shown in FIG. 6G .

It should be noted that an underfill may be applied between the functional dies 611a and 612a and the encapsulation material 651. In the context of utilizing a pre-applied underfill (PUF), such a PUF may be applied to the functional dies 611a and 612a, and/or to the top exposed ends of the encapsulation material 651 and/or the interconnect structures 614 and 617 prior to coupling the functional dies.

After the attachment performed at block 545, block 550 may include forming an underfill (e.g., a capillary underfill, an injected underfill, etc.). As shown in example embodiment 600G of FIG. 6G, an underfill material 661 (e.g., any underfill material discussed herein, etc.) may fully or partially cover the bottom surfaces of the functional dies 611a and 612a (e.g., oriented as shown in FIG. 6G), and/or at least a portion (if not all) of the side surfaces of the functional dies 611a and 612a. The underfill material 661 may also, for example, cover a majority (or all) of the top surface of the encapsulation material 651. The underfill material 661 may also, for example, surround the corresponding interconnect structures of the functional dies 611a and 612a to which the high interconnect structures 614 and the connecting die interconnect structures 617 are attached. In example embodiments where ends of the tall interconnect structures 614 and/or the connecting die interconnect structures 617 protrude from the encapsulation material 651, the underfill material 661 may also surround such protruding portions.

It should be noted that in various example implementations of the example method 500, the underfill performed at block 550 may be skipped. For example, underfilling the functional die may be performed at another block (e.g., at block 555, etc.). For another example, such underfill may be omitted entirely.

Typically, block 550 may include underfilling the functional die. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or the characteristics of any particular type of underfill material.

Example method 500 may include encapsulation at block 555. Block 555 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 555 may, for example, share any or all features with other encapsulation blocks (or steps) discussed herein (e.g., with block 535, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, etc.).

Various example aspects of block 555 are presented in example 600H shown in Figure 6H. For example, encapsulation material 652' (and/or its formation) can share any or all features with encapsulation material 226' (and/or its formation) of Figure 2E, with encapsulation material 426 (and/or its formation) of Figure 4K, with encapsulation material 651 (and/or its formation) of Figure 6D, etc.

The encapsulation material 652' covers the top surface of the encapsulation material 651, covers the side surfaces of the bottom fill 661, covers at least some (if not all) of the side surfaces of the functional dies 611a and 612b, covers the top surfaces of the functional dies 611a and 612b, etc.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226' of FIG. 2E, etc.), encapsulation material 652' need not be initially formed to cover the top surfaces of functional die 611a and 612a. For example, block 555 may include forming encapsulation material 652' using film-assisted molding, sealing molding, etc.

In general, block 555 may include encapsulation. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 500 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 560. Block 560 may include performing such grinding (or any thinning or planarizing process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 560 may, for example, share any or all features with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of example method 100 of FIG. 1 , with block 335 of example method 300 of FIG. 3 , with block 540, etc.).

Various example aspects of block 560 are presented in example 600I shown in Fig. 6I. Example ground (or thinned or planarized, etc.) encapsulation material 652 (and/or its formation) can share any or all features with encapsulation material 226 (and/or its formation) of Fig. 2F, with encapsulation material 426 (and/or its formation) of Fig. 4F, with encapsulation material 651 (and/or its formation) of Fig. 6E, etc.

Block 560 may, for example, include grinding the encapsulation material 652 and/or the functional die 611a and 612a so that the top surface of the encapsulation material 652 is coplanar with the top surface of the functional die 611a and/or with the top surface of the functional die 612a.

Typically, block 560 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such grinding (or thinning or planarizing).

Example method 500 may include removing the carrier at block 565. Block 565 may include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 565 may share any or all features with any of the carrier removal processes discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1 , with blocks 345 and/or 360 of example method 300 of FIG. 3 , etc.). Various example aspects of block 565 are shown in example 600J of FIG. 6J .

For example, example 600J of FIG. 6J shows that first carrier 621a is removed (e.g., compared to example 600I of FIG. 6I). Block 565 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, stripping, shearing, thermal release or laser release, etc.). For another example, if an adhesive layer was utilized during the formation of RD structure 646a at block 520, for example, then block 565 may include removing the adhesive layer.

It should be noted that in various example embodiments, a second carrier (e.g., coupled to encapsulation material 652 and/or coupled to functional die 611a and 612a) may be utilized as shown and discussed herein with respect to example methods 100 and 300 of FIGS. 1 and 3. In other example embodiments, various tool structures may be utilized in place of a carrier.

Typically, block 565 may include removing the carrier. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of removing the carrier or the features of any particular type of carrier.

Example method 500 may include a completion signal redistribution (RD) structure at block 570. Block 570 may include any of a variety of ways to complete the RD structure, non-limiting examples of which are provided herein. Block 570 may, for example, share any or all features with block 520 (e.g., with respect to the RD structure formation aspects of block 520). Various aspects of block 570 are shown in example 600K shown in FIG. 6K.

As discussed herein, for example, with respect to block 520, the carrier may have been (but need not have been) received (or manufactured or prepared) with only a portion of the desired RD structure formed. In such an example scenario, block 570 may include completing the formation of the RD structure.

6K , block 570 may include forming a second portion 646b of the RD structure on a first portion 646a of the RD structure (e.g., the first portion 646a of the RD structure that has been received or manufactured or prepared at block 520). Block 570 may, for example, include forming the second portion 646b of the RD structure in the same manner as the first portion 646a of the RD structure is formed.

It should be noted that in various embodiments, the first portion 646a of the RD structure and the second portion 646b of the RD structure can be formed using different materials and/or different processes. For example, the first portion 646a of the RD structure can be formed using an inorganic dielectric layer, and the second portion 646b of the RD structure can be formed using an organic dielectric layer. For another example, the first portion 646a of the RD structure can be formed to have a finer spacing (or a finer trace, etc.), and the second portion 646b of the RD structure can be formed to have a coarser spacing (or a coarser trace, etc.). For another example, the first portion 646a of the RD structure can be formed using a back-end of line (BEOL) semiconductor wafer manufacturing (fab) process, and the second portion 646b of the RD structure can be formed using a post-fab electronic device packaging process. Additionally, the first portion 646a of the RD structure and the second portion 646b of the RD structure may be formed at different geographical locations.

Like the first portion 646a of the RD structure, the second portion 646b of the RD structure may have any number of dielectric layers and/or conductive layers.

As discussed herein, interconnect structures may be formed on RD structure 646b. In such example embodiments, block 565 may include forming an under bump metallization (UBM) on the exposed pad to enhance the formation (or attachment) of such interconnect structures.

Generally, block 570 may include completing a signal redistribution (RD) structure. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of forming a signal redistribution structure or the features of any particular type of signal distribution structure.

Example method 500 may include forming an interconnect structure on the redistribution structure at block 575. Block 575 may include forming the interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 575 may share any or all features with any interconnect structure formation discussed herein.

Various example aspects of block 575 are presented in example 600L shown in FIG6L. Example interconnect structure 652 (e.g., package interconnect structure, etc.) can include features of any of a variety of interconnect structures. For example, package interconnect structure 652 can include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive posts, leads, etc.

Block 575 may include forming interconnect structures 652 in any of a variety of ways. For example, interconnect structures 652 may be adhered and/or printed on RD structures 646b (e.g., adhered and/or printed to their corresponding pads 651 and/or UBMs) and then reflowed. For another example, interconnect structures 652 (e.g., conductive balls, conductive bumps, pillars, leads, etc.) may be preformed prior to attachment and then attached to RD structures 646b (e.g., attached to their corresponding pads 651) by, for example, reflowing, electroplating, gluing with epoxy, wire bonding, etc.

It should be noted that, as described above, pad 651 of RD structure 646b may be formed by under bump metallization (UBM) or any metallization to assist in the formation (e.g., building, attaching, coupling, deposition, etc.) of interconnect structure 652. For example, such UBM formation may be performed at block 570 and/or block 575.

Typically, block 575 may include forming an interconnect structure on a redistribution structure. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of forming such an interconnect structure or any particular features of the interconnect structure.

The example method 500 may include a singulation cut at block 580. Block 580 may include performing such a singulation cut in any of a variety of ways, non-limiting examples of which are discussed herein. Block 580 may, for example, share any or all features with any singulation cut discussed herein (e.g., as discussed with respect to block 165 of the example method 100 of FIG. 1 , as discussed with respect to block 365 of the example method 300 of FIG. 3 , etc.).

Various example aspects of block 580 are presented in example 600M shown in FIG6M. The singulated cut structure (e.g., corresponding to encapsulation material portion 652a) can, for example, share any or all features with the singulated cut structure of FIG2L (e.g., corresponding to two encapsulation material portions 226a and 226b), with the singulated cut structure of FIG4L (e.g., corresponding to two encapsulation material portions 426a and 426b), etc.

Typically, block 580 may include singulation. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of singulation.

The example method 500 may include performing a continuation process at block 590. Such continuation process may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 590 may share any or all features with block 190 of the example method 100 of FIG. 1 , with block 390 of the example method 300 of FIG. 3 , and so on.

For example, block 590 may include returning the execution flow of the example method 500 to any of its blocks. For another example, block 590 may include directing the execution flow of the example method 500 to any other method block (or step) discussed herein (e.g., example method 100 of FIG. 1 , example method 300 of FIG. 3 , example method 700 of FIG. 7 , etc.).

As another example, as shown in example 200O of FIG. 2O , example 200P of FIG. 2P , and example 200Q of FIG. 2Q , block 590 may include forming an encapsulation material and/or an underfill (or skipping forming an encapsulation material and/or an underfill).

As discussed herein, the functional die and the connection die can be mounted to the substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in FIGS. 9 and 10 .

FIG. 7 shows a flow chart of an example method 700 for manufacturing an electronic device according to various aspects of the present disclosure. Example method 700 may, for example, share any or all features with any other example method discussed herein (e.g., example method 100 of FIG. 1 , example method 300 of FIG. 3 , example method 500 of FIG. 5 , etc.). The cross-sectional views shown in FIGS. 8A-8N show example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to various aspects of the present disclosure. FIGS. 8A-8N may, for example, show example electronic devices with the various blocks (or steps) of method 700 of FIG. 7 . FIGS. 7 and 8A-8N will now be discussed together. It should be noted that the order of the example blocks of method 700 may be varied without departing from the scope of the present disclosure. In an example implementation, the method 700 of FIG. 7 may be considered similar to the method of FIG. 5 , but with the addition of block 742 for forming a second redistribution structure.

Example method 700 may begin execution at block 705. Method 700 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, method 700 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, etc. For another example, method 700 may begin execution in response to an operator command to start. Additionally, for example, method 700 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 700 may include receiving, manufacturing and/or preparing multiple functional dies at block 710. Block 710 may include receiving, manufacturing and/or preparing multiple functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 710 may share any or all features with block 510 of example method 500 shown in FIG. 5 and discussed herein, with block 310 of example method 300 shown in FIG. 3 and discussed herein, and the like. Various aspects of block 710 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A. It should be noted that block 710 may also share any or all features with, for example, block 110 of example method 100 shown in FIG. 1 and discussed herein.

Functional dies 811a and 812a (and/or formations thereof) as shown in many of FIGS. 8A-8N may, for example, share any or all features with functional dies 611a and 612a (and/or formations thereof), functional dies 411 and 412 (and/or formations thereof), functional dies 211 and 212 (and/or formations thereof), etc. For example, but not limited to, functional dies 811a and 812a may include features of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

In general, block 710 may include receiving, manufacturing and/or preparing a plurality of functional dies. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such receiving and/or manufacturing, nor by any particular characteristics of such functional dies.

Example method 700 may include receiving, manufacturing and/or preparing a connection die at block 715. Block 715 may include receiving, manufacturing and/or preparing a plurality of connection die in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 715 may share any or all features with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example aspects of block 715 are presented in examples 200B-1 and 200B-7 shown in FIGS. 2B-1 to 2B-2. It should be noted that block 715 may also share any or all features with, for example, block 315 of example method 100 shown in FIG. 3 and discussed herein, block 515 of example method 500 shown in FIG. 5, and the like.

The connecting die 816b and connecting die interconnect structures 817 (and/or their formation) as shown in many of FIGS. 8A-8N may, for example, share any or all features with the connecting die 216b and connecting die interconnect structures 217 (and/or their formation) of FIGS. 2B-1 to 2B-2.

It should be noted that the connecting die interconnect structure 817 (and/or its formation) may, for example, share any or all features with the first die interconnect structure 213 (and/or its formation). For example, in an example embodiment, instead of forming a first die interconnect structure such as the first die interconnect structure 213 of FIG. 2A on the functional die 211/212, the same or similar connecting die interconnect structure 817 may be formed on the connecting die 816b.

Generally, block 715 may include receiving, manufacturing and/or preparing a connection die. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of such receiving, manufacturing and/or preparing or any particular characteristics of such connection die.

The example method 700 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure (or distribution structure) thereon at block 720. Block 720 may include performing such receiving, manufacturing, and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 720 may, for example, share any or all features with any or all carrier receiving, manufacturing, and/or preparation discussed herein (e.g., block 120 with respect to example method 100 of FIG. 1 , block 320 with respect to example method 300 of FIG. 3 , block 520 with respect to example method 500 of FIG. 5 , etc.). Various example aspects of block 720 are provided in example 800A of FIG. 8A .

As discussed herein, any or all of the carriers discussed herein may, for example, include only bulk material (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all of such carriers may also include a signal redistribution (RD) structure on (or in place of) the bulk material. Block 720 provides an example of receiving, manufacturing, and/or preparing such a carrier.

Block 720 may include forming RD structure 846a on block carrier 821a in any of a variety of ways, non-limiting examples of which are presented herein. In an example embodiment, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to vertical interconnect structures 814 (formed later), which will ultimately connect to second redistribution structures 896 and/or functional die 811 and 812 (connected later). Thus, RD structure 846a may be coreless. However, it should be noted that in various alternative embodiments, RD structure 846a may be a cored structure.

8A shows an example in which the RD structure 846a includes three dielectric layers 847 and three conductive layers 848. Such number of layers is merely an example, and the scope of the present disclosure is not limited thereto. In another example embodiment, the RD structure 846a may include only a single dielectric layer 847 and a single conductive layer 848, two dielectric layers and two conductive layers, etc. The example redistribution (RD) structure 846a is formed on a bulk carrier 821a material.

The dielectric layer 847 may be formed of any of a variety of materials (e.g., Si ₃ N ₄ , SiO ₂ , SiON, PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 847 may be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 847 may be patterned, for example, to expose various surfaces (e.g., to expose the underlying traces or pads of the conductive layer 848, etc.).

The conductive layer 848 may be formed of any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 848 may be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 846a may, for example, include a conductor exposed at an outer surface thereof (e.g., exposed at a top surface of the example 800A). Such exposed conductors may, for example, be used for attachment (or formation) of a die interconnect structure (e.g., at block 725, etc.). In such embodiments, the exposed conductors may include a pad and may, for example, include an under bump metal (UBM) formed thereon to enhance attachment (or formation) of a die interconnect structure. Such under bump metal may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

Example redistributed structures and/or their formation are provided in U.S. Patent Application No. 14/823,689, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” filed on August 11, 2015; and U.S. Patent Application No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF,” each of which is hereby incorporated by reference in its entirety.

The redistribution structure 846a may, for example, perform fan-out redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to-be-formed) vertical interconnect structures 814 to a location outside the footprint of the functional dies 811 and 812 to be attached via such vertical interconnect structures 814. For another example, the redistribution structure 846a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to-be-formed) vertical interconnect structures 814 to a location within the footprint of the (to-be-connected) connection die 816b and/or to a location within the footprint of the (to-be-connected) functional dies 811 and 812. The redistribution structure 846a may also, for example, provide connectivity for various signals between the functional die 811 and 812 (eg, in addition to the connections provided by the connection die 816b).

In various example embodiments, block 720 may include forming only a first portion 846a of the entire RD structure 846, wherein a second portion 846b of the entire RD structure 846 may be formed later (eg, at block 770).

Generally, block 720 may include receiving, manufacturing and/or preparing a carrier having a signal redistribution (RD) structure thereon. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of manufacturing such carriers and/or signal redistribution structures or any particular characteristics of such carriers and/or signal redistribution structures.

Example method 700 may include forming a vertical interconnect structure on an RD structure (e.g., as provided at block 720) at block 725. Block 725 may include forming a vertical interconnect structure on the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. It should be noted that the vertical interconnect structure may also be referred to herein as a high bump, a high pillar, a high pillar, a die interconnect structure, a functional die interconnect structure, etc.

Block 725 may, for example, share any or all features (e.g., second die interconnect structure formation features, etc.) with any or all functional die reception, fabrication, and/or preparation discussed herein (e.g., block 110 and the formation of the second die interconnect structure 214 and/or the formation of the first die interconnect structure 213 with respect to the example method 100 of FIG. 1 , block 347 and the formation of the second die interconnect structure 414 with respect to the example method 347 of FIG. 3 , block 525 with respect to the example method 500 of FIG. 5 , etc.).

Various example aspects of block 725 are provided in example 800B of FIG8B . The vertical interconnect structure 814 (and/or its formation) can share any or all features with the second die interconnect structure 214 (and/or its formation) of FIG2A and/or with the second die interconnect structure 414 (and/or its formation) of FIG4H-2 . In addition, the vertical interconnect structure 814 (and/or its formation) can share any or all features with the interconnect structure 614 (and/or its formation) of FIG6B .

In general, block 725 may include forming a vertical interconnect structure on an RD structure (e.g., as provided at block 720). Thus, the scope of the present disclosure should not be limited by the features of any particular manner of forming such a vertical interconnect structure and/or the features of any particular type of vertical interconnect structure.

Example method 700 may include mounting a connection die to an RD structure (e.g., as provided at block 720) at block 730. Block 730 may include performing such mounting (or attachment or coupling) in any of a variety of ways, non-limiting examples of which are provided herein. Block 730 may, for example, share any or all features with any die attachment discussed herein (e.g., block 530 of example method 500 shown in FIG. 5 and discussed herein, block 325 of example method 300 shown in FIG. 3 and discussed herein, block 125 of example method 100 shown in FIG. 1 and discussed herein, etc.). Various example aspects of block 730 are presented in example 800C shown in FIG. 8C.

Block 730 may, for example, include attaching the back side of the connection die 816b to the RD structure 846a using a die attach adhesive (e.g., tape, liquid, paste, etc.). Although the connection die 816b is shown in FIG. 8C as being coupled to a dielectric layer of the RD structure 846a, in other example embodiments, the back side of the connection die 816b may be coupled to a conductive layer (e.g., to enhance heat dissipation, provide additional structural support, etc.).

In addition, as discussed herein, any connection die discussed herein can be double-sided. In such example embodiments, the backside interconnect structure can be electrically connected to a corresponding interconnect structure (e.g., pad, connection pad, bump, etc.) of the RD structure 846a.

Generally, block 730 may include mounting a connection die to an RD structure (eg, as provided at block 720). Thus, the scope of the present disclosure should not be limited by the features of any particular manner of mounting a connection die.

Example method 700 may include encapsulation at block 735. Block 735 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 735 may, for example, share any or all features with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of example method 100 of FIG. 1 , with block 330 of example method 300 of FIG. 3 , with block 530 of example method 500 of FIG. 5 , etc.). Various example aspects of block 735 are presented at FIG. 8D .

Block 735 may, for example, include performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to singulation of the individual modules. Referring to example embodiment 800D shown in FIG. 8D , encapsulation material 851′ may cover at least a portion (or all) of the top surface of RD structure 846a, vertical interconnect structure 814, connecting die interconnect structure 817, the top surface (or active surface or front surface) of connecting die 816b, and the side surface surface of connecting die 816b.

Although encapsulation material 851' (as shown in FIG. 8D) is shown as covering the top ends of vertical interconnect structures 814 and the top ends of connecting die interconnect structures 817, any or all of these ends may be exposed from encapsulation material 851' (as shown in FIG. 8E). Block 735 may, for example, include initially forming encapsulation material 851' with the top ends of various interconnects exposed or protruding (e.g., using film-assisted molding techniques, die-seal molding techniques, etc.). Alternatively, block 735 may include forming encapsulation material 851' followed by a thinning (or planarization or grinding) process (e.g., performed at block 740) to thin encapsulation material 851' sufficiently to expose the top surfaces of any or all of vertical interconnect structures 814 and connecting die interconnect structures 817, etc.

In general, block 735 may include encapsulation. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or the characteristics of any particular type of encapsulation material or its configuration.

Example method 700 may include grinding encapsulation materials and/or various interconnect structures at block 740. Block 740 may include performing such grinding (or any thinning or planarization) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 740 are presented in example 800E shown in FIG. 8E. Block 740 may, for example, share any or all features with other grinding (or thinning or planarization) blocks (or steps) discussed herein.

As discussed herein, in various example embodiments, the encapsulation material 851' may be initially formed to a thickness greater than that ultimately desired, and/or the vertical interconnect structures 814 and the connecting die interconnect structures 817 may be initially formed to a thickness greater than that ultimately desired. In such example embodiments, block 740 may be performed to grind (or otherwise thin or planarize) the encapsulation material 851', the vertical interconnect structures 814, and/or the connecting die interconnect structures 817. In the example 800E shown in FIG8E, the encapsulation material 851, the vertical interconnect structures 814, and/or the connecting die interconnect structures 817 have been ground to produce the encapsulation material 851 and the vertical interconnect structures 814 and the connecting die interconnect structures 817 (as shown in FIG8E). The top surface of the ground encapsulation material 851, the top surface of the vertical interconnect structure 814, and/or the top surface of the connecting die interconnect structure 817 can be, for example, coplanar.

It should be noted that in various example embodiments, the top surface of the vertical interconnect structure 814 and/or the top surface of the connecting die interconnect structure 817 may protrude from the top surface of the encapsulation material 851, such as by utilizing a chemical or mechanical process that thins the encapsulation material 851 more than the vertical interconnect structure 814 and/or the connecting die interconnect structure 817, utilizing a film-assisted and/or sealing molding process at block 735, etc.

Typically, block 740 may include grinding (or thinning or planarizing) encapsulation materials and/or various interconnect structures. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

The example method 700 may include forming a second signal redistribution (RD) structure (or distribution structure) at block 742. Block 742 may include performing such formation in any of a variety of ways, non-limiting examples of which are provided herein.

Block 742 may, for example, share any or all features with any or all signal distribution structures discussed herein (e.g., block 120 with respect to example method 100 of FIG. 1 , block 320 with respect to example method 300 of FIG. 3 , block 520 with respect to example method 500 of FIG. 5 , block 720, etc.). Various example aspects of block 742 are provided in example 800F of FIG. 8F .

As discussed herein, the example structure 800E resulting from block 740 may include top surfaces including a top surface of encapsulation material 851, exposed top surfaces of vertical interconnect structures 814 and/or connecting die interconnect structures 817, exposed top side surfaces of vertical interconnect structures 814 and/or connecting die interconnect structures 817, etc. Block 742 may, for example, include forming a second signal redistribution structure on any or all of such surfaces.

Block 742 may include forming a second RD structure on top of structure 800E in any of a variety of ways, for example, non-limiting examples of which are presented herein. In an example embodiment, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections between vertical interconnect structures 814 and/or connecting die interconnect structures 817 laterally and/or vertically to electrical components mounted therein (e.g., to semiconductor dies such as die 811 and 812, passive electrical components, shielding components, etc.). FIG. 8F illustrates an example in which a second RD structure 896 includes three dielectric layers 897 and three conductive layers 898. Such number of layers is merely an example, and the scope of the present disclosure is not limited thereto. In another example embodiment, the second RD structure 896 may include only a single dielectric layer 897 and a single conductive layer 898, two dielectric layers and two conductive layers, etc. Therefore, the second RD structure 896 may be coreless. However, it should be noted that in various alternative embodiments, the second RD structure 896 may be a cored structure. In another example embodiment, the second redistribution (or distribution) structure 896 may include only a single vertical metal structure (e.g., one or more layers), such as an under bump metallization structure.

The dielectric layer 897 may be formed of any of a variety of materials (e.g., Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy resin or other insulating materials). The dielectric layer 897 may be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 897 may be patterned, for example, to expose various surfaces (e.g., to expose the underlying traces or pads of the conductive layer 898, etc.).

The conductive layer 898 may be formed of any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 898 may be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The second RD structure 896 may, for example, include a conductor exposed at its outer surface (e.g., exposed at the top surface of the example 800F). Such exposed conductors may, for example, be used for attachment (or formation) of electrical components and/or their attachment structures (e.g., at blocks 745, etc.). Such exposed conductors may, for example, include pad structures, under-bump metallization structures, etc. In such embodiments, the exposed conductors may include pads and may, for example, include under-bump metallization (UBM) formed thereon to enhance the attachment (or formation) of components and/or their interconnect structures. Such under-bump metallization may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

Example redistributed structures and/or their formation are provided in U.S. Patent Application No. 14/823,689, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” filed on August 11, 2015; and U.S. Patent Application No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF,” each of which is hereby incorporated by reference in its entirety.

The second RD structure 896 may, for example, perform a fan-out redistribution of at least some electrical connections or signals, moving the electrical connections or signals laterally from at least a portion of the connecting die interconnect structure 817 and/or the vertical interconnect structure 814 (attached to the bottom surface of the second RD structure 896) to a location outside the footprint of the connecting die interconnect structure 817 (or the connecting die 816 b) and/or the vertical interconnect structure 814. For another example, the second RD structure 896 may perform a fan-in redistribution of at least some electrical connections or signals, moving the electrical connections or signals laterally from at least a portion of the connecting die interconnect structure 817 and/or the vertical interconnect structure 814 to a location inside the footprint of the connecting die interconnect structure 817 (or the connecting die 816 b) and/or the vertical interconnect structure 814. The second RD structure 896 may also, for example, provide connectivity for various signals between the functional dies 811 and 812 (eg, in addition to the connection provided by the connection die 816b, in addition to the connection provided by the RD structure 846a, etc.).

Although the example block 742 has been described as forming the second RD structure layer by layer, it should be noted that the second RD structure may be received in a pre-formed format and then attached (eg, welded, epoxy-glued, etc.) at the block 742 .

Typically, block 742 may include forming a second redistribution (RD) structure. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of making such carriers and/or signal redistribution structures or any particular features of such carriers and/or signal redistribution structures.

Example method 700 may include attaching (or coupling or mounting) a functional die to a second redistribution (RD) structure (e.g., as formed at block 742) at block 745. Block 745 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 745 may, for example, share any or all features with any die attach process discussed herein. Various example aspects of block 745 are presented in example 800G shown in FIG. 8G.

For example, the die interconnect structures (e.g., pads, bumps, etc.) of the first functional die 811a can be mechanically and electrically connected to corresponding conductors (e.g., pads, under bump metal, exposed traces, etc.) of the second RD structure 896. For example, the die interconnect structures of the first functional die 811a can be electrically connected to corresponding vertical interconnect structures 814 and/or electrically connected to corresponding connecting die interconnect structures 817 through conductors of the second RD structure 896. Similarly, the die interconnect structures (e.g., pads, bumps, etc.) of the second functional die 812a can be mechanically and electrically connected to corresponding conductors (e.g., pads, under bump metal, exposed traces, etc.) of the second RD structure 896. For example, the die interconnect structure of the second functional die 812 a may be electrically connected to the corresponding vertical interconnect structure 814 and/or electrically connected to the corresponding connecting die interconnect structure 817 through the conductor of the second RD structure 896 .

Such interconnect structures of functional dies can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In an example embodiment, the interconnect structures of functional dies 811a and 812a may include a solder cap (or other solder structure) that can be reflowed by mass reflow, thermal compression bonding (TCB), etc. Similarly, the pad or under-bump metal of the second RD structure 896 may have been formed with (for example, at block 742) a solder cap (or other solder structure) that can be reflowed by mass reflow, thermal compression bonding (TCB), etc. In another example embodiment, the connection can be performed by direct metal-to-metal (for example, copper-to-copper, etc.) bonding without solder and/or by utilizing one or more intermediate non-solder metal layers. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, filed on December 8, 2015, entitled “Transient Interface Gradient Bonding for Metal Bonds,” and U.S. Patent Application No. 14/989,455, filed on January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” each of which is hereby incorporated by reference in its entirety. The functional die interconnect structure may be attached to the second RD structure 896 using any of a variety of techniques (eg, mass reflow, thermal compression bonding (TCB), direct metal-to-metal metal bonding, conductive adhesives, etc.).

As shown in example embodiment 800G, the first connecting die interconnect structure 817 of the connecting die 816b is connected to the corresponding interconnect structure of the first functional die 811a through the second RD structure 896, and the second connecting die interconnect structure 817 of the connecting die 816b is connected to the corresponding interconnect structure of the second functional die 812a through the second RD structure 896. When connected, the connecting die 816b (e.g., combined with the second RD structure 896) provides electrical connection between the various die interconnect structures of the first functional die 811a and the second functional die 812a via the RD structure 298 of the connecting die 816b (e.g., as shown in example 200B-4 of FIG. 2B-1, etc.).

In the example 800G shown in FIG8F, the height of the vertical interconnect structure 814 can be, for example, equal to (or greater than) the combined height of the connecting die interconnect structure 217 and the supporting layer 290b of the connecting die 816b and the adhesive or other member used to attach the connecting die 816b to the RD structure 846a. Therefore, the second RD structure 896 can, for example, include a substantially planar lower surface, a substantially uniform thickness, and a substantially planar upper surface.

Typically, block 745 may include attaching (or coupling or mounting) a functional die to a second RD structure. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment or the features of any particular type of attachment structure.

Example method 700 may include bottom filling the functional die at block 750. Block 750 may include performing such bottom filling in any of a variety of ways, non-limiting examples of which are provided herein. Block 750 may, for example, share any or all features with any bottom filling discussed herein (e.g., with block 155 and/or block 175 of example method 100 of FIG. 1 , with block 355 and/or block 375 of example method 300 of FIG. 3 , with block 550 of example method 500 of FIG. 5 , etc.). Various example aspects of block 750 are presented in example 800H shown in FIG. 8H .

It should be noted that an underfill may be applied between the functional dies 811a and 812a and the second RD structure 896. In the context of utilizing a pre-applied underfill (PUF), such a PUF may be applied to the functional dies 811a and 812a, and/or to the second RD structure 896 and/or to top exposed conductors (e.g., pads, under bump metallization, exposed traces, etc.) of the second RD structure 896 prior to coupling the functional dies 811a and 812a.

After the attachment performed at block 745, block 750 may include forming an underfill (e.g., a capillary underfill, an injected underfill, etc.). As shown in example embodiment 800H of FIG. 8H, an underfill material 861 (e.g., any underfill material discussed herein, etc.) may fully or partially cover the bottom surfaces of the functional die 811a and 812a (e.g., in the orientation shown in FIG. 8H), and/or at least a portion (if not all) of the side surfaces of the functional die 811a and 812a. The underfill material 861 may also, for example, cover most (or all) of the top surface of the second RD structure 896. The bottom fill material 861 may also, for example, surround the corresponding interconnect structures (e.g., pads, bumps, etc.) of the functional dies 811a and 812a to which the corresponding interconnect structures (e.g., pads, lands, traces, under bump metallization, etc.) of the second RD structure 896 are attached. In an example embodiment in which the ends of the interconnect structures of the second RD structure 896 protrude from the top surface (e.g., the top dielectric layer surface) of the second RD structure 896, the bottom fill material 861 may also surround such protruding portions.

It should be noted that in various example implementations of the example method 700, the underfill performed at block 750 may be skipped. For example, underfilling the functional die may be performed at another block (e.g., at block 755, etc.). For another example, such underfill may be omitted entirely.

Typically, block 750 may include underfilling the functional die. Thus, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or the characteristics of any particular type of underfill material.

Example method 700 may include encapsulation at block 755. Block 755 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 755 may, for example, share any or all features with other encapsulation blocks (or steps) discussed herein (e.g., with block 735, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, with blocks 535 and 555 of example method 500 of FIG. 5, etc.).

Various example aspects of block 755 are presented in example 800I shown in Figure 8I. For example, encapsulation material 852' (and/or its formation) can share any or all features with encapsulation material 226' (and/or its formation) of Figure 2E, with encapsulation material 426 (and/or its formation) of Figure 4K, with encapsulation materials 651 and 652' (and/or its formation) of Figures 6D and 6H, with encapsulation material 851 of Figure 8E, etc.

The encapsulation material 852′ covers the top surface of the second RD structure 896, covers the side surfaces of the underfill 861, covers the top surface of the underfill 861 (e.g., between the dies 811 a and 812 a), covers at least some (if not all) of the side surfaces of the functional dies 811 a and 812 a, covers the top surfaces of the functional dies 811 a and 812 a, etc. In other examples, the encapsulation material 852′ can replace the underfill 861, thereby providing an underfill between the functional dies 811 a and/or 812 a and the second RD structure 896.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226' of FIG. 2E, etc.), encapsulation material 852' need not be initially formed to cover the top surfaces of functional die 811a and 812a. For example, block 755 may include forming encapsulation material 852' using film-assisted molding, sealing molding, etc.

In general, block 755 may include encapsulation. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of implementing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 700 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 760. Block 760 may include performing such grinding (or any thinning or planarizing process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 760 may, for example, share any or all features with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of example method 100 of FIG. 1 , with block 335 of example method 300 of FIG. 3 , with blocks 540 and 555 of example method 500 of FIG. 5 , with block 735, etc.).

Various example aspects of block 760 are presented in example 800J shown in Fig. 8J. Example ground (or thinned or planarized, etc.) encapsulation material 852 (and/or formation thereof) may share any or all features with encapsulation material 226 (and/or formation thereof) of Fig. 2F, with encapsulation material 426 (and/or formation thereof) of Fig. 4F, with encapsulation materials 651 and 652 (and/or formation thereof) of Figs. 6E and 6I, with encapsulation material 851, etc.

Block 760 may, for example, include grinding the encapsulation material 852 and/or the functional die 811a and 812a so that the top surface of the encapsulation material 852 is coplanar with the top surface of the functional die 811a and/or with the top surface of the functional die 812a.

Typically, block 760 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such grinding (or thinning or planarizing).

Example method 700 may include removing the carrier at block 765. Block 765 may include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 765 may share any or all features with any carrier removal process discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1 , with blocks 345 and/or 360 of example method 300 of FIG. 3 , with block 565 of example method 500 of FIG. 5 , etc.). Various example aspects of block 765 are shown in example 800K of FIG. 8K .

For example, example 800K of FIG. 8K shows the first carrier 821a removed (e.g., compared to example 800J of FIG. 8J ). Block 765 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, stripping, shearing, thermal release or laser release, etc.). For another example, if an adhesive layer was utilized during the formation of the RD structure 846a at block 720, for example, then block 765 may include removing the adhesive layer.

It should be noted that in various example embodiments, a second carrier (e.g., coupled to encapsulation material 852 and/or coupled to functional die 811a and 812a) may be utilized as shown and discussed herein with respect to example methods 100 and 300 of FIGS. 1 and 3. In other example embodiments, various tool structures may be utilized in place of a carrier.

Typically, block 765 may include removing the carrier. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of removing the carrier or the features of any particular type of carrier.

Example method 700 may include completing a signal redistribution (RD) structure at block 770 (e.g., if RD structure 846a is not fully formed at block 820). Block 770 may include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 770 may, for example, share any or all features with block 720 (e.g., with respect to RD structure formation aspects of block 720). Various aspects of block 770 are presented in example 800L shown in FIG. 8L.

As discussed herein, for example, with respect to block 720, the carrier may have been (but need not have been) received (or manufactured or prepared) with only a portion of the desired RD structure formed. In such an example scenario, block 770 may include completing the formation of the RD structure.

8L, block 770 may include forming a second portion 846b of the RD structure on a first portion 846a of the RD structure (e.g., the first portion 846a of the RD structure that has been received or manufactured or prepared at block 720). Block 770 may, for example, include forming the second portion 846b of the RD structure in the same manner as the first portion 846a of the RD structure was formed.

It should be noted that in various embodiments, the first portion 846a of the RD structure and the second portion 846b of the RD structure can be formed using different materials and/or different processes. For example, the first portion 846a of the RD structure can be formed using an inorganic dielectric layer, and the second portion 846b of the RD structure can be formed using an organic dielectric layer. For another example, the first portion 846a of the RD structure can be formed to have a finer spacing (or a finer trace, etc.), and the second portion 846b of the RD structure can be formed to have a coarser spacing (or a coarser trace, etc.). For another example, the first portion 846a of the RD structure can be formed using a back-end of line (BEOL) semiconductor wafer manufacturing (fab) process, and the second portion 846b of the RD structure can be formed using a post-fab electronic device packaging process. Additionally, the first portion 846a of the RD structure and the second portion 846b of the RD structure may be formed at different geographical locations.

Like the first portion 846a of the RD structure, the second portion 846b of the RD structure may have any number of dielectric layers and/or conductive layers.

As discussed herein, interconnect structures may be formed on RD structure 846b. In such example embodiments, block 765 may include forming an under bump metallization (UBM) on the exposed pads to enhance the formation (or attachment) of such interconnect structures.

Generally, block 770 may include completing a signal redistribution (RD) structure. Thus, the scope of the present disclosure should not be limited by the features of any particular manner of forming a signal redistribution structure or the features of any particular type of signal distribution structure.

Example method 700 may include forming an interconnect structure on the redistribution structure at block 775. Block 775 may include forming the interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 775 may share any or all features with any interconnect structure formation discussed herein.

Various example aspects of block 775 are presented in example 800M shown in FIG8M. Example interconnect structures 852 (e.g., package interconnect structures, etc.) may include features of any of a variety of interconnect structures. For example, package interconnect structures 852 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive posts, leads, etc.

Block 775 may include forming interconnect structures 852 in any of a variety of ways. For example, interconnect structures 852 may be adhered and/or printed on RD structures 846b (e.g., adhered and/or printed to their corresponding pads 851 and/or UBMs) and then reflowed. For another example, interconnect structures 852 (e.g., conductive balls, conductive bumps, pillars, leads, etc.) may be preformed prior to attachment and then attached to RD structures 846b (e.g., attached to their corresponding pads 851) such as by reflowing, electroplating, epoxy, wire bonding, etc.

It should be noted that, as described above, pad 851 of RD structure 846b may be formed by under bump metallization (UBM) or any metallization to assist in the formation (e.g., building, attaching, coupling, deposition, etc.) of interconnect structure 852. For example, such UBM formation may be performed at block 770 and/or block 775.

Typically, block 775 may include forming an interconnect structure on a redistribution structure. Therefore, the scope of the present disclosure should not be limited by the features of any particular manner of forming such an interconnect structure or any particular features of the interconnect structure.

The example method 700 may include a singulation cut at block 780. Block 780 may include performing such a singulation cut in any of a variety of ways, non-limiting examples of which are discussed herein. Block 780 may, for example, share any or all features with any singulation cut discussed herein (e.g., as discussed with respect to block 165 of the example method 100 of FIG. 1 , as discussed with respect to block 365 of the example method 300 of FIG. 3 , as discussed with respect to block 580 of the example method 500 of FIG. 5 , etc.).

Various example aspects of block 780 are presented in example 800N shown in Figure 8N. The singulated structure (e.g., corresponding to encapsulation material portion 852a) can, for example, share any or all features with the singulated structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b), with the singulated structure of Figure 4L (e.g., corresponding to two encapsulation material portions 426a and 426b), with the singulated structure 600M of Figure 6M, etc.

Generally, block 780 may include cutting. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of cutting.

The example method 700 may include performing a continuation process at block 790. Such continuation process may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 790 may share any or all features with block 190 of the example method 100 of FIG. 1 , with block 390 of the example method 300 of FIG. 3 , with block 590 of the example method 500 of FIG. 5 , and the like.

For example, block 790 may include returning the execution flow of the example method 700 to any of its blocks. For another example, block 790 may include directing the execution flow of the example method 700 to any other method block (or step) discussed herein (e.g., example method 100 of FIG. 1 , example method 300 of FIG. 3 , example method 500 of FIG. 5 , etc.).

As another example, as shown in example 200O of FIG. 2O , example 200P of FIG. 2P , and example 200Q of FIG. 2Q , block 790 may include forming an encapsulation material and/or an underfill (or skipping forming an encapsulation material and/or an underfill).

As discussed herein, the functional die and the connection die can be mounted to the substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in FIGS. 9 and 10 .

FIG. 9 shows a top view of an example electronic device 900 according to various aspects of the present disclosure. Example electronic device 900 may, for example, share any or all features with any or all electronic devices discussed herein. For example, functional die 911 and 912 may share any or all features with any or all functional die (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, etc.) discussed herein. For another example, connection die 916 may share any or all features with any or all connection die (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, etc.) discussed herein. Additionally, for example, substrate 930 may share any or all features with any or all of the substrates and/or RD structures (288, 488, 646, 846, 896, etc.) discussed herein.

FIG. 10 shows a top view of an example electronic device according to various aspects of the present disclosure. Example electronic device 1000 can, for example, share any or all features with any or all electronic devices discussed herein. For example, functional die (functional die 1 to functional die 10) can share any or all features with any or all functional die (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, 911, 912, etc.) discussed herein. For another example, the connecting die (connecting die 1 to connecting die 10) can share any or all features with any or all connecting dies (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, 916, etc.) discussed herein. In addition, for example, the substrate 1030 can share any or all features with any or all substrates and/or RD structures (288, 488, 646, 846, 896, 930, etc.) discussed herein.

Although the diagrams discussed herein generally include a connection die between two functional dies, the scope of the present disclosure is not limited thereto. For example, as shown in FIG. 10 , a connection die 9 is connected to three functional dies (e.g., functional die 2, functional die 9, and functional die 10), for example, electrically connecting each such functional die to each other. Thus, a single connection die can couple multiple functional dies (e.g., two functional dies, three functional dies, four functional dies, etc.).

Additionally, although the diagrams discussed herein generally include functional die connected to only one connection die, the scope of the present disclosure is not limited thereto. For example, a single functional die may be connected to two or more connection die. For example, as shown in FIG. 10 , functional die 1 is connected to many other functional die via many corresponding connection die.

The discussion herein contains many illustrative drawings that show various parts of semiconductor device components (or packages) and/or methods of making them. For clarity, these drawings do not show all aspects of each example component. Any example component presented herein may share any or all features with any or all other components presented herein.

In summary, various aspects of the present disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present disclosure provide various semiconductor package structures and methods for manufacturing the same, the semiconductor package structure including a connected die that sends electrical signals along a specific route between multiple other semiconductor die. Although the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the scope of the present disclosure. Therefore, it is intended that the disclosure not be limited to the particular instances disclosed, but that the disclosure will include all instances falling within the scope of the appended claims.

100: Example method/method 105: block 110: block 115: block 120: block 125: block 130: block 135: block 140: block 145: block 150: block 155: block 160: block 165: block 170: block 175: block 190: block 200A-1: example 200A-2: example 200A-3: example/example wafer 200A-4: example 200B-1: example/wafer 200B-2: example 200B-3: Example 200B-4: Example 200B-5: Example 200B-6: Example 200B-7: Example 200C: Example 200D: Example 200E: Example 200F: Example 200G: Example 200H: Example 200I: Example 200J: Example 200K: Example 200L: Example 200M: Example 200N: Example 200O: Example/Example Implementation Scheme 200P: Example/Example Implementation Scheme 200Q: Example/Example Implementation Scheme 201: Functional grain 202: Functional grain 203: Functional grain 204: Functional grain 211: Example die/functional die/first functional die/first die 212: Example die/functional die/second functional die/second die 213: Die interconnect structure/first die interconnect structure 214: Die interconnect structure/second die interconnect structure 216a: Example connection die/connection die 216b: Thin connection die/connection die 216c: Connection die 217: Connection die interconnect structure 217b: Connection die interconnect structure 221: Carrier 223: Adhesive material/adhesive layer/bottom filler 224: Bottom filler 225: Encapsulation material 226: Encapsulation material 226': Encapsulation material 226a: Encapsulation material portion 226b: encapsulation material portion 231: second carrier 288: substrate 290: support layer 290a: support layer 290b: support layer 291: base dielectric layer 291b: base dielectric layer 292: first conductive trace 292b: first conductive trace 293: first dielectric layer 293b: first dielectric layer 294: conductive via 294b: conductive via 295: second conductive trace 295b: second conductive trace 296: second dielectric layer 296b: second dielectric layer 298: redistribution (RD) structure 298b: redistribution (RD) structure 299: second set of connecting die interconnect structure/second connecting die interconnect structure 300: example method/method 305: block 310: block 315: block 320: block 325: block 330: block 335: block 340: block 345: block 347: block 350: block 355: block 360: block 365: block 370: block 375: block 390: block 400A-1: example 400A-2: example 400A-3: Example 400A-4: Example 400B-1: Example 400B-2: Example 400C: Example 400D: Example 400E: Example 400F: Example 400G: Example 400H: Example 400H-2: Example/Example Implementation Scheme 400I: Example 400J: Example 400K: Example 400L: Example 400M: Example 400N: Example 401: Functional die 402: Functional die 403: Functional die 404: Functional die 411: Functional die 412: Functional die 413: First die interconnect structure 414: second die interconnect structure 416a: connecting die 416b: connecting die 417: connecting die interconnect structure/passivation layer 421: carrier 423: adhesive/bottom filler 424: bottom filler 426: encapsulation material 426': encapsulation material 426a: encapsulation material portion 426b: encapsulation material portion 431: second carrier 488: substrate 500: example method/method 505: block 510: block 515: block 520: block 525: block 530: block 535: block 540: block 545: Block 550: Block 555: Block 560: Block 565: Block 570: Block 575: Block 580: Block 590: Block 600A: Example 600B: Example 600C: Example 600D: Example 600E: Example 600F: Example 600G: Example 600H: Example 600I: Example 600J: Example 600K: Example 600L: Example 600M: Example 611a: First functional die 612a: Second functional die 614: Pillar/interconnect structure 616b: Connecting die 617: Connecting die interconnect structure/interconnect structure 621a: Block carrier 646a: Redistribution (RD) structure 646b: RD structure 647: Dielectric layer 648: Conductive layer 651: Encapsulation material 651': Encapsulation material 652: Auxiliary interconnect structure 652': Encapsulation material 652a: Encapsulation material portion 661: Bottom fill material 700: Example method/method 705: Block 710: Block 715: Block 720: Block 725: Block 730: Block 735: Block 740: Block 742: Block 745: Block 750: Block 755: Block 760: Block 765: Block 770: Block 775: Block 780: Block 790: Block 800A: Example 800B: Example 800C: Example 800D: Example 800E: Example 800F: Example 800G: Example 800H: Example 800I: Example 800J: Example 800K: Example 800L: Example 800M: Example 800N: Example 811a: Functional die 812a: functional die 814: vertical interconnect structure 816b: connecting die 817: connecting die interconnect structure 821a: block carrier 846a: redistribution (RD) structure/first part 846b: redistribution (RD) structure/second part 847: dielectric layer 848: conductive layer 851: encapsulation material 851': encapsulation material 852: encapsulation material 852': encapsulation material 852a: encapsulation material part 861: bottom filling material 896: second redistribution (RD) structure 897: dielectric layer 898: conductive layer 900: example electronic device 911: functional die 912: Functional die 916: Connection die 930: RD structure 1000: Example electronic device 1030: Substrate

[FIG. 1] is a flow chart showing an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIG. 2A] to [FIG. 2Q] show cross-sectional views illustrating various aspects of example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[FIG. 3] is a flow chart showing an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIG. 4A] to [FIG. 4N] show cross-sectional views illustrating various aspects of example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 5] shows a flow chart of an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIGS. 6A] to [FIGS. 6M] show cross-sectional views illustrating various aspects of example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 7] shows a flow chart of an example method for manufacturing an electronic device according to various aspects of the present disclosure.

[FIGS. 8A] to [FIGS. 8N] show cross-sectional views illustrating various aspects of example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 9] shows a top view of an example electronic device in various aspects according to the present disclosure.

[Figure 10] shows a top view of an example electronic device according to various aspects of the present disclosure.

200Q: Examples/Example Implementation Plan

201: Functional grains

202: Functional grains

213: Die interconnect structure/first die interconnect structure

214: Die interconnect structure/second die interconnect structure

216b: Thin connection die/connection die

225: Encapsulation material

288: Substrate

299: Second set of connecting die interconnection structure/second connecting die interconnection structure

Claims (20)

An electronic device, comprising: a first signal redistribution structure; a vertical interconnect structure on a first side of the first signal redistribution structure; a connecting die including a back side and a front side, wherein the back side faces and is coupled to the first side of the first signal redistribution structure; a die attach material on the back side of the connecting die and the first side of the first signal redistribution structure; a connecting die interconnect structure coupled to the front side of the connecting die; and a second signal redistribution structure including a first side and a second side opposite the first side, wherein the second side of the second signal redistribution structure is on the vertical interconnect structure and on the connecting die interconnect structure. An electronic device as described in claim 1, comprising a first encapsulation material, wherein the first encapsulation material covers the first surface of the first signal redistribution structure and laterally surrounds the vertical interconnect structure and the connecting die interconnect structure. An electronic device as described in claim 2, wherein the first encapsulation material laterally surrounds the connecting die. An electronic device as described in claim 2, wherein the first surface of the first encapsulation material is coplanar with the first end surface of the vertical interconnect structure and the first end surface of the connecting die interconnect structure, and the first surface of the first encapsulation material is positioned toward the second signal redistribution structure. An electronic device as described in claim 4, wherein the first side of the first signal redistribution structure, the first side of the second signal redistribution structure and the first side of the encapsulation material are coplanar. An electronic device as described in claim 4, wherein the second surface of the encapsulation material is coplanar with the bottom surface of the die attach material, and wherein the second surface of the encapsulation material is opposite to the first surface of the encapsulation material. An electronic device as described in claim 2, wherein the encapsulation material contacts the die attach material. The electronic device as described in claim 1 comprises: a first electronic component coupled to the first surface of the second signal redistribution structure; and a second electronic component coupled to the first surface of the second signal redistribution structure. An electronic device as described in claim 8, wherein the connecting die includes no active electronic components. A method for manufacturing an electronic device, comprising: providing a first signal redistribution structure; providing a vertical interconnect structure on a first side of the first signal redistribution structure; coupling a connection die to the first side of the first signal redistribution structure; providing a first encapsulation material above the first side of the first signal redistribution structure and surrounding the vertical interconnect structure and the connection die; and providing a second signal redistribution structure on the vertical interconnect structure and on the first encapsulation material. The method as described in claim 10, comprising coupling the second signal redistribution structure to a connecting die interconnect structure, wherein the connecting die interconnect structure is disposed above the front side of the connecting die. The method as described in claim 11, wherein the first encapsulation material contacts the connecting die interconnect structure. The method as described in claim 10, comprising: disposing a first electronic component above a first surface of the second signal redistribution structure, wherein the first surface of the second signal redistribution structure is oriented away from the connection grain; and disposing a second electronic component above the first surface of the second signal redistribution structure. The method of claim 10, wherein coupling the connection die to the first side of the first signal redistribution structure comprises connecting a backside interconnect structure of the connection die to an interconnect structure of the first signal redistribution structure. The method of claim 10, wherein coupling the connection die to the first side of the first signal redistribution structure comprises coupling the die attach material to the back side of the connection die and the first side of the first signal redistribution structure. A method for manufacturing an electronic device, comprising: providing a first signal redistribution structure; providing a vertical interconnect structure on a first surface of the first signal redistribution structure; coupling a connecting die to the first surface of the first signal redistribution structure; coupling a second signal redistribution structure to the vertical interconnect structure and the connecting die; disposing a first electronic component above the first surface of the second signal redistribution structure, the first surface of the second signal redistribution structure being oriented away from the connecting die; and disposing a second electronic component above the first surface of the second signal redistribution structure. The method as claimed in claim 16, comprising: providing a first encapsulation material above the first surface of the first signal redistribution structure and surrounding the connecting die and the vertical interconnect structure; and providing a second encapsulation material above the first surface of the second signal redistribution structure and surrounding the first electronic component and the second component. The method of claim 17, comprising coupling the second signal redistribution structure to a connecting die interconnect structure over the front side of the connecting die, wherein the first encapsulation material contacts the connecting die interconnect structure. The method of claim 16, wherein coupling the connection die to the first side of the first signal redistribution structure comprises connecting a backside interconnect structure of the connection die to an interconnect structure of the first signal redistribution structure. The method of claim 16, wherein coupling the connection die to the first side of the first signal redistribution structure comprises connecting the die attach material to the back side of the connection die and the first side of the first signal redistribution structure.