TWI901721B - Semiconductor package and fabricating method thereof - Google Patents

Abstract

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Description

Semiconductor packaging and its manufacturing method

This invention relates to semiconductor packaging and methods for manufacturing semiconductor packaging. Cross-reference to / incorporation of related applications by reference.

This application is a partial continuation of U.S. Patent Application No. 16/700,592, filed December 2, 2019, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”, which is a continuation of U.S. Patent Application No. 16/213,769, filed December 7, 2018, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF” (now U.S. Patent No. 10,497,674), each of which is hereby incorporated herein by reference in its entirety.

This application relates to the following applications: U.S. Patent Application No. 14/686,725, filed April 14, 2015, entitled "Semiconductor Package with High Routing Density Patch"; U.S. Patent Application No. 14/823,689, filed August 11, 2015, entitled "Semiconductor Package and Fabricating Method Thereof" (now U.S. Patent No. 9,543,242); and U.S. Patent Application No. 6, January 2017, entitled "Semiconductor Package and Fabricating Method Thereof". U.S. Patent Application No. 15/400,041 entitled “Semiconductor Package and Method of Manufacturing Thereof”, filed on March 10, 2016, and U.S. Patent Application No. 15/066,724 entitled “Semiconductor Package and Method of Manufacturing Thereof”, are hereby incorporated herein by reference in their entirety.

Current semiconductor packaging and the methods used to form semiconductor packages are unsuitable, for example, leading to excessive costs, reduced reliability, or excessively large package sizes. Further limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing conventional and traditional methods with the disclosure herein, as illustrated in the remainder of this application with reference to the figures.

Various embodiments of this disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As a non-limiting example, various embodiments of this disclosure provide various semiconductor package structures and methods for manufacturing them, said semiconductor package structures including interconnecting dies that route electrical signals between a plurality of other semiconductor dies.

The following statements illustrate various aspects of this disclosure by providing examples. These examples are non-limiting, and therefore the scope of the various aspects of this disclosure should not be limited by any particular characteristic of the examples provided. In the following statements, the phrases “by way of example,” “for example,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limiting,” “by way of example and not limiting,” etc.

As used herein, “and/or” means any one or more items in a list linked by “and/or”. As an example, “x and/or y” means any element in the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y”. As another example, “x, y and/or z” means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z”. Similarly, as used herein, “and/or” means any one or more items in a list linked by “or”.

The terms used herein are for the purpose of describing specific examples only and are not intended to limit the scope of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “including,” “having,” and similar terms, when used in this specification, designate the presence of the stated features, integrals, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and/or groups thereof.

It should be understood that while terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first segment discussed below may be referred to as the second element, second component, or second segment. Similarly, various spatial terms, such as “upper,” “lower,” “side,” and the like, may be used to distinguish one element from another in a relative manner. However, it should be understood that components may be oriented in different ways; for example, without departing from the teachings of this disclosure, a semiconductor device or package may be rotated laterally such that its “top” surface faces horizontally and its “side” surface faces vertically.

This disclosure provides various embodiments of a semiconductor device or package and a method of manufacturing the same, which can reduce costs, increase reliability and/or improve the manufacturability of the semiconductor device or package.

The above and other variations of this disclosure will be described in and will become apparent from the following description of various embodiments. Various variations of this disclosure will now be presented with reference to the accompanying drawings, so that those skilled in the art can readily implement the various variations.

Figure 1 shows a flowchart of an example method 100 for manufacturing an electronic device (e.g., a semiconductor package, etc.). Example method 100 may, for example, share any or all of the characteristics with any other example methods discussed herein (e.g., example method 300 of Figure 3, example method 500 of Figure 5, example method 700 of Figure 7, etc.). Figures 2A to 2Q show cross-sectional views of various illustrative example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to this disclosure. Figures 2A to 2Q may illustrate example electronic devices, for example, with the various blocks (or steps) of method 100 of Figure 1. Figures 1 and 2A to 2Q will now be discussed together. It should be noted that the order of the instance blocks in method 100 may be changed without departing from the scope of this disclosure.

Example method 100 may begin execution at block 105. Method 100 may begin execution in response to any of a variety of causes or conditions, and non-limiting examples are provided herein. For example, method 100 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, upon the arrival of components and/or manufacturing materials used during the execution of method 100, etc. As another example, method 100 may begin execution in response to an operator command to begin. Additionally, for example, method 100 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 100 may include receiving, manufacturing, and/or preparing multiple functional dies at block 110. Block 110 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 110 may share any or all of the characteristics with any of the functional die receiving, manufacturing, and/or preparing operations discussed herein. Various example forms of block 110 are illustrated in Figure 2A.

Block 110 may include, for example, receiving multiple functional dies (or any portion thereof) from an upstream manufacturing process in the same facility or geographical location. Block 110 may also include, for example, receiving functional dies (or any portion thereof) from a supplier (e.g., from a foundry, etc.).

The received, manufactured, and/or prepared functional dies can include any of a variety of characteristics. For example, although not shown, the received dies can include multiple different dies on the same wafer (e.g., a multi-project wafer (MPW)). An example of this configuration is shown in Example 210A of Figure 2A of U.S. Patent Application No. 15/594,313, which is hereby incorporated herein by reference in its entirety for all purposes. In this type of MPW configuration, the wafer can contain multiple functional dies of different types. For example, the first die can include a processor, and the second die can include a memory chip. As another example, the first die can include a processor, and the second die can include a co-processor. Alternatively, for example, both the first and second dies can include memory chips. Typically, the die can include an active semiconductor circuit system. Although the various examples presented herein typically involve placing or attaching functional dies that have been individually cut, such dies may also be interconnected before placement (e.g., as part of the same half-conductor wafer, as part of a reconstructed wafer, etc.).

Block 110 may, for example, include receiving functional dies in one or more corresponding wafers dedicated to a single type of die. For example, as shown in FIG2A, Example 200A-1 shows a wafer dedicated to an entire wafer of die 1, an example die of which is shown at label 211, and Example wafer 200A-3 shows a wafer dedicated to an entire wafer of die 2, an example die of which is shown at label 212. It should be understood that although the various examples shown herein generally involve first and second functional dies (e.g., die 1 and die 2), the scope of this disclosure extends to any number of functional dies of the same or different types (e.g., three dies, four dies, etc.). For example, in addition to or replacing functional semiconductor chips, the scope of this disclosure extends to passive electronic components (e.g., resistors, capacitors, inductors, etc.).

Functional grains 211 and 212 may include grain interconnect structures. For example, as shown in FIG2A, the first functional grain 211 includes a first set of one or more grain interconnect structures 213 and a second set of one or more grain interconnect structures 214. Similarly, the second functional grain 212 may include such structures. Grain interconnect structures 213 and 214 may include any of a variety of grain interconnect structure characteristics, and non-limiting examples thereof are provided herein.

The first grain interconnect structure 213 may include, for example, metal pillars (e.g., copper, aluminum, etc.) or pads. The first grain interconnect structure 213 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, pillars, etc.

The first grain interconnect structure 213 can be formed in any of a variety of ways. For example, the first grain interconnect structure 213 can be electroplated onto the grain pad of the functional grain 211. Furthermore, for example, the first grain interconnect structure 213 can be printed and reflowed, wire-bonded, etc. It should be noted that in some embodiments, the first grain interconnect structure 213 can be the grain pad of the first functional grain 211.

The first grain interconnect structure 213 can be capped, for example. For example, the first grain interconnect structure 213 can be capped with solder. Or, for example, the first grain interconnect structure 213 can be capped with a metal layer (e.g., a metal layer other than solder, forming a substituted solid solution or an intermetallic compound having copper). For example, the first grain interconnect structure 213 can be formed and/or connected as described in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," the entire contents of which are hereby incorporated herein by reference. Additionally, for example, the first grain interconnect structure 213 may be formed and/or connected as illustrated in U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” the entire contents of which are hereby incorporated herein by reference.

The first grain interconnect structure 213 may include any of a variety of dimensional characteristics. For example, in an exemplary embodiment, the first grain interconnect structure 213 may include a spacing of 30 micrometers (e.g., center-to-center spacing) and a diameter (or width, minor axis or major axis width, etc.) of 17.5 micrometers. As another example, in an exemplary embodiment, the first grain interconnect structure 213 may include a spacing in the range of 20 to 40 (or 30 to 40) micrometers and a diameter (or width, minor axis or major axis width, etc.) in the range of 10 to 25 micrometers. The first grain interconnect structure 213 may, for example, be 15 to 20 micrometers high.

The second grain interconnect structure 214 may, for example, share any or all of the properties with the first grain interconnect structure 213. Some or all of the second grain interconnect structure 214 may, for example, be substantially different from the first grain interconnect structure 213.

The second grain interconnect 214 may include, for example, metal pillars (e.g., copper, aluminum, etc.) or pads. The second grain interconnect 214 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, etc. The second grain interconnect 214 may be, for example, a general type of interconnect structure similar to the first grain interconnect 213, but is not required to be. For example, both the first grain interconnect 213 and the second grain interconnect 214 may include copper pillars. As another example, the first grain interconnect 213 may include metal pads, and the second grain interconnect 214 may include copper pillars.

The second grain interconnect structure 214 can be formed in any of a variety of ways. For example, the second grain interconnect structure 214 can be electroplated onto the grain pad of the functional grain 211. Furthermore, for example, the second grain interconnect structure 214 can be printed and reflowed, wire-bonded, etc. The second grain interconnect structure 214 can be formed with the first grain interconnect structure 213 using the same process steps, but such grain interconnect structures 213 and 214 can also be formed separately in corresponding steps and/or in overlapping steps.

For example, in a first embodiment, a first portion (e.g., a first half, a first third, etc.) of each of the second grain interconnect structures 214 can be formed in the same first electroplating operation as the first grain interconnect structure 213. Continuing with the first embodiment, a second portion (e.g., a second half, the remaining two-thirds, etc.) of each of the second grain interconnect structures 214 can then be formed in a second electroplating operation. For example, during the second electroplating operation, additional electroplating of the first grain interconnect structure 213 can be suppressed (e.g., by using a dielectric or protective masking layer formed thereon, by removing electroplating signals, etc.). In another example scenario, the second grain interconnect structure 214 can be formed in a second electroplating process that is completely independent of the first electroplating process used to form the first grain interconnect structure 213, during which the first grain interconnect structure can be covered, for example, by a protective masking layer.

The second grain interconnect structure 214 may, for example, be uncapped. For instance, the second grain interconnect structure 214 may not be capped by solder. In an example scenario, the first grain interconnect structure 213 may be capped (e.g., capped by solder, capped by a metal layer, etc.), while the second grain interconnect structure 214 is uncapped. In another example scenario, both the first grain interconnect structure 213 and the second grain interconnect structure 214 are uncapped.

The second grain interconnect structure 214 may include any of a variety of dimensional characteristics. For example, in an exemplary embodiment, the second grain interconnect structure 214 may include a spacing of 80 micrometers (e.g., center-to-center spacing) and a diameter (or width) of 25 micrometers or greater. As another example, in an exemplary embodiment, the second grain interconnect structure 214 may include a spacing in the range of 50 to 80 micrometers and a diameter (or width, minor axis or major axis width, etc.) in the range of 20 to 30 micrometers. Additionally, for example, in an exemplary embodiment, the second grain interconnect structure 214 may include a spacing in the range of 80 to 150 (or 100 to 150) micrometers and a diameter (or width, minor axis or major axis width, etc.) in the range of 25 to 40 micrometers. The second grain interconnect structure 214 can be, for example, 40 to 80 micrometers high.

It should be noted that functional grains (e.g., in wafer form, etc.) that already have one or more grain interconnection structures 213/214 (or any part thereof) formed thereon can be received.

It should also be noted that the functional grains (e.g., in wafer form) can be thinned from their original grain thickness (e.g., by grinding, mechanical and/or chemical thinning, etc.), but this is not necessary. For example, the functional grain wafers (e.g., the wafers shown in Examples 200A-1, 200A-2, 200A-3 and/or 200A-4) can be full-thickness wafers. As another example, the functional grain wafers (e.g., the wafers shown in Examples 200A-1, 200A-2, 200A-3, 200A-4, etc.) can be at least partially thinned to reduce the thickness of the resulting package while still enabling safe wafer handling.

Typically, block 110 may include receiving, manufacturing, and/or preparing multiple functional chips. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of receiving and/or manufacturing, nor by any particular characteristic of such functional chips.

Example method 100 may include receiving, manufacturing, and/or preparing interconnect dies at block 115. Block 115 may include receiving and/or manufacturing multiple interconnect dies in any of various ways, and non-limiting examples thereof are provided herein. Various example states of block 115 are presented in examples 200B-1 to 200B-7 shown in Figures 2B-1 and 2B-2.

Block 115 may include, for example, receiving multiple interconnecting dies from an upstream manufacturing process in the same facility or geographical location. Block 115 may also include, for example, receiving interconnecting dies from a supplier (e.g., from a foundry, etc.).

The received, manufactured, and/or prepared interconnect dies can include any of a variety of characteristics. For example, the received, manufactured, and/or prepared dies can include multiple interconnect dies on a wafer (e.g., silicon or other semiconductor wafers, glass wafers or panels, metal wafers or panels, etc.). For example, as shown in Figure 2B-1, Example 200B-1 includes an entire wafer of interconnect dies, and example interconnect dies are indicated by component symbol 216a. It should be understood that although the various examples shown herein generally relate to the use of a single interconnect die in a package, multiple interconnect dies (e.g., multiple interconnect dies having the same or different designs) can be used in a single electronic device package. Non-limiting examples of such configurations are provided herein.

In the examples shown herein (e.g., 200B-1 to 200B-4), the interconnect die may, for example, contain only an electrical routing circuit system (e.g., without active semiconductor components and/or passive components). However, it should be noted that the scope of this disclosure is not limited thereto. For example, the interconnect die shown herein may include passive electronic components (e.g., resistors, capacitors, inductors, integrated passive devices (IPDs), etc.) and/or active electronic components (e.g., transistors, logic circuits, semiconductor processing components, semiconductor memory components, etc.) and/or optical components, etc.

Interconnect dies may include interconnect dies interconnect structures. For example, the example interconnect die 216a shown in FIG200B-1 includes interconnect dies interconnect structure 217. Interconnect dies interconnect structure 217 may include any of a variety of interconnect structure characteristics, and non-limiting examples thereof are provided herein. Although this description generally presents all interconnect dies interconnect structures 217 as identical to each other, they may also differ from each other. For example, referring to FIG2B-1, the left portion of interconnect dies interconnect structure 217 may be the same as or different from the right portion of interconnect dies interconnect structure 217.

The interconnecting grain interconnect structure 217 and/or its formation may share any or all characteristics with the first grain interconnect structure 213 and/or the second grain interconnect structure 214 and/or its formation discussed herein. In an exemplary embodiment, a first portion of the interconnecting grain interconnect structure 217 may include the spacing, layout, shape, size, and/or material properties of a corresponding first grain interconnect structure 213 that fits such a first portion to a first functional grain 211, and a second portion of the interconnecting grain interconnect structure 217 may include the spacing, layout, shape, size, and/or material properties of a corresponding first grain interconnect structure 213 that fits such a second portion to a second functional grain 212.

The interconnecting die interconnect structure 217 may include, for example, metal pillars (e.g., copper, aluminum, etc.) or pads. The interconnecting die interconnect structure 217 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, pillars, etc.

The interconnecting die structure 217 can be formed in any of a variety of ways. For example, the interconnecting die structure 217 can be electroplated onto the die pad of the interconnecting die 216a. Furthermore, for example, the interconnecting die structure 217 can be printed and reflowed, wire-bonded, etc. It should be noted that in some embodiment, the interconnecting die structure 217 can be the die pad of the interconnecting die 216a.

The interconnecting grain structure 217 can be, for example, capped. For instance, the interconnecting grain structure 217 can be covered with solder. Or, for instance, the interconnecting grain structure 217 can be covered with a metal layer (e.g., a metal layer forming a substituted solid solution or an intermetallic compound containing copper). For example, the interconnecting grain structure 217 can be formed and/or connected as described in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," the entire contents of which are hereby incorporated herein by reference. Additionally, for example, the interconnecting grain structure 217 may be formed and/or connected as explained in U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” the entire contents of which are hereby incorporated herein by reference.

The interconnecting die structure 217 can include any of a variety of dimensional characteristics. For example, in an embodiment, the interconnecting die structure 217 may include a spacing of 30 micrometers (e.g., center-to-center spacing) and a diameter (or width, minor axis or major axis width, etc.) of 17.5 micrometers. As another example, in an embodiment, the interconnecting die structure 217 may include a spacing in the range of 20 to 40 (or 30 to 40) micrometers and a diameter (or width, minor axis or major axis width, etc.) in the range of 10 to 25 micrometers. The interconnecting die structure 217 may be, for example, 15 to 20 micrometers high.

In an example scenario, the interconnecting die interconnect structure 217 may include a copper pillar that mates with the corresponding first die interconnect structure 213 (e.g., metal pad, conductive bump, copper pillar, etc.) of the first functional die 211 and the second functional die 212.

The interconnect die 216a (or its wafer 200B-1) can be formed in any of a variety of ways, and non-limiting examples are discussed herein. For example, referring to FIG. 2B-1, the interconnect die 216a (e.g., shown in example 200B-3) or its wafer (e.g., shown in example 200B-1) may include, for example, a support layer 290a (e.g., a silicon or other semiconductor layer, a glass layer, a metal layer, a plastic layer, etc.). A redistribution (RD) structure 298 may be formed on the support layer 290. The RD structure 298 may include, for example, a substrate dielectric layer 291, a first dielectric layer 293, a first conduction trace 292, a second dielectric layer 296, a second conduction trace 295, and an interconnect die interconnect structure 217.

The substrate dielectric layer 291 may, for example, be on the support layer 290. The substrate dielectric layer 291 may, for example, comprise an oxide layer, a nitride layer, any of a variety of inorganic dielectric materials, etc. The substrate dielectric layer 291 may, for example, be formed according to specifications and/or may be native. The substrate dielectric layer 291 may be referred to as a passivation layer. The substrate dielectric layer 291 may be or comprise, for example, a silicon dioxide layer formed using a low-pressure chemical vapor deposition (LPCVD) process. In other exemplary embodiments, the substrate dielectric layer 291 may be formed from any of a variety of organic dielectric materials, many of which are provided herein.

The connecting die 216a (e.g., shown in Example 200B-3) or its wafer (e.g., shown in Example 200B-1) may also include, for example, a first conductive trace 292 and a first dielectric layer 293. The first conductive trace 292 may, for example, comprise a deposited conductive metal (e.g., copper, aluminum, tungsten, etc.). The first conductive trace 292 may be formed, for example, by sputtering, electroplating, electroless plating, etc. The first conductive trace 292 may be formed, for example, with a submicron or sub-two-micron spacing (or a center-to-center spacing). The first dielectric layer 293 may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It should be noted that in various embodiments, the first dielectric layer 293 may be formed before the first conductive trace 292, for example, by forming an aperture that is then filled with the first conductive trace 292 or a portion thereof. In example embodiments that include copper conductive traces, a double-pile process may be used to deposit the traces.

In alternative assemblies, the first dielectric layer 293 may comprise an organic dielectric material. For example, the first dielectric layer 293 may comprise bismaleimide triazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, and equivalents and compounds thereof, but the scope of this disclosure is not limited thereto. Organic dielectric materials may be formed in any of various ways, such as chemical vapor deposition (CVD). In such alternative assemblies, the first conductive traces 292 may, for example, have a spacing (or center-to-center spacing) of 2 to 5 micrometers.

The connecting die 216a (e.g., shown in Example 200B-3) or its wafer 200B-1 (e.g., shown in Example 200B-1) may also include, for example, a second conducting trace 295 and a second dielectric layer 296. The second conducting trace 295 may include, for example, a deposited conductive metal (e.g., copper, etc.). The second conducting trace 295 may be connected to a corresponding first conducting trace 292, for example, through a corresponding conductive via 294 or a hole (e.g., in the first dielectric layer 293). The second dielectric layer 296 may include, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In alternative assemblies, the second dielectric layer 296 may include an organic dielectric material. For example, the second dielectric layer 296 may include bismaleimide triazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin and its equivalents and compounds, but the scope of this disclosure is not limited thereto. The second dielectric layer 296 may be formed, for example, using a CVD process, but the scope of this disclosure is not limited thereto. It should be noted that various dielectric layers (e.g., the first dielectric layer 293, the second dielectric layer 296, etc.) may be formed from the same dielectric material and/or using the same process, but this is not required. For example, the first dielectric layer 293 may be formed from any inorganic dielectric material discussed herein, and the second dielectric layer 296 may be formed from any organic dielectric material discussed herein, and vice versa.

Although two sets of dielectric layers and conduction traces are illustrated in Figure 2B-1, it should be understood that the RD structure 298 connecting die 216a (e.g., shown in Example 200B-3) or its wafer (e.g., shown in Example 200B-1) can include any number of such layers and traces. For example, the RD structure 298 may include only one dielectric layer and/or one set of conduction traces, three sets of dielectric layers and/or conduction traces, etc.

Interconnecting die interconnects 217 (e.g., conductive bumps, conductive balls, conductive pillars or rods, conductive pads or pads, etc.) can be formed on the surface of the RD structure 298. Examples of such interconnecting die interconnects 217 are shown in Figures 2B-1 and 2B-2, where the interconnecting die interconnects 217 are shown as being formed on the front (or top) side of the RD structure 298 and electrically connected to corresponding second conductive traces 295 via conductive vias in the second dielectric layer 296. Such interconnecting die interconnects 217 can be used, for example, to couple the RD structure 298 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.), including, for example, the first functional die 211 and the second functional die 212 discussed herein.

The interconnecting die structure 217 may include, for example, any of a variety of conductive materials (e.g., any or a combination of copper, nickel, gold, etc.). The interconnecting die structure 217 may also include, for example, solder. As another example, the interconnecting die structure 217 may include solder balls or bumps, multi-ball solder pillars, elongated solder balls, metal (e.g., copper) core balls having a solder layer on a metal core, electroplated pillar structures (e.g., copper pillars, etc.), lead structures (e.g., lead-bonded leads), etc.

Referring to Figure 2B-1, Example 200B-1, showing a wafer with interconnect die 216a, can be thinned, for example, to produce a thin interconnect die wafer as shown in Example 200B-2, with thin interconnect die 216b. For example, the thin interconnect die wafer (e.g., as shown in Example 200B-2) can be thinned to the extent that it still allows for safe disposal of the thin interconnect die wafer and/or its individual thin interconnect dies 216b, but provides a low profile (e.g., by grinding, chemical and/or mechanical thinning, etc.). For example, referring to Figure 2B-1, in an example embodiment where the support layer 290 includes silicon, the thin interconnect die 216b can still include at least a portion of the silicon support layer 290. For example, the bottom (or back) side of the thin interconnect die 216b may include sufficient non-conductive support layer 290, substrate dielectric layer 291, etc., to prevent conductive access from the bottom side of the remaining support layer 290 to the conductive layer on the top side. In other embodiments, the thin interconnect die 216b may be thinned to substantially or completely remove the support layer 290. In such embodiments, conductive access at the bottom side of the interconnect die 216b can still be blocked by the substrate dielectric 291.

For example, in one embodiment, the thin interconnect die wafer (e.g., as shown in Example 200B-2) or its thin interconnect die 216b may have a thickness of 50 micrometers or less. In another embodiment, the thin interconnect die wafer (or its thin interconnect die 216b) may have a thickness in the range of 20 to 40 micrometers. As will be discussed herein, the thickness of the thin interconnect die 216b may be less than the length of the second die interconnect structure 214 of the first die 211 and the second die 212, for example, such that the thin interconnect die 216b can be mounted between the carrier and the functional dies 211 and 212.

Figure 2B-2, at 200B-5, illustrates two example interconnect die implementations labeled "Interconnect Die Example 1" and "Interconnect Die Example 2". Interconnect Die Example 1 may utilize an inorganic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and semiconductor support layer 290, for example. Interconnect Die Example 1 may be generated, for example, using Amkor Technology's Silicon-Free Integrated Module (SLIM™) technology. The semiconductor support layer may be, for example, 30 to 100 μm (e.g., 70 μm) thick, and each layer (or sublayer or layer) of the RD structure (e.g., containing at least a dielectric layer and a conductive layer) may be, for example, 1 to 3 μm (e.g., 3 μm, 5 μm, etc.) thick. The total thickness of the resulting structure can be, for example, in the range of 33 to 109 μm (e.g., <80 μm, etc.). It should be noted that the scope of this disclosure is not limited to any particular size.

Interconnect die example 2 may utilize an organic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and semiconductor support layer 290, for example. Interconnect die example 2 may be generated, for example, using Amkor's silicon wafer integrated fan-out (SWIFT ^™ ) technology. The semiconductor support layer may be, for example, 30 to 100 μm (e.g., 70 μm) thick, and each layer (or sublayer or layer) of the RD structure (e.g., containing at least a dielectric layer and a conductive layer) may be, for example, 4 to 7 μm thick, 10 μm thick, etc. The total thickness of the resulting structure may be, for example, in the range of 41 to 121 μm (e.g., <80 μm, 100 μm, 110 μm, etc.). It should be noted that the scope of this disclosure is not limited to any particular size. It should also be noted that in various embodiment schemes, the support layer 290 of interconnecting die example 2 can be thinned (e.g., relative to interconnecting die example 1) to obtain the same or similar total thickness.

The exemplary embodiments presented herein typically involve single-sided interconnect dies, which may, for example, have interconnect structures on only one side. However, it should be noted that the scope of this disclosure is not limited to such single-sided structures. For example, as shown in Examples 200B-6 and 200B-7, interconnect die 216c may include interconnect structures on both sides. An exemplary embodiment of this interconnect die 216c (e.g., as shown in Example 200B-7) and its wafer (e.g., as shown in Example 200B-6) is shown at Figure 2B-2, and the interconnect die may also be referred to as a double-sided interconnect die. The example wafer of Example 200B-6 may, for example, share any or all of the characteristics of the example wafers shown in Figure 2B and discussed herein (e.g., Examples 200B-1 and/or 200B-2). For example, instance interconnect 216c may share any or all of the characteristics with instance interconnects 216a and/or 216b shown in Figure 2B-1 and discussed herein. For example, interconnect interconnect structure 217b may share any or all of the characteristics with interconnect interconnect structure 217 shown in Figure 2B-1 and discussed herein. For example, any or all of the redistribution (RD) structure 298b, substrate dielectric layer 291b, first conductive trace 292b, first dielectric layer 293b, conductive via 294b, second conductive trace 295b, and second dielectric layer 296b may share any or all of the characteristics with the redistribution (RD) structure 298, substrate dielectric layer 291, first conductive trace 292, first dielectric layer 293, conductive via 294, second conductive trace 295, and second dielectric layer 296 shown in FIG. 2B-1 and discussed herein. Example interconnect die 216c also includes a second set of interconnect die interconnect structures 299 received and/or manufactured on the side of interconnect die 216c opposite to the interconnect die interconnect structure 217b. This type of second interconnect grain interconnect 299 may share any or all of the characteristics with the interconnect grain interconnect 217. In an exemplary embodiment, when the RD structure 298b is built on a support structure (e.g., support structure 290), the second interconnect grain interconnect 299 may be formed first, and the support structure may then be removed, thinned, or planarized (e.g., by grinding, peeling, stripping, etching, etc.).

Similarly, any or all of the exemplary methods and structures shown in U.S. Patent Application No. 15/594,313, which is hereby incorporated herein by reference in its entirety, may be performed by any such interconnecting die 216a, 216b and/or 216c.

It should be noted that one or more or all of the second interconnect die structures 299 may be isolated from other circuit systems of the interconnect die 216c. The interconnect die 216c may also be referred to herein as a dummy structure (e.g., a dummy pillar), an anchoring structure (e.g., an anchoring pillar), etc. For example, any or all of the second interconnect die structures 299 may be formed solely for anchoring the interconnect die 216c to a carrier or RD structure or metal pattern in a later step. It should also be noted that one or more or all of the second interconnect die structures 299 may be electrically connected to traces, which may, for example, be connected to an electronic device circuit system of a die attached to the interconnect die 216c. Such structures may be referred to, for example, as active structures (e.g., active pillars), etc.

Typically, block 115 may include receiving, manufacturing, and/or preparing interconnecting dies. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of receiving, manufacturing, and/or preparing such dies or any particular characteristics of such interconnecting dies.

Example method 100 may include receiving, manufacturing, and/or preparing a first carrier at block 120. Block 120 may include any of the receiving, manufacturing, and/or preparing carriers in various ways, and non-limiting examples thereof are provided herein. For example, block 120 may share any or all of the characteristics with other carrier receiving, manufacturing, and/or preparing steps discussed herein. Various example states of block 120 are shown at example 200C in FIG2C.

Block 120 may include, for example, receiving a carrier from an upstream manufacturing process in the same facility or geographical location. Block 120 may also include, for example, receiving a carrier from a supplier (e.g., from a foundry, etc.).

The received, manufactured, and/or prepared carrier 221 may include any of a variety of characteristics. For example, carrier 221 may include semiconductor wafers or panels (e.g., typical semiconductor wafers, low-grade semiconductor wafers utilizing silicon of a lower grade than that used in the functional grains discussed herein, etc.). As another example, carrier 221 may include metals, glass, plastics, etc. Carrier 221 may be, for example, reusable or destructible (e.g., single-use, multi-use, etc.).

The carrier 221 may include any of a variety of shapes. For example, the carrier may be wafer-shaped (e.g., circular, etc.), plate-shaped (e.g., square, rectangular, etc.), etc. The carrier 221 may have any of a variety of lateral dimensions and/or thicknesses. For example, the carrier 221 may have the same or similar lateral dimensions and/or thicknesses as the functional grains and/or wafers connecting the grains discussed herein. As another example, the carrier 221 may have the same or similar thicknesses as the functional grains and/or wafers connecting the grains discussed herein. The scope of this disclosure is not limited to any particular carrier characteristics (e.g., material, shape, size, etc.).

Example 200C shown in Figure 2C includes an adhesive material 223. The adhesive material 223 may include any of various types of adhesives. For example, the adhesive may be a liquid, paste, tape, etc.

The adhesive 223 can be of any size. For example, the adhesive 223 can cover the entire top side of the first carrier 221. Or, for example, the adhesive can cover the central portion of the top side of the first carrier 221 while leaving the outer edges of the top side of the first carrier 221 uncovered. Or, for example, the adhesive can cover the corresponding portion of the top side of the first carrier 221 that corresponds in position to a future location of a functional die in a single electronic package.

The thickness of the adhesive 223 can be greater than the height of the second grain interconnect structure 214, and therefore also greater than the height of the first grain interconnect structure 213 (e.g., greater by 5%, 10%, 20%, etc.).

Example carrier 221 may share any or all of the characteristics with any carrier discussed herein. For example, but not limited to, the carrier may not have a signal distribution layer, but may include one or more signal distribution layers. Such structures and examples of their formation are illustrated in example 600A of Figure 6A and discussed herein.

Typically, block 120 may include receiving, manufacturing, and/or preparing a carrier. Therefore, the scope of this disclosure should not be limited by any particular conditions of receiving a carrier, any particular manner of manufacturing a carrier, and/or any particular manner of preparing such a carrier for use.

Example method 100 may include coupling (or mounting) a functional die to a carrier at block 125 (e.g., coupling to the top side of a non-conductive carrier, coupling to a metal pattern on the top side of the carrier, coupling to an RD structure on the top side of the carrier, etc.). Block 125 may include performing such coupling in any of a variety of ways, and non-limiting examples are provided herein. For example, block 125 may, for instance, share any or all of the characteristics with other die mounting steps discussed herein. Various example states of block 125 are presented in Example 200D shown in Figure 2.

For example, functional dies 201 to 204 (e.g., any one of functional dies 211 and 212) can be received as individual dies. As another example, one or more of functional dies 201 to 204 can be received on a single wafer, or one or more of functional dies 201 to 204 can be received on multiple corresponding wafers (e.g., as shown in examples 200A-1 and 200A-3), and so on. In the case where one or two of the functional dies are received in wafer form, the functional die can be diced from the wafer. It should be noted that if any functional die 201 to 204 is received on a single MPW, then such a functional die can be diced from the wafer as an attachment device (e.g., connected to block silicon).

Block 125 may include placing functional dies 201 to 204 within an adhesive layer 223. For example, a second die interconnect structure 214 and a first die interconnect structure 213 may be fully (or partially) inserted into the adhesive layer 223. As discussed herein, the adhesive layer 223 may be thicker than the height of the second die interconnect structure 214 such that when the bottom surfaces of the dies 201 to 204 contact the top surface of the adhesive layer 223, the bottom end of the second die interconnect structure 214 does not contact the carrier 221. However, in an alternative embodiment, the adhesive layer 223 may be thinner than the height of the second die interconnect structure 214, but still thick enough to cover at least a portion of the first die interconnect structure 213 when the dies 201 to 204 are placed on the adhesive layer 223.

Block 125 may include functional dies 201 to 204 placed using, for example, a die pick-and-place machine.

It should be noted that although the figures herein generally depict functional dies 201 to 204 (and their interconnections) as similar in size and shape, such symmetry is not essential. For example, functional dies 201 to 204 may have different corresponding shapes and sizes, and may have different types and/or numbers of interconnections, etc. It should also be noted that functional dies 201 to 204 (or any so-called functional die discussed herein) may be semiconductor dies, but may also be any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies, packaged dies, etc.). Therefore, the scope of this disclosure should not be limited by the characteristics of functional dies 201 to 204 (or any so-called functional die discussed herein).

Typically, block 125 may include coupling (or mounting) functional dies to a carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such coupling is performed or by any particular characteristic of such functional dies, interconnects, carriers, attachments, etc.

Example method 100 may include an encapsulation at block 130. Block 130 may include any of these encapsulations implemented in various ways, and non-limiting examples are provided herein. Various instance forms of block 130 are presented in example 200E shown in Figure 2E. Block 130 may, for example, share any or all of the characteristics with other encapsulations discussed herein.

Cube 130 may include, for example, performing wafer (or panel) level molding processes. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to the individual module dicing. Referring to the example embodiment 200E shown in FIG2E, encapsulation material 226' may cover at least part (or all) of the top side of adhesive 223, the top side of functional dies 201 to 204, the lateral side surfaces of functional dies 201 to 204, and so on. Encapsulation material 226' may also, for example, cover any portion of the second grain interconnect structure 214, the first grain interconnect structure 213, and the bottom surface of the functional dies 201 to 204 exposed from 223 (if any of such components is exposed).

Encapsulation material 226' may include any of the various types of encapsulation materials, such as molding materials, any dielectric materials presented herein, etc.

Although the encapsulation material 226' (as shown in Figure 2E) is shown to cover the top side of the functional grains 201 to 204, any or all of such top sides (or any corresponding portion of such top sides) may be exposed from the encapsulation material 226 (as shown in Figure 2F). Block 130 may include, for example, initially forming an encapsulation material 226 in which the top side of the grains is exposed (e.g., using film-assisted molding, grain sealing molding, etc.); forming an encapsulation material 226' and then performing a thinning process (e.g., performed at block 135) to thin the encapsulation material 226' to a point sufficient to expose the top side of any or all functional grains 201 to 204; forming an encapsulation material 226' and then performing a thinning process (e.g., performed at block 135) to thin the encapsulation material but still retaining a portion of the encapsulation material 226' covering the top side of any or all functional grains 201 to 204 (or any corresponding portion thereof); etc.

Typically, block 130 may include an encapsulation. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such encapsulation is performed or by the characteristics of any particular type of encapsulation material or its configuration.

Example method 100 may include grinding encapsulating material at block 135. Block 135 may include performing such grinding (or any thinning or planarization) in any of various ways, and non-limiting examples of this are provided herein. Block 135 may, for example, share any or all of the characteristics with other grinding (or thinning) blocks (or steps) discussed herein. Various example forms of block 135 are presented in example 200F shown in Figure 2F.

As discussed herein, in various embodiment examples, the encapsulating material 226' may initially be formed to a thickness greater than the final desired thickness. In such embodiment examples, block 135 may be executed to grind (or otherwise thin or planarize) the encapsulating material 226'. In embodiment 200F shown in FIG. 2F, the encapsulating material 226' has been ground to form the encapsulating material 226. The top surface of the ground (or thinned or planarized) encapsulating material 226 is coplanar with the top surfaces of the functional grains 201 to 204, thus exposing the functional grains from the encapsulating material 226. It should be noted that in various embodiment examples, one or more of the functional grains 201 to 204 may be exposed, while one or more of the functional grains 201 to 204 may remain covered by the encapsulating material 226. It should be noted that, if performed, this type of polishing operation does not require exposing the top side of the functional grains 201 to 204.

In an example embodiment, block 135 may include grinding (or thinning or planarizing) the encapsulation material 226' and the back side of any or all functional grains 201 to 204, thereby achieving coplanarity of the top surface of the encapsulation material 226 with one or more of the functional grains 201 to 204.

Typically, block 135 may include abrasive encapsulating material. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such abrasion (or thinning or planarization).

Example method 100 may include an attached second carrier at block 140. Block 140 may include any of the attached second carriers in various ways, and non-limiting examples are provided herein. For example, block 140 may share any or all of the properties with any carrier discussed herein. Figure 2G illustrates various example states of block 140.

As shown in Example 200G of Figure 2G, the second carrier 231 can be attached to the top side of the encapsulation material 226 and/or the top side of the functional dies 201 to 204. It should be noted that the assembly may still be in wafer (or panel) form at this time. The second carrier 231 can include any of a variety of properties. For example, the second carrier 231 can include a glass carrier, a silicon (or semiconductor) carrier, a metal carrier, a plastic carrier, etc. The cube 140 can include the second carrier 231 attached (or coupled or mounted) in any of a variety of ways. For example, the cube 140 can include attaching the second carrier 231 using an adhesive, a mechanical attachment mechanism, a vacuum attachment, etc.

Typically, block 140 may include a second carrier attached. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of the attached carrier or the characteristics of any particular type of carrier.

Example method 100 may include removal of the first carrier at block 145. Block 145 may include removal of the first carrier in any of various ways, and non-limiting examples are provided herein. For example, block 145 may share any or all of the characteristics with any carrier removal process discussed herein. Various example forms of block 145 are presented in example 200H shown in Figure 2H.

For example, Example 200H of Figure 2H shows the removal of the first carrier 221 (e.g., compared to Example 200G of Figure 2G). Block 145 may include performing this type of carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, or laser release, etc.).

For example, block 145 may include removing the adhesive layer 223 used at block 125 to couple the functional dies 201 to 204 to the first carrier 221. For example, such adhesive layer 223 may be removed together with the first carrier 221 in a single or multi-step process. For example, in an exemplary embodiment, block 145 may include pulling the first carrier 221 from the functional dies 201 to 204 and the encapsulation material 226, wherein the adhesive (or a portion thereof) is removed together with the first carrier 221. For example, block 145 may include the removal of adhesive layer 223 (e.g., the entire adhesive layer 223 and/or any portion of adhesive layer 223 remaining after the removal of the first carrier 221) from functional grains 201 to 204 (e.g., from the bottom surface of functional grains 201 to 204, from the interconnection structure of the first grain 213 and/or the second grain 214, etc.) and encapsulation material 226 using solvents, heat, light or other cleaning techniques.

Typically, block 145 may include the removal of the first carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of removing the carrier or the characteristics of any particular type of carrier.

Example method 100 may include attaching (or coupling or mounting) a connection die to a functional die at block 150. Block 150 may include performing such attachment in any of a variety of ways, and non-limiting examples are provided herein. Block 150 may, for example, share any or all of the characteristics with any die attachment process discussed herein. Various example forms of block 150 are shown at Figure 2I.

For example, the grain interconnection structure 217 of the first interconnecting die 216b (e.g., any or all of such interconnecting dies) can be mechanically and electrically connected to the corresponding first grain interconnection structure 213 of the first functional die 201 and the second functional die 202.

Such interconnects can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In an example embodiment, the first die interconnect 213 and/or the connecting die interconnect 217 may include a solder cap (or other solder structure) that can be reflowed to perform the connection. Such a solder cap may be reflowed, for example, by mass reflow, thermocompression bonding (TCB), etc. In another example embodiment, the connection may be performed instead of using solder by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," and in U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof," the entire contents of each of which are hereby incorporated by reference. The first grain interconnect structure 213 can be attached to the connecting grain interconnect structure 217 using any of the various techniques (e.g., quality reflow, thermo-press bonding (TCB), direct metal-to-metal intermetal bonding, conductive adhesive, etc.).

As shown in Example 200I, the first interconnect structure 213 of the first connecting die 201 is connected to the corresponding interconnect structure 217 of the connecting die 216b, and the first interconnect structure 213 of the second connecting die 202 is connected to the corresponding interconnect structure 217 of the connecting die 216b. During connection, the connecting die 216b provides electrical connection between the various interconnect structures of the first functional die 201 and the second functional die 202 via the RD structure 298 (e.g., as shown in Example 200B-3, etc., of FIG. 2B-1).

In Example 200I shown in FIG2I, the height of the second grain interconnect structure 214 may, for example, be greater than (or equal to) the combined height of the first grain interconnect structure 213, the connecting grain interconnect structure 217, the RD structure 298, and any support layer 290b connecting the grain 216b. Such a height difference may, for example, provide space for a buffer material (e.g., underfill, etc.) between the connecting grain 216b and another substrate (e.g., as shown in Example 200N of FIG2N and discussed herein).

It should be noted that although the instance interconnect die (216b) is shown as a single-sided interconnect die (e.g., similar to instance interconnect die 216b of FIG. 2B-1), the scope of this disclosure is not limited thereto. For example, any or all such instance interconnect dies 216b may be double-sided (e.g., similar to instance interconnect die 216c of FIG. 2B-2).

Typically, block 150 may include attaching (or coupling or mounting) a connection die to a functional die. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such attachment is performed or the characteristics of any particular type of attachment structure.

Example method 100 may include underfilling of the interconnecting die at block 155. Block 155 may include performing such underfilling in any of a variety of ways, of which non-limiting examples are provided herein. Block 155 may, for example, share any or all of the characteristics with any underfilling process discussed herein. Various example forms of block 155 are presented in Example 200J shown in Figure 2J.

It should be noted that an underfill may be applied between the interconnect die 216b and the functional dies 201 to 204. In the case of using pre-applied underfill (PUF), such PUF may be applied to the functional dies 201 to 204 and/or to the interconnect die 216b before the interconnect structure 217 is coupled to the first die interconnect structure 213 of the functional dies 201 to 204 (e.g., at block 150).

Following the attachment performed at block 150, block 155 may include forming an underfill (e.g., capillary underfill, etc.). As shown in Example Embodiment 200J of FIG2J, the underfill material 223 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom side of the connecting die 216b (e.g., orientation as shown in FIG2J), and/or at least a portion (if not all) of the lateral side of the connecting die 216b. The underfill material 223 may also, for example, surround the connecting die interconnect structure 217 and the first die interconnect structure 213 surrounding the functional dies 201 to 204. The bottom filler material 223 may additionally cover, for example, the top side of the functional grains 201 to 204 in the region corresponding to the first grain interconnect structure 213 (as shown in FIG2J orientation).

It should be noted that in various implementations of example method 100, the bottom fill performed at block 155 can be skipped. For example, the bottom fill for the connecting grains can be performed at another block (e.g., at block 175, etc.). Or, for example, this type of bottom fill can be omitted entirely.

Typically, block 155 may include underfill for interconnecting dies. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill.

Example method 100 may include the removal of a second carrier at block 160. Block 160 may include the removal of a second carrier in any of various ways, and non-limiting examples of this are provided herein. For example, block 160 may share any or all of the characteristics with any carrier removal process discussed herein (e.g., with respect to block 145, etc.). Example 200K shown in Figure 2K presents various example states of block 160.

For example, the embodiment 200K shown in Figure 2K does not include the second carrier 231 of the embodiment 200J shown in Figure 2J. It should be noted that such removal may include, for example, cleaning the surface, removing adhesives (if used), etc.

Typically, block 160 may include the removal of a second carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing this type of carrier removal or the characteristics of any particular type of carrier or carrier material being removed.

Example method 100 may include a single-unit cut at block 165. Block 165 may include performing such a single-unit cut in any of various ways, of which non-limiting examples are discussed herein. Block 165 may, for example, share any or all of the characteristics with any single-unit cut discussed herein. Example 200L shown in Figure 2L presents various instance forms of block 165.

As discussed herein, the example assemblies shown herein can be formed on a wafer or panel containing multiple such assemblies (or modules). For example, Example 200K shown in Figure 2K has two assemblies (left and right) bonded together by encapsulation material 226. In such example embodiments, the wafer or panel can be diced (or cut into pieces) to form individual assemblies (or modules). In Example 200L of Figure 2L, the encapsulation material 226 is sawed (or cut, broken, pulled, diced, or otherwise shaped) into two encapsulation material portions 226a and 226b, each corresponding to a corresponding electronic device.

In the example embodiment 200L shown in Figure 2L, only the encapsulation material 226 needs to be trimmed. However, block 165 can include trimming any of various materials (if there is a single-piece cutting line (or trimming line)). For example, block 165 can include trimming underfill material, carrier material, functional and/or interconnecting die material, substrate material, etc.

Typically, block 165 can include single-piece cuts. Therefore, the scope of this disclosure should not be limited to any particular method of single-piece cutting.

Example method 100 may include mounting to a substrate at block 170. Block 170 may, for example, include performing such attachment in any of various ways, of which non-limiting examples are provided herein. For example, block 170 may share any or all of the characteristics with any mounting (or attachment) steps discussed herein (e.g., attaching interconnects, attaching die backsides, etc.). Various example states of block 170 are presented in Example 400M shown in Figure 4M.

Substrate 288 may include any of a variety of characteristics, and non-limiting examples are provided herein. For example, substrate 288 may include a packaging substrate, an insert, a motherboard, a printed circuit board, a functional semiconductor die, a stacking redistribution structure of another device, etc. For example, substrate 288 may include a coreless substrate, an organic substrate, a ceramic substrate, etc. Substrate 288 may, for example, include one or more dielectric layers (e.g., organic and/or inorganic dielectric layers) and/or conductive layers formed on a semiconductor (e.g., silicon, etc.) substrate, a glass or metal substrate, a ceramic substrate, etc. Substrate 288 may, for example, share any or all of the characteristics with the RD structure 298 of FIG. 2B-1, the RD structure 298b of FIG. 2B-2, any RD structure discussed herein, etc. The substrate 288 may include, for example, individual packaged substrates or may include multiple substrates coupled together (e.g., in a panel or wafer), which may later be monolithically cut.

In the example 200M shown in Figure 2M, block 170 may include welding (e.g., using quality reflow, thermoforming, laser welding, etc.) the second grain interconnect structure 214 of functional grains 201 to 202 to corresponding pads (e.g., bonding pads, traces, pads, etc.) or other interconnect structures (e.g., pillars, rods, balls, bumps, etc.) of substrate 288.

It should be noted that in the embodiment where interconnect die 216b is a double-sided interconnect die similar to interconnect die 216c, block 170 may also include a corresponding pad or other interconnect structure for connecting the second set of interconnect die interconnect structures 299 to the substrate 288. However, in embodiment 200M of FIG2M, interconnect die 216b is a single-sided interconnect die. It should be noted that, as discussed herein, because the second grain interconnect structure 214 of functional grains 201 to 202 is taller than the combined height of the first grain interconnect structure 213, the connecting grain interconnect structure 217, and the support layer 290b of the connecting grain 216b, a gap exists between the back side of the connecting grain 216b (the lower side of the connecting grain 216b in FIG. 2M) and the top side of the substrate 288. As shown in FIG. 2N, this gap can be filled with an underfill material.

Typically, block 170 includes mounting (or attaching or coupling) an assembly (or module) that is monolithically cut at block 165 to a substrate. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular type of mounting (or attachment) or any particular mounting (or attachment) structure.

Example method 100 may include underfilling at block 175 between the substrate and the assembly (or module) mounted thereon at block 170. Block 175 may include underfilling in any of various ways, and non-limiting examples thereof are provided herein. Block 175 may share any or all of the characteristics, for example, with any underfill (or encapsulation) process discussed herein (e.g., with respect to block 155, etc.). Various forms of block 175 are presented in example 200N shown in Figure 2N.

Block 175 may include, for example, performing a capillary underfill or injected underfill process after mounting at block 170. Alternatively, in a scenario utilizing pre-applied underfill (PUF), such PUF may be applied to a substrate, a metal pattern of the substrate, and/or its interconnections prior to such mounting. Block 175 may also include performing such underfill using a molding underfill process.

As shown in Example Embodiment 200N of Figure 2N, the underfill material 291 (e.g., any underfill material discussed herein) may completely or partially cover the top side of the substrate 288. The underfill material 291 may also, for example, surround the second grain interconnect structure 214 (and/or the corresponding substrate pad) of the functional grains 201 to 202. The underfill material 291 may, for example, cover the bottom side of the functional grains 201 to 202, the bottom side of the connecting grain 216b, and the bottom side of the encapsulation material 226a. The underfill material 291 may also, for example, cover the lateral surface of the connecting grain 216b and/or the exposed lateral surface of the underfill 223 between the connecting grain 216b and the functional grains 201 to 202. The bottom filler material 291 may, for example, cover the lateral surfaces of the encapsulation material 226a and/or the functional grains 201 to 202 (e.g., all or part of them).

In an embodiment where the bottom filler 223 is not formed, a bottom filler material 291 can be formed instead of the bottom filler 223. For example, referring to embodiment 200N, more bottom filler material 291 can be used instead of bottom filler material 223 in embodiment 200N.

In one embodiment where bottom filler 223 is formed, bottom filler material 291 can be a different type of bottom filler material than bottom filler material 223. In another embodiment, bottom filler materials 223 and 291 can both be the same type of material.

Similar to block 155, you can also skip block 175, for example, leaving space at another block location to be filled with another bottom filler (e.g., a molded bottom filler).

Typically, block 175 includes a bottom fill. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular type of bottom fill or any particular bottom fill material.

Instance method 100 may include further processing at block 190. Such further processing may include any of a variety of features, of which non-limiting examples are provided herein. For example, block 190 may include returning the execution flow of instance method 100 to any of its blocks. As another example, block 190 may include directing the execution flow of instance method 100 to any other method block (or step) discussed herein (e.g., instance method 300 of Figure 3, instance method 500 of Figure 5, etc.).

For example, the cube 190 may include an interconnection structure 299 (e.g., a conductive ball, a bump, a pillar, etc.) formed on the bottom side of the substrate 288.

For example, as shown in Example 2000 of FIG20, block 190 may include encapsulating material 225. Such encapsulating material 225 may, for example, cover the top side of substrate 288, the lateral side of bottom filler 224, the lateral side of encapsulating material 226a, and/or the lateral side of functional grains 201 to 202. In Example 2000 shown in FIG20, the top side of encapsulating material 225, the top side of encapsulating material 226a, and/or the top side of functional grains 201 to 202 may be coplanar.

As discussed herein, underfill 224 may not be formed (e.g., as the underfill formed at block 175). In this case, encapsulating material 225 may be used instead of the underfill. An example 200P of such a structure and method is provided at Figure 2P. In example embodiment 200P, compared to example embodiment 200O shown in Figure 2O, the underfill 224 of example embodiment 200O is replaced by encapsulating material 225 as the underfill.

As discussed herein, bottom filler 223 (e.g., the bottom filler formed at block 155) and bottom filler 224 may not be formed. In this case, encapsulating material 225 may be used instead. An example embodiment 200Q of this type of structure and method is provided at FIG2Q. In example embodiment 200Q, the bottom filler 223 of example embodiment 200P is replaced by encapsulating material 225, in contrast to example embodiment 200P shown in FIG2P.

It should be noted that in any of the example embodiments 200O, 200P, and 200Q shown in Figures 2O, 2P, and 2Q, the lateral sides of the encapsulation material 225 and the substrate 288 may be coplanar.

In the example method 100 illustrated in Figures 1 and 2A to 2Q, various grain interconnect structures (e.g., first grain interconnect structure 213, second grain interconnect structure 214, connecting grain interconnect structure 217 (and/or 299), etc.) are typically formed during the receiving, manufacturing, and/or preparation processes of the grains. For example, such various grain interconnect structures can typically be formed before their respective grains are integrated into the assembly. However, the scope of this disclosure should not be limited by the timing of such example embodiments. For example, any or all of the various grain interconnect structures can be formed after their respective grains are integrated into the assembly. An example method 300 for forming grain interconnect structures at different stages will now be discussed.

Figure 3 shows a flowchart of an example method 300 for manufacturing an electronic device (e.g., a semiconductor package, etc.). Example method 300 may share any or all of the characteristics with, for example, any other example method discussed herein (e.g., example method 100 of Figure 1, example method 500 of Figure 5, example method 700 of Figure 7, etc.). Figures 4A to 4N show cross-sectional views of various illustrative example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to this disclosure. Figures 4A to 4N may illustrate example electronic devices, for example, with the various blocks (or steps) of method 300 of Figure 3. Figures 3 and 4A to 4N will now be discussed together. It should be noted that the order of the instance blocks in method 300 may be changed without departing from the scope of this disclosure.

Example method 300 may begin execution at block 305. Method 300 may begin execution in response to any of a variety of causes or conditions, and non-limiting examples are provided herein. For example, method 300 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 300 may begin execution in response to an operator command to begin. Additionally, for example, method 300 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 300 may include receiving, manufacturing, and/or preparing multiple functional dies at block 310. Block 310 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 310 may share any or all of the characteristics with block 110 of example method 100 shown in FIG. 1 and discussed herein. Various forms of block 310 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A.

Block 310 may include, for example, receiving multiple functional granules from an upstream manufacturing process in the same facility or geographical location. Block 310 may also include, for example, receiving functional granules from a supplier (e.g., from a foundry). Block 310 may also include, for example, any or all features that form multiple functional granules.

In an example embodiment, block 310 may share any or all of the characteristics with block 110 of example method 100 of FIG1, but does not have the first grain interconnect structure 213 and the second grain interconnect structure 214. It will be seen that such grain interconnect structures may be formed later in example method 300 (e.g., at block 347, etc.). Although not shown in FIG4A, each of the functional grains 411 to 412 may, for example, include grain pads and/or under-bump metallization structures on which such grain interconnect structures may be formed.

The functional dies 411 to 412 shown in Figure 4A may, for example, share any or all of the characteristics with the functional dies 211 to 212 shown in Figure 2A (e.g., not having the first die interconnect structure 213 and the second die interconnect structure 214). For example, but not limited to, the functional dies 411 to 412 may include the characteristics of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Typically, block 310 may include receiving, manufacturing, and/or preparing multiple functional dies. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such receiving, manufacturing, and/or preparation, nor by any particular characteristic of such functional dies.

Example method 300 may include receiving, manufacturing, and/or preparing interconnect dies at block 315. Block 315 may include receiving, manufacturing, and/or preparing one or more interconnect dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 315 may share any or all of the characteristics with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example states of block 315 are presented in examples 400B-1 and 400B-2 shown in FIG. 4B.

Interconnecting dies 416a and/or 416b (or their wafers) may include, for example, an interconnecting die interconnect structure 417. The interconnecting die interconnect structure 417 may include any of a variety of characteristics. For example, the formation of the interconnecting die interconnect structure 417 and/or any form thereof may share any or all of the characteristics with the interconnecting die interconnect structure 217 and/or its formation shown in Figures 2B-1 to 2B-2 and discussed herein.

The interconnecting dies 416a and/or 416b (or their wafers) can be formed in any of a variety of ways, and non-limiting examples thereof are provided herein, for example, with respect to interconnecting dies 216a, 216b and/or 216c of Figures 2B-1 to 2B-2.

Typically, block 315 may include receiving, manufacturing, and/or preparing a connection die. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such receiving, manufacturing, and/or preparation, nor by any particular characteristic of such a connection die.

Example method 300 may include receiving, manufacturing, and/or preparing a first carrier at block 320. Block 320 may include receiving, manufacturing, and/or preparing a first carrier in any of various ways, of which non-limiting examples are provided herein. Block 320 may share any or all of the features, for example, with other carrier receiving, manufacturing, and/or preparation steps discussed herein (e.g., with block 120 of example method 100 of FIG. 1).

Various instances of block 320 are presented in Example 400C shown in Figure 4C. For example, carrier 421 may share any or all of the properties with carrier 221 of Figure 2C. As another example, adhesive 423 may share any or all of the properties with adhesive 223 of Figure 2C. However, it should be noted that since adhesive 423 does not receive the grain interconnection structure of functional grains (e.g., at block 325), adhesive 423 need not be as thick as adhesive 223.

Typically, block 320 may include receiving, manufacturing, and/or preparing a first carrier. Therefore, the scope of this disclosure should not be limited by any particular conditions of receiving a carrier, any particular manner of manufacturing a carrier, and/or any particular manner of preparing such a carrier for use.

Example method 300 may include, at block 325, coupling (or mounting) a functional die to a carrier (e.g., coupling to the top side of a non-conductive carrier, coupling to a metal pattern on the top side of the carrier, coupling to an RD structure on the top side of the carrier, etc.). Block 325 may include performing such coupling in any of a variety of ways, and non-limiting examples are provided herein. For example, block 325 may share any or all of the characteristics, for example, with other die mounting steps discussed herein (e.g., at block 125 of example method 100 of FIG. 1, etc.).

Various instance types of block 325 are presented in instance 400D shown in Figure 4D. Instance 400D may share any or all of the characteristics with instance 200D of Figure 2D. For example, functional dies 401 to 404 (e.g., instances of dies 411 and/or 412) may share any or all of the characteristics (e.g., dies 211 and/or 212) with functional dies 201 to 204 of Figure 2D (e.g., instances of dies 211 and/or 212) (e.g., die interconnect structures 213 and 214 do not extend into adhesive 223).

In Example 400D, the corresponding active sides of functional dies 401 to 404 are shown coupled to adhesive 423, but the scope of this disclosure is not limited to this type of orientation. In alternative embodiments, the corresponding non-active sides of functional dies 401 to 404 may be mounted to adhesive 423 (e.g., where functional dies 401 to 404 may have through-silicon vias or other structures for later connection to connecting dies, etc.).

Typically, block 325 may include coupling functional dies to the carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such coupling is performed.

Example method 300 may include an envelope at block 330. Block 330 may include such an envelope in any of various ways, and non-limiting examples of this are provided herein. For example, block 330 may share any or all of the characteristics with other envelopes discussed herein (e.g., block 130 with example method 100 of FIG1, etc.).

Various instance forms of block 330 are presented in example 400E shown in Figure 4E. For example, encapsulating material 426' (and/or its formation) may share any or all of the properties with encapsulating material 226' (and/or its formation) of Figure 2E.

Typically, block 330 may include an encapsulation. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 300 may include grinding (or otherwise thinning or planarizing) the encapsulating material at block 335. Block 335 may include performing such grinding (or any thinning or planarizing process) in any of various ways, and non-limiting examples are provided herein. For example, block 335 may share any or all of the characteristics with other grinding (or thinning or planarizing) discussed herein (e.g., with block 135 of example method 100 of FIG. 1, etc.).

Various instance forms of block 335 are presented in example 400F shown in Figure 4F. The encapsulating material 426 (and/or its formation) of the instance milled (or thinned or planarized, etc.) may share any or all properties with the encapsulating material 226 (and/or its formation) of Figure 2F.

Typically, block 335 may include grinding (or otherwise thinning or planarizing) the encapsulating material. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such grinding (or thinning or planarizing).

Example method 300 may include an attached second carrier at block 340. Block 340 may include any of the attached second carriers in various ways, and non-limiting examples of such attachments are provided herein. For example, block 340 may share any or all of the properties with any carrier discussed herein (e.g., with block 140 of example method 100 of FIG1).

Various instance types of block 340 are shown in instance 400G in Figure 4G. The second carrier 431 (and/or its attachments) may, for example, share any or all of the properties with the second carrier 231 of Figure 2G.

Typically, block 340 may include an attached second carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of attachment and/or the characteristics of any particular type of second carrier.

Example method 300 may include removal of the first carrier at block 345. Block 345 may include removal of the first carrier in any of various ways, and non-limiting examples thereof are provided herein. For example, block 345 may share any or all features with any carrier removal discussed herein (e.g., block 145 of example method 100 shown in FIG. 1).

The instance states of block 345 are shown in instance 400H in Figure 4H-1. For example, the first carrier 421 has been removed relative to instance 400G.

Typically, block 345 may include the removal of the first carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such removal.

Example method 300 may include forming an interconnection at block 347. Block 347 may include any of the forming interconnections in various ways, and non-limiting examples of such forming interconnections are provided herein. For example, block 347 may share any or all of the characteristics with other interconnection forming processes (or steps) or blocks discussed herein (e.g., with respect to block 110 shown in Figure 1 and example method 100 discussed herein).

Various instance forms of block 347 are shown at instance 400H-2 in Figure 4H-2. The first grain interconnect structure 413 (and/or its formation) of Figure 4H-2 may share any or all properties with the first grain interconnect structure 213 (and/or its formation) of Figure 2A. Similarly, the second grain interconnect structure 414 (and/or its formation) of Figure 4H-2 may share any or all properties with the second grain interconnect structure 214 (and/or its formation) of Figure 2A.

Example embodiment 400H-2 includes a passivation layer 417 (or a re-passivation layer). Although not shown in the example embodiment of FIG2A and/or other example embodiments presented herein, such example embodiments may also include such a passivation layer 417 (e.g., between functional grains and grain interconnects and/or around the substrate of the grain interconnects, between connecting grains and connecting grain interconnects and/or around the substrate of the connecting grain interconnects, etc.). For example, in a scenario where such a passivation layer 417 has not yet been formed prior to block 347, block 347 may include forming such a passivation layer 417. It should be noted that the passivation layer 417 may also be omitted.

In an example embodiment, where functional grains are received or formed by an external inorganic dielectric layer, the passivation layer 417 may include an organic dielectric layer (e.g., any organic dielectric layer discussed herein).

The passivation layer 417 (and/or its formation) may include the characteristics of any passivation (or mass-electric) layer (and/or its formation) discussed herein. The first grain interconnect structure 413 and the second grain interconnect structure 414 may be electrically connected to the functional grains 401 to 404, for example, through corresponding holes in the passivation layer 417.

Although a passivation layer 417 is displayed on the molding layer 426 and the functional grains 401 to 404, the passivation layer 417 may also be formed only on the functional grains 401 to 404 (e.g., at block 310). In this type of embodiment, the outer surface of the passivation layer 417 (e.g., the upward-facing surface of the passivation layer 417 in FIG. 4H-2) may be coplanar with the corresponding surface of the encapsulation material 426 (e.g., the upward-facing surface of the encapsulation material 426 in FIG. 4H-2).

Typically, block 347 may include the formation of interconnected structures. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of such formation or any particular characteristic of interconnected structures.

Example method 300 may include attaching (or coupling or mounting) a connection die to a functional die at block 350. Block 350 may include performing such attachment in any of a variety of ways, and non-limiting examples of this are provided herein. For example, block 350 may share any or all of the characteristics, for example, with any die attachment discussed herein (e.g., with block 150 of example method 100 of FIG1).

Various instance types of block 350 are presented in example 400I shown in Figure 4I. The interconnection of connection die 416b, functional dies 401 to 404 and/or such dies to each other may, for example, share any or all characteristics with the interconnection of connection die 216b, functional dies 201 to 204 and/or such dies to each other in example 200I shown in Figure 2I.

Typically, block 350 may include attaching a connection die to a functional die. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such attachment is performed and/or the characteristics of any particular structure used to perform such attachment.

Example method 300 may include underfilling of the interconnecting grains at block 355. Block 355 may include performing such underfilling in any of a variety of ways, of which non-limiting examples are provided herein. Block 355 may, for example, share any or all of the characteristics with any underfilling discussed herein (e.g., with blocks 155 and/or 175, etc., of example method 100 of FIG1).

Various instance types of block 355 are presented in example 400J shown in Figure 4J. For example, the bottom fill 423 (and/or its formation) of Figure 4J may share any or all of the properties with the bottom fill 223 (and/or its formation) of Figure 2J. It should be noted that, as with any bottom fill discussed herein, various instance embodiments may omit the execution of such bottom fills.

Typically, block 355 may include underfill for connecting grains. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill material.

Example method 300 may include the removal of a second carrier at block 360. Block 360 may include the removal of a second carrier in any of various ways, and non-limiting examples thereof are provided herein. For example, block 360 may share any or all of the features with any carrier removal discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG1, with block 345, etc.).

The various instance forms of block 360 are presented in instance 400K shown in Figure 4K. For example, comparing Figure 4K with Figure 4J, the second carrier 431 has been removed.

Typically, block 360 may include the removal of a second carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such removal.

Example method 300 may include a granular cut at block 365. Block 365 may include performing such a granular cut in any of various ways, of which non-limiting examples are discussed herein. Block 365 may, for example, share any or all of the characteristics with any granular cut discussed herein (e.g., as discussed with respect to block 165 of example method 100 of FIG1).

Various instance forms of block 365 are presented in example 400L shown in Figure 4L. The monolithic cut structure (e.g., corresponding to two encapsulation material portions 426a and 426b) may share any or all of the characteristics with the monolithic cut structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b).

Typically, a block 365 may include single-piece cuts. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of single-piece cutting.

Example method 300 may include mounting to a substrate at block 370. Block 370 may, for example, include performing such mounting (or coupling or attachment) in any of various ways, of which non-limiting examples are provided herein. For example, block 370 may share any or all of the characteristics with any mounting (or coupling or attachment) discussed herein (e.g., block 170, etc., with respect to example method 100 shown in FIG. 1).

Figure 4M shows various instance types of block 370 in example 400M. For example, substrate 488 (and/or attachment to such substrate 288) may share any or all characteristics with substrate 288 (and/or attachment to such substrate 288) of example 200M in Figure 2M.

Typically, block 370 may include mounting to a substrate. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of mounting to a substrate or the characteristics of any particular type of substrate.

Example method 300 may include underfilling at block 375 between the substrate and the assembly (or module) mounted thereon at block 370. Block 375 may include underfilling performed in any of a variety of ways, of which non-limiting examples are provided herein. Block 375 may, for example, share any or all of the characteristics with any underfill (or encapsulation) process discussed herein (e.g., with respect to block 355, blocks 155 and 175, etc., of example method 100 of FIG. 1).

Various forms of block 375 are presented in example 400N shown in Figure 4N. The bottom fill 424 (and/or its formation) may share any or all of the characteristics, for example, with the bottom fill 224 (and/or its formation) shown in example 200N of Figure 2N. It should be noted that, as with any bottom fill discussed herein, the bottom fill of block 375 may be skipped or may be performed at different points in the method.

Typically, block 375 may include underfill between the substrate and the assembly mounted to the substrate. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of mounting to the substrate or the characteristics of any particular type of substrate.

Instance method 300 may include continued processing at block 390. Such continued processing may include any of a variety of properties, of which non-limiting instances are provided herein. For example, block 390 may share any or all of the properties with block 190 of instance method 100 of Figure 1 discussed herein.

For example, block 390 may include returning the execution flow of instance method 300 to any of its blocks. As another example, block 390 may include directing the execution flow of instance method 300 to any other method block (or step) discussed herein (e.g., instance method 100 of Figure 1, instance method 500 of Figure 5, instance method 700 of Figure 7, etc.).

For example, the cube 390 may include an interconnection structure 499 (e.g., a conductive ball, a bump, a pillar, etc.) formed on the bottom side of the substrate 488.

For example, as shown in Example 200O of Figure 2O, Example 200P of Figure 2P and Example 200Q of Figure 2Q, block 390 may include forming an encapsulation material and/or a bottom filler (or skip forming an encapsulation material and/or a bottom filler).

In the various embodiments discussed herein, the functional die is mounted to the carrier before the interconnect die is attached to the functional die. The scope of this disclosure is not limited to this mounting sequence. Non-limiting embodiments are now presented in which the interconnect die is mounted to the carrier before the interconnect die is attached to the functional die.

Figure 5 shows a flowchart of an example method 500 for manufacturing an electronic device in various forms according to this disclosure. Example method 500 may, for example, share any or all characteristics with any other example method discussed herein (e.g., example method 100 of Figure 1, example method 300 of Figure 3, example method 700 of Figure 7, etc.). Figures 6A to 6M show cross-sectional views of illustrative example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices in various forms according to this disclosure. Figures 6A to 6M may, for example, illustrate example electronic devices at various blocks (or steps) of method 500 of Figure 5. Figures 5 and 6A to 6M will now be discussed together. It should be noted that the order of the instance blocks in Method 500 may be changed without departing from the scope of this disclosure.

Example method 500 may begin execution at block 505. Method 500 may begin execution in response to any of a variety of causes or conditions, and non-limiting examples are provided herein. For example, method 500 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 500 may begin execution in response to an operator command to begin. Additionally, for example, method 500 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 500 may include receiving, manufacturing, and/or preparing multiple functional dies at block 510. Block 510 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 510 may share any or all of the characteristics with block 310 of example method 300 shown in FIG. 3 and discussed herein. Various forms of block 510 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A. It should be noted that block 510 may also share any or all of the characteristics, for example, with block 110 of example method 100 shown in FIG. 1 and discussed herein.

The functional dies 611a and 612a (and/or their formations) shown in many of the figures in Figures 6A to 6M may share any or all of the characteristics with, for example, the functional dies 411 and 412 (and/or their formations) of Figure 4A, and the functional dies 211 to 212 (and/or their formations) of Figure 2A. For example, but not limited to, the functional dies 611 and 612 may include the characteristics of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Typically, block 510 may include receiving, manufacturing, and/or preparing multiple functional dies. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such receiving and/or manufacturing, nor by any particular characteristic of such functional dies.

Example method 500 may include receiving, manufacturing, and/or preparing interconnect dies at block 515. Block 515 may include receiving and/or manufacturing multiple interconnect dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 515 may share any or all of the characteristics with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example states of block 515 are presented in examples 200B-1 and 200B-7 shown in FIG. 2B-1 to 2B-2. It should be noted that block 515 may also share any or all of the characteristics, for example, with block 315 of example method 300 shown in FIG. 3 and discussed herein.

The interconnecting dies 616b and interconnecting dies interconnecting structures 617 (and/or their formations) shown in many of the figures in Figures 6A to 6M may, for example, share any or all of the characteristics with the interconnecting dies 216b and interconnecting dies interconnecting structures 217 (and/or their formations) in Figures 2B-1 to 2B-2.

It should be noted that the interconnecting grain interconnect structure 617 (and/or its formation) may, for example, share any or all of the characteristics with the first grain interconnect structure 213 (and/or its formation). For example, in an exemplary embodiment, instead of forming a first grain interconnect structure such as the first grain interconnect structure 213 of FIG. 2A on the functional grains 211/212, the same or similar interconnecting grain interconnect structure 617 may be formed on the interconnecting grain 616b.

Typically, block 515 may include receiving, manufacturing, and/or preparing interconnecting dies. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of receiving, manufacturing, and/or preparing such dies or any particular characteristics of such interconnecting dies.

Example method 500 may include at block 520 a carrier having a signal redistribution (RD) structure (or distribution structure) thereon. Block 520 may include performing such receiving, manufacturing and/or preparation in any of various ways, and non-limiting examples thereof are provided herein.

Block 520 may share any or all characteristics with any or all carriers discussed herein that receive, manufacture, and/or prepare (e.g., block 120 with respect to example method 100 of FIG1, block 320 with respect to example method 300 of FIG3, etc.). Various instance forms of block 520 are provided in example 600A of FIG6A.

As discussed herein, any or all carriers discussed herein may include, for example, only bulk materials (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal redistribution (RD) structures on (or in lieu of) bulk materials. Block 520 provides examples of receiving, manufacturing, and/or preparing such carriers.

Block 520 may include an RD structure 646a formed on a block carrier 621a in any of various ways, of which non-limiting examples are presented herein. In an exemplary embodiment, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to a second grain interconnect structure 614 (formed later), which will ultimately connect to functional grains 611 and 612 (connected later).

Figure 6A illustrates an example in which the RD structure 646a includes three dielectric layers 647 and three conductive layers 648. This number of layers is merely an example, and the scope of this disclosure is not limited thereto. In another embodiment, the RD structure 646a may include only a single dielectric layer 647 and a single conductive layer 648, two of each layer, etc. The example redistribution (RD) structure 646a is formed on a bulk carrier material 621a.

The dielectric layer 647 can be formed from any of a variety _of materials (e.g., _Si3N4 , _SiO2 , SiON, PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 647 can be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 647 can, for example, be patterned to expose various surfaces (e.g., exposing the lower traces or pads of the conductive layer 648).

The conductive layer 648 can be formed from any of various materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 648 can be formed using any of various processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 646a may include, for example, conductors exposed at its outer surface (e.g., at the top surface of example 600A). Such exposed conductors may be used, for example, for attaching (or forming) grain interconnect structures (e.g., at block 525, etc.). In such embodiments, the exposed conductors may include pads and may include, for example, under-bump metal (UBM) formed thereon to enhance the attachment (or formation) of the grain interconnect structures. Such under-bump metal may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

The replicating structures and/or their formations are provided in U.S. Patent Application No. 14/823,689, filed August 11, 2015, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” and U.S. Patent No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF,” the contents of each of which are hereby incorporated herein by reference in their entirety.

The redistribution structure 646a may, for example, perform fan-out redistribution of at least some electrical connections, such as laterally moving at least a portion of the electrical connections to the (to be formed) die interconnect structure 614 to locations outside the coverage areas of the functional dies 611 and 612 to which such die interconnect structure 614 will be attached. Alternatively, the redistribution structure 646a may perform fan-in redistribution of at least some electrical connections, such as laterally moving at least a portion of the electrical connections to the (to be formed) die interconnect structure 614 to locations inside the coverage areas of the (to be connected) connecting die 616b and/or to locations inside the coverage areas of the (to be connected) functional dies 611 and 612. The redistribution structure 646a can also provide, for example, connectivity between functional dies 611 and 612 (e.g., in addition to the connectivity provided by the connecting die 616b).

In various implementation schemes, block 520 may include a first portion 646a that forms only the entire RD structure 646, wherein a second portion 646b of the entire RD structure 646 may be formed later (e.g., at block 570).

Typically, block 520 may include a carrier that receives, manufactures, and/or prepares to have a signal redistribution (RD) structure thereon. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of manufacturing such carriers and/or signal redistribution structures or any particular characteristics of such carriers and/or signal redistribution structures.

Example method 500 may include forming a high-grain interconnect structure on the RD structure (e.g., as provided at block 520) at block 525. Block 525 may include forming a high-grain interconnect structure on the RD structure in any of various ways, and non-limiting examples thereof are provided herein.

Block 525 may share any or all characteristics (e.g., second grain interconnection formation characteristics, etc.) with any or all functional grain receiving, manufacturing and/or preparation discussed herein (e.g., the formation of block 110 and second grain interconnection structure 214 and/or the formation of first grain interconnection structure 213 in respect of example method 100 of FIG1, the formation of block 347 and second grain interconnection structure 414 in respect of example method 300 of FIG3, etc.).

Various instance forms of block 525 are provided in example 600B of Figure 6B. The high interconnect structure 614 (and/or its formation) may share any or all of the properties with the second grain interconnect structure 214 (and/or its formation) of Figure 2A and/or with the second grain interconnect structure 414 (and/or its formation) of Figure 4H-2.

Typically, block 525 may include a high-grain interconnect structure formed on the RD structure (e.g., as provided at block 520). Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such a high-grain interconnect structure is formed and/or the characteristics of any particular type of high interconnect structure.

Example method 500 may include mounting a connection die to the RD structure at block 530 (e.g., as provided at block 520). Block 530 may include performing such mounting (or attachment or coupling) in any of various ways, and non-limiting examples of this are provided herein. Block 530 may, for example, share any or all of the characteristics of any of the die attachments discussed herein (e.g., block 325 of example method 300 shown in FIG. 3 and discussed herein, block 125 of example method 100 shown in FIG. 1 and discussed herein, etc.). Various example states of block 530 are presented in example 600C shown in FIG. 6C.

Block 530 may, for example, include attaching the back side of the connecting die 616b to the RD structure 646a using a die-attach adhesive (e.g., tape, liquid, paste, etc.). Although Figure 6C shows the connecting die 616b coupled to the dielectric layer of the RD structure 646a, in other embodiments, the back side of the connecting die 616b may be coupled to a conductive layer (e.g., to provide additional structural support for enhanced heat dissipation).

Additionally, as discussed herein, any interconnect die discussed herein may be bilateral. In such example embodiments, the back-side interconnect may be electrically connected to the corresponding interconnect of the RD structure 646a (e.g., pads, solder pads, bumps, etc.).

Typically, block 530 may include mounting a connector die to the RD structure (e.g., as provided at block 520). Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of mounting the connector die.

Example method 500 may include an encapsulation at block 535. Block 535 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. Block 535 may, for example, share any or all of the characteristics with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, etc.). Various example states of block 535 are shown in FIG. 6D.

Block 535 may include, for example, performing wafer (or panel) level molding processes. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to the individual module dicing. Referring to the example embodiment 600D shown in Figure 6D, encapsulation material 651' may cover at least part (or all) of the top side of RD structure 646a, the high pillar 614, the die interconnect structure 617, the top side (or active side or front side) of die 616b, and the lateral side surface of die 616b.

Although the encapsulating material 651' (as shown in FIG. 6D) is shown to cover the top end of the high interconnect structure 614 and the top end of the connecting grain interconnect structure 617, any or all of these ends may be exposed from the encapsulating material 651' (as shown in FIG. 6E). Block 535 may, for example, include initially forming the encapsulating material 651' with the top ends of various interconnects exposed or protruding (e.g., using film-assisted molding, grain sealing molding, etc.). Alternatively, block 535 may include forming the encapsulating material 651' followed by a thinning (or planarization or grinding) process (e.g., performed at block 540) to thin the encapsulating material 651' sufficiently to expose the top sides of any or all of the high interconnect structure 614 and the connecting grain interconnect structure 617, etc.

Typically, block 535 may include an encapsulation. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such encapsulation is performed or by the characteristics of any particular type of encapsulation material or its configuration.

Example method 500 may include a grinding encapsulating material and/or various interconnections at block 540. Block 540 may include performing such grinding (or any thinning or planarization) in any of various ways, and non-limiting examples of this are provided herein. Various example forms of block 540 are presented in example 600E shown in Figure 6E. Block 540 may, for example, share any or all of the characteristics with other grinding (or thinning or planarization) blocks (or steps) discussed herein.

As discussed herein, in various example embodiments, the encapsulation material 651' may initially be formed to a thickness greater than the final required thickness, and/or the high interconnect structure 614 and the interconnecting grain structure 617 may initially be formed to a thickness greater than the final required thickness. In such example embodiments, block 540 may be executed to grind (or additionally thin or planarize) the encapsulation material 651', the high interconnect structure 614, and/or the interconnecting grain structure 617. In example 600E shown in Figure 6E, the encapsulation material 651, the high interconnect structure 614, and/or the interconnecting grain structure 617 have been ground to produce the encapsulation material 651 and interconnect structures 613 and 617 (as shown in Figure 6E). The top surfaces of the milled encapsulating material 651, the top surfaces of the highly interconnected structure 614, and/or the top surfaces of the grain interconnected structure 617 may, for example, be coplanar.

It should be noted that in various implementation schemes, such as using chemical or mechanical processes to make the encapsulating material 651 thinner than the interconnecting structures 614 and/or 617, or using film-assisted and/or sealing molding processes at block 535, the top surface of the high interconnecting structure 614 and/or the top surface of the connecting grain interconnecting structure 617 may protrude from the top surface of the encapsulating material 651.

Typically, block 540 may include polished (or thinned or planarized) encapsulating material and/or various interconnect structures. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such polishing (or thinning or planarization).

Example method 500 may include attaching (or coupling or mounting) functional dies to a high interconnect structure and connecting die interconnect structures at block 545. Block 545 may include performing such attachments in any of a variety of ways, and non-limiting examples are provided herein. Block 545 may, for example, share any or all of the characteristics with any die attachment process discussed herein. Various example states of block 545 are presented in example 600F shown in Figure 6F.

For example, the grain interconnect structure (e.g., pads, bumps, etc.) of the first functional grain 611a can be mechanically and electrically connected to the corresponding high interconnect structure 614 and connected to the corresponding connecting grain interconnect structure 617. Similarly, the grain interconnect structure (e.g., pads, bumps, etc.) of the second functional grain 612a can be mechanically and electrically connected to the corresponding high interconnect structure 614 and connected to the corresponding connecting grain interconnect structure 617.

Such interconnect structures can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In an exemplary embodiment, the corresponding interconnect structures of the high-grain interconnect structure 614, the connecting grain interconnect structure 617, and/or the first functional grain 611a and the second functional grain 612a may include solder caps (or other solder structures) that can be reflowed to perform the connection. Such solder caps can be reflowed, for example, by quality reflow, thermo-press bonding (TCB), etc. In another exemplary embodiment, the connection can be performed instead of using solder by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," and U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof," the entire contents of each of which are hereby incorporated by reference. The functional grain interconnect structure can be attached to the high interconnect structure 614 and the connecting grain interconnect structure 617 using any of the various techniques (e.g., quality reflow, thermo-press bonding (TCB), direct metal-to-metal intermetal bonding, conductive adhesive, etc.).

As shown in Example Embodiment 600F, a first interconnecting die 617 of the connecting die 616b is connected to a corresponding interconnecting structure of the first functional die 611a, and a second interconnecting die 617 of the connecting die 616b is connected to a corresponding interconnecting structure of the second functional die 612a. During connection, the connecting die 616b provides electrical connections between the various die interconnecting structures of the first functional die 611a and the second functional die 612a via the RD structure 298 of the connecting die 616b (e.g., as shown in Example 200B-4, etc., of FIG. 2B-1).

In Example 600F shown in Figure 6F, the height of the high interconnect structure 614 can be, for example, equal to (or greater than) the combined height of the connecting die interconnect structure 217 and the support layer 290b of the connecting die 616b, as well as the adhesive or other components used to attach the connecting die 616b to the RD structure 646a.

Typically, block 545 may include attaching (or coupling or mounting) functional dies to a high interconnect structure and connecting die interconnect structures. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such attachments or the characteristics of any particular type of attachment structure.

Example method 500 may include underfilling of the functional grain at block 550. Block 550 may include performing such underfilling in any of various ways, and non-limiting examples thereof are provided herein. Block 550 may, for example, share any or all of the characteristics with any underfilling discussed herein (e.g., with blocks 155 and/or 175 of example method 100 of FIG. 1, with blocks 355 and/or 375 of example method 300 of FIG. 3, etc.). Various example states of block 550 are presented in example 600G shown in FIG. 6G.

It should be noted that an underfill material can be applied between the functional grains 611a and 612a and the encapsulation material 651. In the case of using pre-applied underfill material (PUF), such PUF can be applied to the functional grains 611a and 612a, and/or to the top exposed ends of the encapsulation material 651 and/or the interconnect structures 614 and 617 before coupling the functional grains.

Following the attachment performed at block 545, block 550 may include forming an underfill (e.g., capillary underfill, injected underfill, etc.). As shown in the example embodiment 600G of FIG. 6G, underfill material 661 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom side (e.g., orientation as shown in FIG. 6G) and/or at least a portion (if not all) of the lateral side of functional dies 611a and 612a. Underfill material 661 may also, for example, cover most (or all) of the top side of encapsulation material 651. Underfill material 661 may also, for example, surround the corresponding interconnect structures of functional dies 611a and 612a to which the high interconnect structure 614 and the connecting die interconnect structure 617 are attached. In an example embodiment where the ends of the high interconnect structure 614 and/or the connecting grain interconnect structure 617 protrude from the encapsulation material 651, the bottom filler material 661 may also surround such protrusions.

It should be noted that in various implementations of instance method 500, the bottom fill performed at block 550 can be skipped. For example, the bottom fill of the functional grain can be performed at another block (e.g., at block 555, etc.). Or, for example, this type of bottom fill can be omitted entirely.

Typically, block 550 may include underfill for functional grains. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill material.

Example method 500 may include an encapsulation at block 555. Block 555 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. For example, block 555 may share any or all of the characteristics with other encapsulation blocks (or steps) discussed herein (e.g., with block 535, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, etc.).

Various instance forms of block 555 are presented in example 600H shown in Figure 6H. For example, encapsulating material 652' (and/or its formation) may share any or all of the properties with encapsulating material 226' (and/or its formation) of Figure 2E, encapsulating material 426 (and/or its formation) of Figure 4K, encapsulating material 651 (and/or its formation) of Figure 6D, etc.

Encapsulating material 652' covers the top side of encapsulating material 651, covers the lateral side surface of bottom filler 661, covers at least some (if not all) of the lateral side surfaces of functional grains 611a and 612b, covers the top side of functional grains 611a and 612b, etc.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226' in FIG. 2E, etc.), encapsulation material 652' need not initially be formed to cover the top side of functional grains 611a and 612a. For example, block 555 may include encapsulation material 652' formed using film-assisted molding, sealing molding, etc.

Typically, block 555 may include an encapsulation. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 500 may include grinding (or otherwise thinning or planarizing) the encapsulating material at block 560. Block 560 may include performing such grinding (or any thinning or planarizing process) in any of various ways, and non-limiting examples of this are provided herein. For example, block 560 may share any or all of the characteristics with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of example method 100 of FIG. 1, with block 335 of example method 300 of FIG. 3, with block 540, etc.).

Various examples of block 560 are presented in example 600I shown in Figure 6I. The encapsulating material 652 (and/or its formation thereof) of the example milled (or thinned or planarized, etc.) may share any or all of the properties with encapsulating material 226 (and/or its formation thereof) of Figure 2F, encapsulating material 426 (and/or its formation thereof) of Figure 4F, encapsulating material 651 (and/or its formation thereof) of Figure 6E, etc.

Block 560 may include, for example, a polished encapsulating material 652 and/or functional grains 611a and 612a, such that the top surface of the encapsulating material 652 is coplanar with the top surface of the functional grain 611a and/or with the top surface of the functional grain 612a.

Typically, block 560 may include abrasive (or otherwise thinned or planarized) encapsulating material. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such abrasive (or thinning or planarization).

Example method 500 may include a removal carrier at block 565. Block 565 may include any removal carrier in various ways, and non-limiting examples are provided herein. For example, block 565 may share any or all of the characteristics with any carrier removal process discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1, with blocks 345 and/or 360 of example method 300 of FIG. 3, etc.). Various example states of block 565 are shown in example 600J of FIG. 6J.

For example, Example 600J of FIG6J shows the removal of the first carrier 621a (e.g., compared to Example 600I of FIG6I). Block 565 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, or laser release, etc.). As another example, if an adhesive layer was utilized, for example, at block 520 during the formation of the RD structure 646a, then block 565 may include removing the adhesive layer.

It should be noted that in various embodiment schemes, such as those shown and discussed herein with respect to example methods 100 and 300 of Figures 1 and 3, a second carrier (e.g., coupled to encapsulation material 652 and/or coupled to functional grains 611a and 612a) may be utilized. In other embodiment schemes, various tool structures may be used instead of a carrier.

Typically, block 565 may include a removal carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of removing carriers or the characteristics of any particular type of carrier.

Example method 500 may include a completion signal redistribution (RD) structure at block 570. Block 570 may include any of the completion RD structures in various ways, and non-limiting examples of such structures are provided herein. Block 570 may share any or all of its properties with, for example, block 520 (e.g., regarding the RD structure morphology of block 520). Various morphologies of block 570 are presented in example 600K shown in Figure 6K.

As discussed herein, for example, with respect to block 520, the carrier may have been (but not necessarily) received (or manufactured or prepared) only to form a portion of the desired RD structure. In such an instance scenario, block 570 may include completing the formation of the RD structure.

Referring to FIG6K, block 570 may include a second portion 646b of the RD structure formed on a first portion 646a of the RD structure (e.g., the first portion 646a of the RD structure has been received, manufactured, or prepared at block 520). Block 570 may, for example, include a second portion 646b of the RD structure formed in the same manner as the first portion 646a of the RD structure.

It should be noted that in various embodiments, the first portion 646a and the second portion 646b of the RD structure can be formed using different materials and/or different processes. For example, the first portion 646a of the RD structure can be formed using an inorganic dielectric layer, while the second portion 646b of the RD structure can be formed using an organic dielectric layer. As another example, the first portion 646a of the RD structure can be formed with a finer pitch (or finer traces, etc.), while the second portion 646b of the RD structure can be formed with a coarser pitch (or coarser traces, etc.). As yet another example, the first portion 646a of the RD structure can be formed using a back-to-office (BEOL) semiconductor wafer fabrication (fab) process, while the second portion 646b of the RD structure can be formed using a fab post-electronic device packaging process. Furthermore, the first part 646a and the second part 646b of the RD structure can be formed at different geographical locations.

Similar to the first part 646a of the RD structure, the second part 646b of the RD structure can have any number of dielectric layers and/or conductive layers.

As discussed herein, interconnect structures can be formed on RD structure 646b. In such an embodiment, block 565 may include forming under-bump metallization (UBM) on the exposed pad to enhance the formation (or attachment) of such interconnect structures.

Typically, block 570 may include a complete signal redistribution (RD) structure. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which a signal redistribution structure is formed or the characteristics of any particular type of signal redistribution structure.

Example method 500 may include forming an interconnected structure on a recursive structure at block 575. Block 575 may include any of the interconnected structures formed in various ways, and non-limiting examples are provided herein. For example, block 575 may form any or all of the properties with any interconnected structure discussed herein.

Various instance forms of block 575 are presented in example 600L shown in Figure 6L. Instance interconnect structure 652 (e.g., package interconnect structure, etc.) may include the characteristics of any of the various interconnect structures. For example, package interconnect structure 652 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive posts, leads, etc.

Block 575 may include interconnection structure 652 formed in any of various ways. For example, interconnection structure 652 may be glued and/or printed on RD structure 646b (e.g., glued and/or printed to its corresponding pad 651 and/or UBM) and then reflowed. As another example, interconnection structure 652 (e.g., conductive ball, conductive bump, post, lead, etc.) may be pre-formed before attachment and then attached to RD structure 646b (e.g., attached to its corresponding pad 651) via, for example, reflow, electroplating, epoxy bonding, wire bonding, etc.

It should be noted that, as discussed above, the pad 651 of the RD structure 646b may be formed with under-bump metal (UBM) or any metallization to facilitate the formation (e.g., construction, attachment, coupling, deposition, etc.) of the interconnect structure 652. For example, such UBM formation may be performed at block 570 and/or at block 575.

Typically, block 575 can be included in a recursive structure to form an interconnected structure. Therefore, the scope of this disclosure should not be limited by any particular manner in which such an interconnected structure is formed or by any particular characteristic of the interconnected structure.

Example method 500 may include a granular cut at block 580. Block 580 may include performing such a granular cut in any of various ways, of which non-limiting examples are discussed herein. Block 580 may, for example, share any or all of the characteristics with any granular cut discussed herein (e.g., as discussed with respect to example method 100 of FIG1, as discussed with respect to example method 300 of FIG3, etc.).

Various instance forms of block 580 are presented in example 600M shown in Figure 6M. The monolithic cut structure (e.g., corresponding to encapsulation material portion 652a) may share any or all characteristics with, for example, the monolithic cut structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b) and the monolithic cut structure of Figure 4L (e.g., corresponding to two encapsulation material portions 426a and 426b).

Typically, a block 580 can include single-piece cuts. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of single-piece cutting.

Instance method 500 may include continued processing at block 590. Such continued processing may include any of a variety of features, and non-limiting examples are provided herein. For example, block 590 may share any or all features with block 190 of instance method 100 of Figure 1, block 390 of instance method 300 of Figure 3, etc.

For example, block 590 may include returning the execution flow of instance method 500 to any of its blocks. Or, for example, block 590 may include directing the execution flow of instance method 500 to any other method block (or step) discussed herein (e.g., instance method 100 of Figure 1, instance method 300 of Figure 3, instance method 700 of Figure 7, etc.).

For example, as shown in Example 200O of FIG2O, Example 200P of FIG2P and Example 200Q of FIG2Q, block 590 may include forming encapsulation material and/or bottom filler (or skip forming encapsulation material and/or bottom filler).

As discussed herein, functional dies and interconnect dies can be mounted to a substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in Figures 9 and 10.

Figure 7 shows a flowchart of an example method 700 for manufacturing an electronic device according to various forms of this disclosure. Example method 700 may, for example, share any or all characteristics with any other example method discussed herein (e.g., example method 100 of Figure 1, example method 300 of Figure 3, example method 500 of Figure 5, etc.). Figures 8A to 8N show cross-sectional views of illustrative example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to various forms of this disclosure. Figures 8A to 8N may, for example, illustrate example electronic devices at various blocks (or steps) of method 700 of Figure 7. Figures 7 and 8A to 8N will now be discussed together. It should be noted that the order of the instance blocks in method 700 can be changed without departing from the scope of this disclosure. In the example implementation, method 700 of Figure 7 can be considered similar to the method of Figure 5, but with the addition of block 742 for forming the second rearrangement structure.

Example method 700 may begin execution at block 705. Method 700 may begin execution in response to any of a variety of causes or conditions, and non-limiting examples are provided herein. For example, method 700 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 700 may begin execution in response to an operator command. Additionally, for example, method 700 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 700 may include receiving, manufacturing, and/or preparing multiple functional dies at block 710. Block 710 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 710 may share any or all of the characteristics with block 510 of example method 500 shown in FIG. 5 and discussed herein, block 310 of example method 300 shown in FIG. 3 and discussed herein, etc. Various forms of block 710 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A. It should be noted that block 710 may also share any or all of the characteristics, for example, with block 110 of example method 100 shown in FIG. 1 and discussed herein.

As shown in many figures in Figures 8A to 8N, functional dies 811a and 812a (and/or their formation) may share any or all of the characteristics with functional dies 611a and 612a (and/or their formation), functional dies 411 and 412 (and/or their formation), functional dies 211 and 212 (and/or their formation), etc. For example, but not limited to, functional dies 811a and 812a may include the characteristics of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Typically, block 710 may include receiving, manufacturing, and/or preparing multiple functional chips. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such receiving and/or manufacturing, nor by any particular characteristic of such functional chips.

Example method 700 may include receiving, manufacturing, and/or preparing interconnect dies at block 715. Block 715 may include receiving and/or manufacturing multiple interconnect dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 715 may share any or all of the characteristics with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example forms of block 715 are presented in examples 200B-1 and 200B-7 shown in FIG. 2B-1 to 2B-2. It should be noted that block 715 may also share any or all of the characteristics, for example, with block 315 of example method 100 shown in FIG. 3 and discussed herein, and with block 515 of example method 500 shown in FIG. 5, etc.

The interconnecting dies 816b and interconnecting dies interconnecting structures 817 (and/or their formations) shown in many of the figures in Figures 8A to 8N may, for example, share any or all of the characteristics with the interconnecting dies 216b and interconnecting dies interconnecting structures 217 (and/or their formations) in Figures 2B-1 to 2B-2.

It should be noted that the interconnecting grain interconnect structure 817 (and/or its formation) may, for example, share any or all of the characteristics with the first grain interconnect structure 213 (and/or its formation). For example, in an exemplary embodiment, instead of forming a first grain interconnect structure such as the first grain interconnect structure 213 of FIG. 2A on the functional grains 211/212, the same or similar interconnecting grain interconnect structure 817 may be formed on the interconnecting grain 816b.

Typically, block 715 may include receiving, manufacturing, and/or preparing interconnecting dies. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of receiving, manufacturing, and/or preparing such dies or any particular characteristics of such interconnecting dies.

Example method 700 may include at block 720 a carrier having a signal redistribution (RD) structure (or distribution structure) thereon. Block 720 may include performing such receiving, manufacturing and/or preparation in any of various ways, and non-limiting examples thereof are provided herein.

Block 720 may share any or all characteristics with any or all carriers discussed herein that receive, manufacture, and/or prepare (e.g., block 120 for example method 100 of Figure 1, block 320 for example method 300 of Figure 3, block 520 for example method 500 of Figure 5, etc.). Various instance forms of block 720 are provided in example 800A of Figure 8A.

As discussed herein, any or all carriers discussed herein may include, for example, only bulk materials (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal redistribution (RD) structures on (or instead of bulk materials). Block 720 provides examples of receiving, manufacturing, and/or preparing such carriers.

Block 720 may include an RD structure 846a formed on a block carrier 821a in any of various ways, of which non-limiting examples are presented herein. In exemplary embodiments, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to a vertical interconnect structure 814 (formed later), which ultimately electrically connects to a second redistribution structure 896 and/or functional dies 811 and 812 (connected later). Thus, the RD structure 846a may be coreless. However, it should be noted that in various alternative embodiments, the RD structure 846a may be a cored structure.

Figure 8A illustrates an example in which the RD structure 846a includes three dielectric layers 847 and three conductive layers 848. This number of layers is merely an example, and the scope of this disclosure is not limited thereto. In another embodiment, the RD structure 846a may include only a single dielectric layer 847 and a single conductive layer 848, two of each layer, etc. The example redistribution (RD) structure 846a is formed on a bulk carrier material 821a.

The dielectric layer 847 can be formed from any of a variety _of materials (e.g., _Si3N4 , _SiO2 , SiON, PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 847 can be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 847 can, for example, be patterned to expose various surfaces (e.g., exposing the lower traces or pads of the conductive layer 848).

The conductive layer 848 can be formed from any of various materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 848 can be formed using any of various processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 846a may include, for example, conductors exposed at its outer surface (e.g., at the top surface of example 800A). Such exposed conductors may be used, for example, for attaching (or forming) grain interconnect structures (e.g., at block 725, etc.). In such embodiments, the exposed conductors may include pads and may include, for example, under-bump metal (UBM) formed thereon to enhance the attachment (or formation) of the grain interconnect structures. Such under-bump metal may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

The replicating structures and/or their formations are provided in U.S. Patent Application No. 14/823,689, filed August 11, 2015, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” and U.S. Patent No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF,” the contents of each of which are hereby incorporated herein by reference in their entirety.

The redistribution structure 846a may, for example, perform fan-out redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to be formed) vertical interconnect structure 814 to locations outside the coverage areas of functional dies 811 and 812 to which such vertical interconnect structure 814 will be attached. Alternatively, the redistribution structure 846a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to be formed) vertical interconnect structure 814 to locations inside the coverage areas of the (to be connected) connecting die 816b and/or to locations inside the coverage areas of the (to be connected) functional dies 811 and 812. The redistribution structure 846a can also provide, for example, connectivity between various signals between functional dies 811 and 812 (e.g., in addition to the connectivity provided by the connecting die 816b).

In various implementation schemes, block 720 may include a first portion 846a that forms only the entire RD structure 846, wherein a second portion 846b of the entire RD structure 846 may be formed later (e.g., at block 770).

Typically, block 720 may include a carrier that receives, manufactures, and/or prepares to have a signal redistribution (RD) structure thereon. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of manufacturing such carriers and/or signal redistribution structures or any particular characteristics of such carriers and/or signal redistribution structures.

Example method 700 may include forming a vertical interconnect structure on the RD structure (e.g., as provided at block 720) at block 725. Block 725 may include any of the various ways in which a vertical interconnect structure is formed on the RD structure, and non-limiting examples thereof are provided herein. It should be noted that the vertical interconnect structure may also be referred to herein as a high bump, high pillar, high bar, grain interconnect structure, functional grain interconnect structure, etc.

Block 725 may share any or all characteristics (e.g., second grain interconnection formation characteristics, etc.) with any or all functional grain receiving, manufacturing and/or preparation discussed herein (e.g., the formation of block 110 and second grain interconnection structure 214 and/or the formation of first grain interconnection structure 213 in respect of example method 100 of FIG1, the formation of block 347 and second grain interconnection structure 414 in respect of example method 347 of FIG3, block 525 in respect of example method 500 of FIG5, etc.).

Various instances of block 725 are provided in example 800B of Figure 8B. The vertical interconnect structure 814 (and/or its formation) may share any or all characteristics with the second grain interconnect structure 214 (and/or its formation) of Figure 2A and/or with the second grain interconnect structure 414 (and/or its formation) of Figure 4H-2. Additionally, the vertical interconnect structure 814 (and/or its formation) may share any or all characteristics with the interconnect structure 614 (and/or its formation) of Figure 6B.

Typically, block 725 may include a vertical interconnection formed on an RD structure (e.g., as provided at block 720). Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such a vertical interconnection is formed and/or the characteristics of any particular type of vertical interconnection.

Example method 700 may include mounting a connecting die to the RD structure at block 730 (e.g., as provided at block 720). Block 730 may include performing such mounting (or attachment or coupling) in any of various ways, and non-limiting examples of this are provided herein. Block 730 may, for example, share any or all of the characteristics with any die attached herein (e.g., block 530 of example method 500 shown in FIG. 5 and discussed herein, block 325 of example method 300 shown in FIG. 3 and discussed herein, block 125 of example method 100 shown in FIG. 1, etc.). Various example states of block 730 are presented in example 800C shown in FIG. 8C.

Block 730 may, for example, include attaching the back side of the connecting die 816b to the RD structure 846a using a die-attach adhesive (e.g., tape, liquid, paste, etc.). Although Figure 8C shows the connecting die 816b coupled to the dielectric layer of the RD structure 846a, in other embodiments, the back side of the connecting die 816b may be coupled to a conductive layer (e.g., to provide additional structural support for enhanced heat dissipation).

Additionally, as discussed herein, any interconnect die discussed herein may be bilateral. In such example embodiments, the back-side interconnect may be electrically connected to the corresponding interconnect of the RD structure 846a (e.g., pads, solder pads, bumps, etc.).

Typically, block 730 may include mounting a connector die to the RD structure (e.g., as provided at block 720). Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of mounting the connector die.

Example method 700 may include an encapsulation at block 735. Block 735 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples are provided herein. For example, block 735 may share any or all of the characteristics with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, with block 530 of example method 500 of FIG. 5, etc.). Various example states of block 735 are shown in FIG. 8D.

Block 735 may include, for example, performing wafer (or panel) level molding processes. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to the individual module dicing. Referring to the example embodiment 800D shown in Figure 8D, encapsulation material 851' may cover at least part (or all) of the top side of RD structure 846a, vertical interconnect structure 814, die interconnect structure 817, the top side (or active side or front side) of die 816b, and the lateral side surface of die 816b.

Although the encapsulating material 851' (as shown in FIG. 8D) is shown to cover the top ends of the vertical interconnect structure 814 and the connecting grain interconnect structure 817, any or all of these ends may be exposed from the encapsulating material 851' (as shown in FIG. 8E). The block 735 may, for example, include initially forming the encapsulating material 851' with the top ends of the various interconnects exposed or protruding (e.g., using film-assisted molding, grain sealing molding, etc.). Alternatively, the block 735 may include forming the encapsulating material 851' followed by a thinning (or planarizing or grinding) process (e.g., performed at the block 740) to thin the encapsulating material 851' sufficiently to expose the top sides of any or all of the vertical interconnect structure 814 and the connecting grain interconnect structure 817, etc.

Typically, block 735 may include an encapsulation. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or by the characteristics of any particular type of encapsulation material or its configuration.

Example method 700 may include a grinding encapsulating material and/or various interconnections at block 740. Block 740 may include performing such grinding (or any thinning or planarization) in any of various ways, and non-limiting examples of this are provided herein. Various example forms of block 740 are presented in example 800E shown in Figure 8E. Block 740 may, for example, share any or all of the characteristics with other grinding (or thinning or planarization) blocks (or steps) discussed herein.

As discussed herein, in various embodiment examples, the encapsulation material 851' may initially be formed to a thickness greater than the final required thickness, and/or the vertical interconnect structure 814 and the interconnect grain interconnect structure 817 may initially be formed to a thickness greater than the final required thickness. In such embodiment examples, block 740 may be executed to grind (or otherwise thin or planarize) the encapsulation material 851', the vertical interconnect structure 814, and/or the interconnect grain interconnect structure 817. In embodiment 800E shown in FIG8E, the encapsulation material 851, the vertical interconnect structure 814, and/or the interconnect grain interconnect structure 817 have been ground to produce the encapsulation material 851, the vertical interconnect structure 814, and the interconnect grain interconnect structure 817 (as shown in FIG8E). The top surfaces of the milled encapsulating material 851, the top surfaces of the vertical interconnect structure 814, and/or the top surfaces of the grain interconnect structure 817 may, for example, be coplanar.

It should be noted that in various implementation schemes, such as using chemical or mechanical processes to make the encapsulation material 851 thinner than the vertical interconnect structure 814 and/or the connecting grain interconnect structure 817, or using film-assisted and/or sealing molding processes at block 735, the top surface of the vertical interconnect structure 814 and/or the top surface of the connecting grain interconnect structure 817 may protrude from the top surface of the encapsulation material 851.

Typically, block 740 may include polished (or thinned or planarized) encapsulating material and/or various interconnect structures. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such polishing (or thinning or planarization).

Example method 700 may include forming a second signal redistribution (RD) structure (or distribution structure) at block 742. Block 742 may include performing such formation in any of a variety of ways, and non-limiting examples of this are provided herein.

Block 742 may share any or all of the characteristics with any or all signal distribution structures discussed herein (e.g., block 120 for instance method 100 of Figure 1, block 320 for instance method 300 of Figure 3, block 520 for instance method 500 of Figure 5, block 720, etc.). Various instance forms of block 742 are provided in instance 800F of Figure 8F.

As discussed herein, the example structure 800E generated by block 740 may include a top surface, which includes the top surface of the encapsulation material 851, the exposed top surface of the vertical interconnect structure 814 and/or the exposed top lateral surface of the vertical interconnect structure 814 and/or the connected grain interconnect structure 817, etc. Block 742 may, for example, include forming a second signal redistribution structure on any or all of these surfaces.

Block 742 may include a second RD structure formed on top of structure 800E in any of various ways, such as in a non-limiting example. In exemplary embodiments, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections between vertical interconnect structures 814 and/or die interconnect structures 817 laterally and/or vertically to electrical components mounted therein (e.g., semiconductor dies, passive electrical components, shielding components, etc., distributed to, for example, dies 811 and 812). Figure 8F shows an example in which the second RD structure 896 includes three dielectric layers 897 and three conductive layers 898. This number of layers is merely an example, and the scope of this disclosure is not limited thereto. In another embodiment, the second RD structure 896 may consist of only a single dielectric layer 897 and a single conductive layer 898, two of each layer, etc. Therefore, the second RD structure 896 may be coreless. However, it should be noted that in various alternative embodiments, the second RD structure 896 may be a cored structure. In another embodiment, the second redistribution (or distribution) structure 896 may consist of only a single vertical metal structure (e.g., one or more layers), such as a bump-under metallization structure.

The dielectric layer 897 can be formed from any of a variety _of materials (e.g., _Si3N4 , _SiO2 , SiON, PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 897 can be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 897 can, for example, be patterned to expose various surfaces (e.g., exposing the lower traces or pads of the conductive layer 898).

The conductive layer 898 can be formed from any of various materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 898 can be formed using any of various processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The second RD structure 896 may, for example, include conductors exposed at its outer surface (e.g., at the top surface of example 800F). Such exposed conductors may be used, for example, for the attachment (or formation) of electrical components and/or their attachment structures (e.g., at block 745, etc.). Such exposed conductors may, for example, include pad structures, under-bump metallization structures, etc. In such embodiments, the exposed conductors may include pads and may, for example, include under-bump metallization (UBM) formed thereon to enhance the attachment (or formation) of components and/or their interconnection structures. Such under-bump metallization may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

The replicating structures and/or their formations are provided in U.S. Patent Application No. 14/823,689, filed August 11, 2015, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” and U.S. Patent No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF,” the contents of each of which are hereby incorporated herein by reference in their entirety.

The second RD structure 896 may, for example, perform at least some fan-out redistribution of electrical connections or signals, laterally moving at least a portion of the interconnect structure 817 and/or the vertical interconnect structure 814 (attached to the bottom side of the second RD structure 896) to a position outside the coverage area of the interconnect structure 817 (or interconnect 816b) and/or the vertical interconnect structure 814. Alternatively, the second RD structure 896 may perform at least some fan-in redistribution of electrical connections or signals, laterally moving at least a portion of the interconnect structure 817 and/or the vertical interconnect structure 814 to a position inside the coverage area of the interconnect structure 817 (or interconnect 816b) and/or the vertical interconnect structure 814. The second RD structure 896 can also provide, for example, connectivity between functional dies 811 and 812 for various signals (e.g., in addition to the connectivity provided by the connecting die 816b, in addition to the connectivity provided by the RD structure 846a, etc.).

Although instance block 742 is described as forming the second RD structure layer by layer, it should be noted that the second RD structure can be received in a pre-formed format and then attached to block 742 (e.g., by welding, gluing with epoxy resin, etc.).

Typically, block 742 may include a second redistribution (RD) structure. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of manufacturing such carriers and/or signal redistribution structures or any particular characteristics of such carriers and/or signal redistribution structures.

Example method 700 may include attaching (or coupling or mounting) a functional die to a second redistribution (RD) structure (e.g., as formed at block 742) at block 745. Block 745 may include performing such attachment in any of various ways, and non-limiting examples are provided herein. Block 745 may, for example, share any or all of the characteristics with any die attachment process discussed herein. Various example states of block 745 are presented in example 800G shown in Figure 8G.

For example, the grain interconnect structure of the first functional grain 811a (e.g., pads, bumps, etc.) can be mechanically and electrically connected to the corresponding conductors of the second RD structure 896 (e.g., pads, under-bump metal, exposed traces, etc.). For example, the grain interconnect structure of the first functional grain 811a can be electrically connected to the corresponding vertical interconnect structure 814 and/or electrically connected to the corresponding connecting grain interconnect structure 817 via the conductors of the second RD structure 896. Similarly, the grain interconnect structure of the second functional grain 812a (e.g., pads, bumps, etc.) can be mechanically and electrically connected to the corresponding conductors of the second RD structure 896 (e.g., pads, under-bump metal, exposed traces, etc.). For example, the grain interconnection structure of the second functional grain 812a can be electrically connected to the corresponding vertical interconnection structure 814 and/or electrically connected to the corresponding connecting grain interconnection structure 817 through the conductor of the second RD structure 896.

Such interconnection structures of functional grains can be connected in any of a variety of ways. For example, connections can be performed by soldering. In an exemplary embodiment, the interconnection structure of functional grains 811a and 812a may include a solder cap (or other solder structure) that can be reflowed by quality reflow, thermo-press bonding (TCB), etc. Similarly, the under-mask metal of the second RD structure 896 may already have (e.g., at block 742) a solder cap (or other solder structure) that can be reflowed by quality reflow, thermo-press bonding (TCB), etc. In another exemplary embodiment, connections can be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without the use of solder and/or by utilizing one or more intermediate non-solder metal layers. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," and U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof," the entire contents of each of which are hereby incorporated by reference. The functional grain interconnect structure can be attached to the second RD structure 896 using any of the various techniques (e.g., quality reflow, thermo-press bonding (TCB), direct metal-to-metal intermetal bonding, conductive adhesive, etc.).

As shown in Example Embodiment 800G, the first interconnecting die 817 of the connecting die 816b is connected to the corresponding interconnecting structure of the first functional die 811a via the second RD structure 896, and the second interconnecting die 817 of the connecting die 816b is connected to the corresponding interconnecting structure of the second functional die 812a via the second RD structure 896. During connection, the connecting die 816b (e.g., combined with the second RD structure 896) provides electrical connection between the various die interconnecting structures of the first functional die 811a and the second functional die 812a via the RD structure 298 of the connecting die 816b (e.g., as shown in Example 200B-4, etc., of FIG. 2B-1).

In Example 800G shown in Figure 8F, the height of the vertical interconnect structure 814 can be, for example, equal to (or greater than) the combined height of the support layer 290b connecting the interconnect structure 217 and the connecting die 816b, and the adhesive or other components used to attach the connecting die 816b to the RD structure 846a. Therefore, the second RD structure 896 can, for example, include a generally planar lower side, a generally uniform thickness, and a generally planar upper side.

Typically, block 745 may include attaching (or coupling or mounting) a functional die to a second RD structure. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of attachment or the characteristics of any particular type of attachment structure.

Example method 700 may include underfilling of the functional grain at block 750. Block 750 may include performing such underfilling in any of various ways, and non-limiting examples thereof are provided herein. Block 750 may, for example, share any or all of the characteristics with any underfilling discussed herein (e.g., with blocks 155 and/or 175 of example method 100 of FIG. 1, with blocks 355 and/or 375 of example method 300 of FIG. 3, with block 550 of example method 500 of FIG. 5, etc.). Various example states of block 750 are presented in example 800H shown in FIG. 8H.

It should be noted that an underfill material can be applied between the functional dies 811a and 812a and the second RD structure 896. In the case of using a pre-applied underfill material (PUF), such a PUF can be applied to the functional dies 811a and 812a before coupling the functional dies 811a and 812a, and/or to the second RD structure 896 and/or the top exposed conductors of the second RD structure 896 (e.g., pads, under-bump metallization, exposed traces, etc.).

Following the attachment performed at block 745, block 750 may include forming an underfill material (e.g., capillary underfill, injected underfill, etc.). As shown in Example Embodiment 800H of FIG8H, underfill material 861 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom sides (e.g., orientation as shown in FIG8H) of functional grains 811a and 812a, and/or at least a portion (if not all) of the lateral sides of functional grains 811a and 812a. Underfill material 861 may also, for example, cover most (or all) of the top side of the second RD structure 896. The underfill material 861 may also surround, for example, the corresponding interconnection structures (e.g., pads, bumps, etc.) of the functional dies 811a and 812a to which the corresponding interconnection structures (e.g., pads, solder pads, traces, under-bump metallization, etc.) of the second RD structure 896 are attached. In an example embodiment where the ends of the interconnection structures of the second RD structure 896 protrude from the top surface of the second RD structure 896 (e.g., the surface of the top dielectric layer), the underfill material 861 may also surround such protrusions.

It should be noted that in various implementations of instance method 700, the bottom fill performed at block 750 can be skipped. For example, the bottom fill of the functional grain can be performed at another block (e.g., at block 755, etc.). Or, for example, this type of bottom fill can be omitted entirely.

Typically, block 750 may include underfill for functional grains. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill material.

Example method 700 may include an encapsulation at block 755. Block 755 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. For example, block 755 may share any or all of the characteristics with other encapsulation blocks (or steps) discussed herein (e.g., with block 735, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, with blocks 535 and 555 of example method 500 of FIG. 5, etc.).

Various instance forms of block 755 are presented in example 800I shown in Figure 8I. For example, encapsulating material 852' (and/or its formation) may share any or all of the properties with encapsulating material 226' (and/or its formation) of Figure 2E, encapsulating material 426 (and/or its formation) of Figure 4K, encapsulating materials 651 and 652' (and/or their formations) of Figures 6D and 6H, encapsulating material 851 of Figure 8E, etc.

Encapsulating material 852' covers the top side of the second RD structure 896, covers the lateral side surfaces of the underfill 861, covers the top surface of the underfill 861 (e.g., between grains 811a and 812a), covers at least some (if not all) of the lateral side surfaces of the functional grains 811a and 812a, covers the top side of the functional grains 811a and 812a, etc. In other embodiments, encapsulating material 852' may replace the underfill 861, thus providing underfill between the functional grains 811a and/or 812a and the second RD structure 896.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226' in FIG. 2E, etc.), the encapsulation material 852' need not initially be formed to cover the top side of the functional grains 811a and 812a. For example, the block 755 may include encapsulation material 852' formed using film-assisted molding, sealing molding, etc.

Typically, block 755 may include an encapsulation. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 700 may include grinding (or otherwise thinning or planarizing) the encapsulating material at block 760. Block 760 may include performing such grinding (or any thinning or planarizing process) in any of various ways, and non-limiting examples of this are provided herein. For example, block 760 may share any or all of the characteristics with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of example method 100 of FIG. 1, with block 335 of example method 300 of FIG. 3, with blocks 540 and 555 of example method 500 of FIG. 5, with block 735, etc.).

Various examples of block 760 are presented in example 800J shown in Figure 8J. The encapsulating material 852 (and/or its formation) of the example milled (or thinned or planarized, etc.) may share any or all of the properties with encapsulating material 226 (and/or its formation) of Figure 2F, encapsulating material 426 (and/or its formation) of Figure 4F, encapsulating materials 651 and 652 (and/or their formations) of Figures 6E and 6I, encapsulating material 851, etc.

Block 760 may include, for example, a polished encapsulating material 852 and/or functional grains 811a and 812a, such that the top surface of the encapsulating material 852 is coplanar with the top surface of the functional grain 811a and/or with the top surface of the functional grain 812a.

Typically, block 760 may include abrasive (or otherwise thinned or planarized) encapsulating material. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such abrasive (or thinning or planarization).

Example method 700 may include a removal carrier at block 765. Block 765 may include any removal carrier in various ways, and non-limiting examples of this are provided herein. For example, block 765 may share any or all of the features with any carrier removal process discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1, with blocks 345 and/or 360 of example method 300 of FIG. 3, with block 565 of example method 500 of FIG. 5, etc.). Various example states of block 765 are shown in example 800K of FIG. 8K.

For example, Example 800K of Figure 8K shows the removal of the first carrier 821a (e.g., compared to Example 800J of Figure 8J). Block 765 may include performing this type of carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, or laser release, etc.). Again, for example, if an adhesive layer was utilized, for example, at block 720 during the formation of the RD structure 846a, then block 765 may include removing the adhesive layer.

It should be noted that in various embodiment schemes, such as those shown and discussed herein with respect to example methods 100 and 300 of Figures 1 and 3, a second carrier (e.g., coupled to encapsulation material 852 and/or coupled to functional grains 811a and 812a) may be utilized. In other embodiment schemes, various tool structures may be used instead of a carrier.

Typically, block 765 may include a removal carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of removing carriers or the characteristics of any particular type of carrier.

Example method 700 may include a complete signal redistribution (RD) structure at block 770 (e.g., if the RD structure 846a is not fully formed at block 820). Block 770 may include any of the complete RD structures in various ways, and non-limiting examples of such structures are provided herein. Block 770 may share any or all of the properties with block 720, for example (e.g., with respect to the RD structure formation state of block 720). Various states of block 770 are presented in example 800L shown in Figure 8L.

As discussed herein, for example, with respect to block 720, the carrier may have been (but not necessarily) received (or manufactured or prepared) only to form a portion of the desired RD structure. In such an instance scenario, block 770 may include completing the formation of the RD structure.

Referring to Figure 8L, block 770 may include a second portion 846b of the RD structure formed on a first portion 846a of the RD structure (e.g., the first portion 846a of the RD structure has been received, manufactured, or prepared at block 720). Block 770 may, for example, include a second portion 846b of the RD structure formed in the same manner as the first portion 846a of the RD structure.

It should be noted that in various embodiments, the first portion 846a and the second portion 846b of the RD structure can be formed using different materials and/or different processes. For example, the first portion 846a of the RD structure can be formed using an inorganic dielectric layer, while the second portion 846b of the RD structure can be formed using an organic dielectric layer. As another example, the first portion 846a of the RD structure can be formed with a finer pitch (or finer traces, etc.), while the second portion 846b of the RD structure can be formed with a coarser pitch (or coarser traces, etc.). As yet another example, the first portion 846a of the RD structure can be formed using a back-to-office (BEOL) semiconductor wafer fabrication (fab) process, while the second portion 846b of the RD structure can be formed using a fab post-electronic device packaging process. In addition, the first part 846a and the second part 846b of the RD structure can be formed at different geographical locations.

Similar to the first part 846a of the RD structure, the second part 846b of the RD structure can have any number of dielectric layers and/or conductive layers.

As discussed herein, interconnect structures can be formed on RD structure 846b. In such an embodiment, block 765 may include forming under-bump metallization (UBM) on the exposed pad to enhance the formation (or attachment) of such interconnect structures.

Typically, block 770 may include a complete signal redistribution (RD) structure. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner in which the signal redistribution structure is formed or the characteristics of any particular type of signal distribution structure.

Example method 700 may include forming an interconnected structure on a recursive structure at block 775. Block 775 may include any of the interconnected structures formed in various ways, and non-limiting examples are provided herein. For example, block 775 may form any or all of the properties with any interconnected structure discussed herein.

Various instance forms of block 775 are presented in example 800M shown in Figure 8M. Instance interconnect structure 852 (e.g., packaged interconnect structure, etc.) may include the characteristics of any of the various interconnect structures. For example, packaged interconnect structure 852 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive posts, leads, etc.

Block 775 may include interconnect structures 852 formed in any of various ways. For example, interconnect structures 852 may be glued and/or printed onto RD structure 846b (e.g., glued and/or printed to its corresponding pads 851 and/or UBM) and then reflowed. As another example, interconnect structures 852 (e.g., conductive balls, conductive bumps, pillars, leads, etc.) may be pre-formed before attachment and then attached to RD structure 846b (e.g., to its corresponding pads 851) via, for example, reflow, electroplating, epoxy bonding, wire bonding, etc.

It should be noted that, as discussed above, the pad 851 of the RD structure 846b may be formed with under-bump metal (UBM) or any metallization to facilitate the formation (e.g., construction, attachment, coupling, deposition, etc.) of the interconnect structure 852. For example, such UBM formation may be performed at block 770 and/or at block 775.

Typically, block 775 can be included in a recursive structure to form an interconnected structure. Therefore, the scope of this disclosure should not be limited by any particular manner in which such an interconnected structure is formed or by any particular characteristic of the interconnected structure.

Example method 700 may include a single-piece cut at block 780. Block 780 may include performing such a single-piece cut in any of various ways, of which non-limiting examples are discussed herein. Block 780 may, for example, share any or all of the characteristics of any single-piece cut discussed herein (e.g., as discussed in block 165 of example method 100 of FIG. 1, as discussed in block 365 of example method 300 of FIG. 3, as discussed in block 580 of example method 500 of FIG. 5, etc.).

Various instances of block 780 are presented in example 800N shown in Figure 8N. The monolithic cut structure (e.g., corresponding to encapsulation material portion 852a) may share any or all of the characteristics with, for example, the monolithic cut structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b), the monolithic cut structure of Figure 4L (e.g., corresponding to two encapsulation material portions 426a and 426b), and the monolithic cut structure 600M of Figure 6M.

Typically, a block 780 can include single-piece cuts. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of single-piece cutting.

Instance method 700 may include execution of continuation processing at block 790. Such continuation processing may include any of a variety of features, and non-limiting examples are provided herein. For example, block 790 may share any or all features with block 190 of instance method 100 of Figure 1, block 390 of instance method 300 of Figure 3, block 590 of instance method 500 of Figure 5, etc.

For example, block 790 may include returning the execution flow of instance method 700 to any of its blocks. As another example, block 790 may include directing the execution flow of instance method 700 to any other method block (or step) discussed herein (e.g., with respect to instance method 100 of Figure 1, instance method 300 of Figure 3, instance method 500 of Figure 5, etc.).

For example, as shown in Example 200O of Figure 2O, Example 200P of Figure 2P and Example 200Q of Figure 2Q, block 790 may include forming encapsulation material and/or bottom filler (or skip forming encapsulation material and/or bottom filler).

As discussed herein, functional dies and interconnect dies can be mounted to a substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in Figures 9 and 10.

Figure 9 shows a top view of an example electronic device 900 according to various forms of this disclosure. The example electronic device 900 may, for example, share any or all characteristics with any or all electronic devices discussed herein. For example, functional chips 911 and 912 may share any or all characteristics with any or all functional chips (211, 212, 201 to 204, 411, 412, 401 to 404, 611a, 612a, 811a, 812a, etc.) discussed herein. As another example, interconnect chip 916 may share any or all characteristics with any or all interconnect chips (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, etc.) discussed herein. Additionally, for example, substrate 930 may share any or all characteristics with any or all substrates and/or RD structures (288, 488, 646, 846, 896, etc.) discussed herein.

Figure 10 shows a top view of various examples of electronic devices according to this disclosure. Example electronic device 1000 may, for example, share any or all characteristics with any or all electronic devices discussed herein. For example, functional chips (functional chips 1 to 10) may share any or all characteristics with any or all functional chips discussed herein (211, 212, 201 to 204, 411, 412, 401 to 404, 611a, 612a, 811a, 812a, 911, 912, etc.). As another example, interconnect chips (connector chips 1 to 10) may share any or all characteristics with any or all interconnect chips discussed herein (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, 916, etc.). Additionally, for example, substrate 1030 may share any or all characteristics with any or all substrates and/or RD structures (288, 488, 646, 846, 896, 930, etc.) discussed herein.

Although the illustrations discussed herein typically include a connecting die between two functional dies, the scope of this disclosure is not limited thereto. For example, as shown in Figure 10, a connecting die 9 is connected to three functional dies (e.g., functional die 2, functional die 9, and functional die 10), for example, by electrically connecting each of these functional dies to each other. Thus, a single connecting die can couple multiple functional dies (e.g., two functional dies, three functional dies, four functional dies, etc.).

Furthermore, although the illustrations discussed herein typically include functional dies connected to only one interconnect die, the scope of this disclosure is not limited thereto. For example, a single functional die may be connected to two or more interconnect dies. For instance, as shown in Figure 10, functional die 1 is connected to many other functional dies via many corresponding interconnect dies.

Figure 11 shows a cross-sectional view of an example of an electronic device 1100, a connecting die 11-16, and an electronic assembly 1100A according to various embodiments of the present disclosure. In the example shown in Figure 11, the electronic device 1100 may include an external substrate 11-46, device interconnects 11-14, connecting dies 11-16, adhesive 11-23, internal components 11-16z, adhesive 11-23z, internal encapsulation 11-51, internal substrate 11-96, electronic components 11-11, 11-12, external encapsulation 11-52, underfill 11-61 (optional), and external interconnect 11-92. Example electronic device 1100 and electronic assembly 1100A or similarly named portions thereof may share any or all features with any other device or assembly or similarly named portions disclosed herein.

The outer substrate 11-46 may include a dielectric structure 11-47 and a conductive structure 11-48. The inner substrate 11-96 may include a dielectric structure 11-97 and a conductive structure 11-98. The electronic component 11-11 may include component interconnects 11-11a having a relatively thin width or finer spacing, and component interconnects 11-11b having a relatively thick width or coarser spacing. The electronic component 11-12 may include component interconnects 11-12a having a relatively thin width or finer spacing, and component interconnects 11-12b having a relatively thick width or coarser spacing.

In the example shown in Figure 11, interconnecting dies 11-16 may include interconnecting die interconnects 11-17, interconnecting die substrates 11-18, and interconnecting die encapsulations 11-19. Interconnecting die substrates 11-18 may include: a dielectric structure comprising one or more dielectric layers; and a conductive structure comprising conductive features defined by one or more conductive layers. Internal components 11-16z may include component bodies 11-15z, component interconnects 11-17z, component substrates 11-18z, or component encapsulations 11-19z.

In the example shown in Figure 11, the electronic assembly 1100A may include an electronic device 1100, an assembly substrate 11-56, a peripheral structure 11-57, and a component 11-58.

The outer substrate 11-46, inner encapsulation 11-51, inner substrate 11-96, and outer encapsulation 11-52 may be referred to as a semiconductor package, and the package can provide protection for electronic components 11-11 and 11-12, interconnect die 11-16, or internal component 11-16z from external components or environmental exposure. The semiconductor package can provide electrical coupling between external electronic components and external interconnects.

Figures 12A to 12E show cross-sectional views of example methods for manufacturing example interconnecting grains 11-16 according to various forms of this disclosure.

Figure 12A shows a cross-sectional view of the interconnect dies 11-16 during an early manufacturing stage. In the example shown in Figure 12A, a support carrier 11-16A may be provided, and an interconnect die substrate 11-18 may be formed on the support carrier 11-16A. In some embodiments, the interconnect die substrate 11-18 may have a structure or form similar to the RD structure 298 described herein in Figures 2B-1 or 2B-2. In some embodiments, the support carrier 11-16A may include or be referred to as a silicon, glass, ceramic, metal, or plastic wafer or panel. In some embodiments, the support carrier 11-16A may include or be referred to as a low-level printed circuit board or a low-level lead frame. In some examples, the support carriers 11-16A may be wafer-shaped (e.g., circular, etc.) or plate-shaped (e.g., square, rectangular, etc.). The support carriers 11-16A may support the interconnecting die substrates 11-18, the interconnecting die interconnects 11-17, and the interconnecting die capsules 11-19 during the following later stages.

In some instances, interconnect die substrates 11-18 may be mounted on support carriers 11-16A. Although the illustrations herein show a single interconnect die substrate 11-18 mounted on support carriers 11-16A, multiple interconnect die substrates 11-18 may be mounted on support carriers 11-16A in an N×M matrix, where at least one of N or M is greater than 1.

In some embodiments, the interconnecting die substrates 11-18 may be referred to as redistribution (“RD”) layers, substrates, or structures. The RD substrate may include one or more conductive redistribution layers and one or more dielectric layers that can be formed layer by layer over a support carrier, the support carrier being completely or at least partially removed after the RD substrate is provided. The RD substrate may be fabricated layer by layer on a circular wafer as a wafer-level substrate using a wafer-level process, or layer by layer on a rectangular or square panel carrier as a panel-level substrate using a panel-level process. The RD substrate may be formed in an additive accumulation process, and may include one or more dielectric layers stacked alternately with one or more conductive layers, the conductive layers defining corresponding conductive redistribution patterns or traces. Conductive patterns can be formed using plating processes such as electroplating or electroless plating. The conductive patterns may include conductive materials, such as copper or other platingable metals. Photopatterning processes, such as photolithography, and photoresist materials used to form the photolithography mask can be used to define the location of the conductive patterns. The dielectric layer of the RD substrate can be patterned using photopatterning processes and may include a photolithography mask through which light is exposed to desired features of the photopattern, such as vias in the dielectric layer. Therefore, the dielectric layer can be made of photo-definable organic dielectric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials can be spin-coated in liquid form or otherwise coated, rather than attached as a pre-formed film. To allow for the proper formation of desired light-defined features, such light-defined dielectric materials may omit structural reinforcing agents or may be filler-free, and are free from strands, fabrics, or other particles that could interfere with light from photopatterning processes. In some instances, this filler-free characteristic of filler-free dielectric materials allows for a reduced thickness of the resulting dielectric layer. Although the light-defined dielectric materials described above can be organic materials, in other instances, the dielectric material of the RD substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride ( _Si₃N₄ ), silicon oxide ( _SiO₂ ), or SiON. One or more inorganic dielectric layers _may be formed not by using light-defined organic dielectric materials, but by growing inorganic dielectric layers using oxidation or nitriding processes. These inorganic dielectric layers can be filler-free, without strands, fabrics, or other different inorganic particles. In some instances, the RD substrate can omit the permanent core structure or carrier, for example, by using dielectric materials including bismaleimide triazine (BT) or FR4, and these types of RD substrates can be referred to as coreless substrates.

In some embodiments, the dielectric or conductive structures of the interconnecting die substrates 11-18 may have line/space/width in the range of about 0.1 micrometers to about 30 micrometers. In some embodiments, the total thickness of the interconnecting die substrates 11-18 may be in the range of about 3 micrometers to about 50 micrometers.

Figure 12B shows a cross-sectional view of the interconnect dies 11-16 in a later stage of manufacturing. In the example shown in Figure 12B, interconnect die interconnects 11-17 may be disposed on interconnect die substrates 11-18. In some embodiments, interconnect die interconnects 11-17 may be formed on the conductive structure of interconnect die substrates 11-18. Interconnect die interconnects 11-17 may include or be referred to as pillars, rods, balls, leads, or bumps. In some embodiments, interconnect die interconnects 11-17 may include metals such as copper, aluminum, gold, silver, nickel, palladium, or solder. Interconnect die interconnects 11-17 may be formed in any of a variety of ways. In some embodiments, the interconnects 11-17 can be disposed on the conductive structure of the interconnect substrates 11-18 by plating. In some embodiments, the interconnects 11-17 can be disposed on the interconnect substrates 11-18 by printing, reflow soldering, or wire bonding. In some embodiments, the interconnects 11-17 can extend from the conductive structure of the interconnect substrates 11-18. In some embodiments, the interconnects 11-17 can have a line/space spacing or pitch in the range of about 20 micrometers to about 300 micrometers. In some embodiments, the height of the interconnects 11-17 can be in the range of about 10 micrometers to about 300 micrometers.

In some embodiments, the connecting die interconnect 11-17 can act as a bridge to electrically connect the component interconnect 11-11a of electronic component 11-11 and the component interconnect 11-12a of electronic component 11-12, and thus the two electronic components 11-11 and 11-12 can be electrically connected to each other in the horizontal direction via the connecting die substrate 11-18.

In some embodiments, the connecting die substrate 11-18 is electrically connected to the component interconnects 11-11a of electronic component 11-11 and the component interconnects 11-12a of electronic component 11-12. Therefore, the two electronic components 11-11 and 11-12 are electrically connected to each other in the horizontal direction via the connecting die substrate 11-18. Furthermore, the connecting die interconnect 11-17 is electrically connected to the external substrate 11-46, thus connecting the two electronic components 11-11 and 11-12 to the external substrate 11-46. In this embodiment, power from the external substrate 11-46 can be supplied to electronic components 11-11 and 11-12 via the connecting die interconnect 11-17.

Figure 12C shows a cross-sectional view of the interconnect dies 11-16 in a later stage of manufacturing. In the example shown in Figure 12C, interconnect die capsules 11-19 may be disposed on the interconnect die substrates 11-18 and the interconnect die interconnects 11-17. The interconnect die capsules 11-19 may cover the top side of the interconnect die substrates 11-18 or the lateral side of the interconnects 11-17. In some embodiments, the interconnect die capsules 11-19 may include epoxy resin or phenolic resin, or silica filler. In some embodiments, the interconnect die capsules 11-19 may include, or be referred to as, molding compounds, resins, sealants, filler-reinforcing polymers, or organic hosts. In some embodiments, the connecting die capsules 11-19 may cover not only the lateral sides but also the top of the connecting die interconnects 11-17. In some embodiments, the top sides of the connecting die capsules 11-19 and the top sides of the connecting die interconnects 11-17 may be coplanar. In some embodiments, the connecting die capsules 11-19 may be formed by compression molding, transfer molding, liquid phase capsule molding, vacuum lamination, paste printing, or film-assisted molding. In some embodiments, a compression molding process can be performed, in which a flowable resin is pre-supplyed to a mold, a connector die substrate 11-18 having connector die interconnects 11-17 is placed into the mold, and the corresponding flowable resin is then cured. A transfer molding process can be performed, in which the flowable resin is supplied from a gate (supply orifice) of the mold to the outer periphery of the connector die substrate 11-18 including the connector die interconnects 11-17. In some embodiments, the thickness (height) of the connector die capsule 11-19 can be similar to that of the connector die interconnects 11-17. Connector die encapsulation 11-19 can provide structural integrity or protection for connector dies 11-16 (e.g., connector die interconnects 11-17) to protect them from the effects of external components or environmental exposure during the manufacture of connector dies 11-16.

Figure 12D shows a cross-sectional view of the interconnecting dies 11-16 in a later stage of manufacturing. In the example shown in Figure 12D, a thinning process can be performed. A grinding wheel or abrasive pad can be used to reduce the top side of the interconnecting die interconnects 11-17 and the top side of the interconnecting die capsules 11-19. The top side of the interconnecting die interconnects 11-17 and the top side of the interconnecting die capsules 11-19 can be etched before or after the thinning process. After the thinning process, the top side of the connecting grain interconnect 11-17 and the top side of the connecting grain capsule 11-19 may be coplanar, or the top side of the connecting grain interconnect 11-17 may be exposed through the top side of the connecting grain capsule 11-19.

Figure 12E shows a cross-sectional view of the interconnect dies 11-16 in a later stage of manufacturing. In the example shown in Figure 12E, the support carrier 11-16A can be removed from the interconnect substrate 11-18. In some embodiments, the wafer support system may first be attached to the interconnect interconnects 11-17 and the interconnect capsule 11-19. In some embodiments, when the temporary adhesive is positioned between the interconnect substrate 11-18 and the support carrier 11-16A, heat or light (e.g., a laser beam) can be supplied to the temporary adhesive, and thus weaken or remove the adhesiveness of the temporary adhesive, thereby removing the support carrier 11-16A from the interconnect substrate 11-18. In some embodiments, mechanical force can be used to forcibly separate the support carriers 11-16A from the interconnect die substrates 11-18. In some embodiments, the support carriers 11-16A can be removed by mechanical polishing and chemical etching. When the interconnect die substrates 11-18 are manufactured in a matrix configuration as described above, a single-die cutting or sawing process can be performed to separate them into individual interconnect dies 11-16. The lateral sides of the interconnect die encapsulations 11-19 and the lateral sides of the interconnect die substrates 11-18 can be made coplanar by a single-die cutting process.

When completed, interconnect dies 11-16 may include interconnect die substrates 11-18 with fine or narrow pitch and interconnect interconnects 11-17 with fine or narrow pitch. In some embodiments, interconnect interconnects 11-17 may be connected to an inner substrate 11-96, wherein interconnect interconnects 11-17 facing the inner substrate 11-96 (facing upwards) and such upward-facing arrangement may be horizontally coupled to electronic components 11-11 and 11-12 via interconnect dies 11-16. In some embodiments, interconnect die substrates 11-18 may be connected to the inner substrate 11-96, and interconnect interconnects 11-17 may be connected to an outer substrate 11-46, wherein interconnect interconnects 11-17 facing the outer substrate 11-46 (facing downwards). Connector dies 11-16 with similar structures can be used as top-facing type connector dies in some instances and as bottom-facing type connector dies in others, as will be described in further detail below.

Figures 13A to 13K illustrate exemplary methods of manufacturing exemplary electronic devices 1100 and exemplary electronic assemblies 1100A according to various embodiments of the present disclosure.

Figure 13A shows a cross-sectional view of the electronic assembly 1100A in an early stage of manufacturing. In the example shown in Figure 13A, an outer substrate 11-46 may be disposed or formed on a support carrier 11-46A. In some embodiments, the outer substrate 11-46 may include or be referred to as a redistribution (RD) layer, substrate, or structure. The outer substrate 11-46 may include dielectric structures 11-47 and conductive structures 11-48. The dielectric structure 11-47 may include or be referred to as one or more dielectric layers. The conductive structure 11-48 may include or be referred to as one or more conductive layers, traces, vias, pads, or UBMs. In some embodiments, dielectric structures 11-47 may include PI, BCB, PBO, _Si3N4 , _SiO2 , or SiON, and may be provided by PVD, _CVD , printing, spin coating, spraying, sintering, or thermal oxidation. In some embodiments, conductive structures 11-48 may include copper, silver, gold, aluminum, nickel, or palladium, or may be provided by electroplating, electroless plating, CVD, or PVD. In some embodiments, a portion of conductive structures 11-48 may be exposed through dielectric structures 11-47. The exposed portion of conductive structures 11-48 may include a pad, and the pad may include UBM. UBM may include Ti, Cr, Al, TiW, TiN, Cu, NiV, or other conductive materials. In some instances, the features, materials, structure, or process of Figure 13A may be similar to those of Example 600A shown in Figure 6A, Example 800A shown in Figure 8A, or the examples shown in Figure 12A.

Figure 13B shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13B, device interconnects 11-14 may be formed or disposed on an outer substrate 11-46. Device interconnects 11-14 may be disposed on a conductive structure 11-48. Device interconnects 11-14 may include or be referred to as pillars, rods, balls, leads, or bumps. In some examples, the features, materials, structures, or processes of Figure 13B may be similar to those of Example 600B shown in Figure 6B, Example 800B shown in Figure 8B, or the example shown in Figure 12B.

Figure 13C shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13C, the interconnect die 11-16 may be disposed on the outer substrate 11-46. In some embodiments, adhesive 11-23 may be supplied between the dielectric structure 11-47 of the interconnect die substrate 11-18 and the outer substrate 11-46. In some embodiments, adhesive 11-23 may include an electrical insulating layer. In some embodiments, the interconnect die substrate 11-18 and the outer substrate 11-46 may be electrically decoupled from each other by adhesive 11-23. In some embodiments, adhesive 11-23 may include or be referred to as adhesive tape, adhesive film, or adhesive paste. In some embodiments, the adhesives 11-23 may further comprise thermally conductive fillers based on nitrides, oxides, or carbides, such as AlN, BN, _Al2O3 , or SiC. In some embodiments, the interconnecting grains 11-16 are attached in an upward-facing configuration, wherein the interconnecting grains 11-17 face upward or away from the external substrate 11-46. In some embodiments, the features, materials, structures, or processes of FIG. 13C may be similar to those of Example 600C shown in FIG. 6C or Example 800C shown in FIG. 8C.

In some embodiments, internal components 11-16z (FIG. 11) may be additionally disposed on external substrate 11-46. In some embodiments, internal component bodies 11-15z may be attached to dielectric structures 11-47 or conductive structures 11-48 of external substrate 11-46 using adhesive 11-23z. In some embodiments, internal components 11-16z may include active devices such as processors, microcontrollers, memory or transistor devices, passive devices such as resistors, capacitors, inductors or integrated passive devices (IPDs), or another connection die similar to connection die 11-16.

Figure 13D shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13D, an inner encapsulation 11-51 may be disposed on an outer substrate 11-46. The inner encapsulation 11-51 may cover the outer substrate 11-46, and may also cover the device interconnects 11-14 and the interconnect die 11-16. In some embodiments, the thickness of the inner encapsulation 11-51 may be greater than the thickness of the device interconnects 11-14 or the interconnect die 11-16. In this case, a thinning process for removing the top portion of the inner encapsulation 11-51 may be performed separately. In some embodiments, the top sides of device interconnects 11-14 and connecting dies 11-16 may be exposed through the internal encapsulation 11-51 by a thinning process. In some embodiments, an etching process for removing the top sides of the internal encapsulation 11-51 may be performed after or before the thinning process. In some embodiments, the top sides of connecting die interconnects 11-17 and connecting die encapsulations 11-19 may be exposed through the top sides of the internal encapsulation 11-51. In some embodiments, the top sides of device interconnects 11-14 and connecting dies 11-16 may be coplanar with the top sides of the internal encapsulation 11-51. In some embodiments, the top sides of the connecting grain interconnects 11-17 and the connecting grain encapsulations 11-19 may be coplanar with the top sides of the inner encapsulations 11-51. In some embodiments, the features, materials, structures, or processes of FIG13D may be similar to those of embodiments 600D and 600E shown in FIG6D and 6E, embodiments 800D and 800E shown in FIG8D and 8E, or the features, materials, structures, or processes of the embodiments shown in FIG12D.

Figure 13E shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13E, an internal substrate 11-96 may be formed or disposed on the device interconnects 11-14, the internal encapsulation 11-51, and the interconnect die 11-16. In some embodiments, the internal substrate 11-96 may include or be referred to as a redistribution (RD) layer, RD substrate, or RD structure. The internal substrate 11-96 may include dielectric structures 11-97 and conductive structures 11-98. The dielectric structure 11-97 may include or be referred to as one or more dielectric layers. The conductive structure 11-98 may include or be referred to as one or more conductive layers, traces, vias, pads, or UBMs. In some embodiments, the dielectric structure 11-97 of the internal substrate 11-96 may be formed on the internal encapsulation 11-51 or the die-connecting encapsulation 11-19. In some embodiments, the conductive structure 11-98 of the internal substrate 11-96 may be formed as a contact device interconnect 11-14 or a die-connecting interconnect 11-17. In some embodiments, not only the device interconnect 11-14 but also the die-connecting 11-16 may be electrically connected to the internal substrate 11-96. In some embodiments, a portion of the conductive structure 11-98 may be exposed through the dielectric structure 11-97, and the exposed portion of the conductive structure 11-98 may include a pad, and the pad may include a UBM. In some embodiments, the features, materials, structures, or processes of FIG13E may be similar to those of Example 800F shown in FIG8F. In some embodiments, the dielectric structures 11-97 of the inner substrate 11-96 may contact the component encapsulation 11-19z (see FIG11). In some embodiments, the conductive structures 11-98 of the inner substrate 11-96 may electrically contact the component interconnects 11-17z (see FIG11).

Figure 13F shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13F, electronic components 11-11 and 11-12 may be disposed on an internal substrate 11-96. In some embodiments, electronic components 11-11 or 11-12 may be similar to components 811a or 812a described herein. Electronic components 11-11 may include a set of component interconnects 11-11a having a relatively thin width or fine spacing (e.g., in the range of about 20 micrometers to about 300 micrometers) and a set of component interconnects 11-11b having a relatively thick width or coarse spacing (e.g., in the range of about 30 micrometers to about 500 micrometers), and these sets of component interconnects 11-11a and 11-11b may be electrically connected to the conductive structure 11-98 of the internal substrate 11-96. Electronic components 11-12 may include a set of component interconnects 11-12a having a relatively thin width or fine spacing (e.g., in the range of about 20 micrometers to about 300 micrometers) and a set of component interconnects 11-12b having a relatively thick width or coarse spacing (e.g., in the range of about 30 micrometers to about 500 micrometers), and these sets of component interconnects 11-12a and 11-12b may be electrically connected to the conductive structure 11-98 of the internal substrate 11-96.

In some embodiments, component interconnects 11-11a, 11-11b, 11-12a, and 11-12b may include or be referred to as bumps, pillars, solder caps, pads, or leads. In some embodiments, electronic components 11-11 and 11-12 may include or be referred to as dies, chips, or packages. In some embodiments, electronic component 11-11 may include a processor, and electronic component 11-12 may include a memory chip. In some embodiments, both electronic components 11-11 and 11-12 may include a processor or a memory chip. In some embodiments, component interconnects 11-11a, 11-11b, 11-12a, or 11-12b can be directly connected to the conductive structure 11-98 of the inner substrate 11-96, or can be connected using a conductive adhesive such as solder. In some embodiments, underfill 11-61 can be additionally disposed between the electronic components 11-11, 11-12 and the inner substrate 11-96. Underfill 11-61 can be disposed between the bottom side of the electronic components 11-11 and 11-12 and the top side of the inner substrate 11-96, and can cover the lateral side of the electronic components 11-11 or 11-12. The bottom filler 11-61 may surround the lateral side of the component interconnects 11-11a, 11-11b, 11-12a, or 11-12b. In some examples, the features, materials, structures, or processes of FIG13F may be similar to those of examples 600F and 600G shown in FIG6F and 6G, and examples 800G and 800H shown in FIG8G and 8H.

Figure 13G shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13G, an outer encapsulation 11-52 may be disposed on the inner substrate 11-96 and electronic components 11-11 and 11-12. In some embodiments, the outer encapsulation 11-52 may cover the top side of the inner substrate 11-96, the top and (or lateral) sides of the electronic components 11-11 and 11-12, and the side of the bottom filler 11-61. In some embodiments, the top side of the outer encapsulation 11-52 or the top side of the electronic components 11-11 and 11-12 may be ground (or otherwise planarized). In some embodiments, the top side of the outer envelope 11-52 may be coplanar with the top sides of the electronic components 11-11 and 11-12. In some embodiments, the top sides of the electronic components 11-11 and 11-12 may be exposed through the top side of the outer envelope 11-52. In some embodiments, the features, materials, structures, or processes of FIG13G may be similar to those of Examples 600H and 600I shown in FIG6H and 6I or Examples 800I and 800J shown in FIG8I and 8J.

Figure 13H shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13H, a temporary adhesive can be used to place the support carrier 11-52A on the electronic components 11-11 and 11-12 and the outer encapsulation 11-52, and the support carrier 11-16A can be removed from the outer substrate 11-46. In some embodiments, the support carrier 11-16A can be removed from the outer substrate 11-46 by grinding or etching. After the support carrier 11-16A is removed, the bottom sides of the dielectric structure 11-47 and the conductive structure 11-48 of the outer substrate 11-46 can be exposed. In some examples, the process of removing support carriers 11-16A may be similar to that of example 800K shown in Figure 8K. In some examples, the features, materials, structures, or processes of Figure 13H may be similar to those of example 800K shown in Figure 8K.

Figure 13I shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13I, external interconnects 11-92 may be disposed on an external substrate 11-46. In some embodiments, external interconnects 11-92 may be configured to couple to a conductive structure 11-48 of the external substrate 11-46. In some embodiments, external interconnects 11-92 may include or be referred to as conductive balls, conductive bumps, conductive pillars, or solder caps. In some embodiments, the features, materials, structures, or processes of Figure 13I may be similar to those of Example 600L shown in Figure 6L or Example 800M shown in Figure 8M.

The electronic device 1100 can be completed after removing the support carrier 11-52A. The electronic device 1100 may include interconnect dies 11-16 arranged upwards, wherein the interconnect dies 11-16 are electrically coupled to electronic components 11-11 and 11-12 in the horizontal direction. In some embodiments, when multiple electronic devices 1100 are manufactured in a matrix configuration, a single-piece dicing or sawing process may be performed to separate the multiple electronic devices into individual electronic devices 1100. Due to the single-piece dicing process, the lateral sides of the outer substrate 11-46, the inner encapsulation 11-51, the inner substrate 11-96, and the outer encapsulation 11-52 may be coplanar.

Figure 13J shows a cross-sectional view of the electronic assembly 1100A at a later stage of fabrication. In the example shown in Figure 13J, the electronic device 1100 may be disposed on the assembly substrate 11-56. In some embodiments, external interconnects 11-92 of the electronic device 1100 may be coupled to the assembly substrate 11-56. In some embodiments, underfill 11-61A may be disposed between the electronic device 1100 and the assembly substrate 11-56. In some embodiments, electronic components 11-58 may be additionally disposed on the assembly substrate 11-56 (see Figure 11). The assembly substrate 11-56 may include: a dielectric structure having one or more dielectric layers; and a conductive structure having one or more features defined by one or more conductive layers, such as pads, solder pads, or traces.

In some examples, the assembly substrates 11-56 may be preformed substrates. The preformed substrates may be manufactured prior to attachment to the electronic device and may include dielectric layers between corresponding conductive layers. The conductive layers may include copper and may be formed using an electroplating process. The dielectric layers may be relatively thick, non-photoconfinable layers that can be attached in the form of a preformed film rather than a liquid, and may contain resins with fillers such as strands, fabrics, or other inorganic particles for rigid or structural support. Because the dielectric layer is non-photoconfinable, features such as through-holes or openings can be formed using drilling or lasers. In some examples, the dielectric layer may include prepreg material or Ajinomoto laminate (ABF). A preformed substrate may include a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or FR4, and dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate with the permanent core structure omitted, and dielectric and conductive layers may be formed on a sacrificial carrier and removed after the dielectric and conductive layers are formed and before attachment to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such preformed substrates may be formed using a semi-additive process or a modified semi-additive process.

Figure 13K shows a cross-sectional view of the electronic assembly 1100A in a later stage of manufacturing. In the example shown in Figure 13K, peripheral structures 11-57 may be disposed on the assembly substrate 11-56. In some embodiments, peripheral structures 11-57 may include or be referred to as covers, shields, heat sinks, reinforcements, shrouds, or enclosures. In some embodiments, peripheral structures 11-57 may include conductive materials (e.g., copper, steel, or aluminum), dielectric materials (e.g., molding compounds, resins, or ceramics), or dielectric materials coated with conductive materials. In some instances, the peripheral structure 11-57 may be used as a preformed part, or may be formed in a suitable location by being applied as a layer or sputtered onto the top or side of the outer cladding 11-52 or the inner cladding 11-51.

In some embodiments, peripheral structures 11-57 may include sidewalls coupled to assembly substrates 11-56 and a top portion above said sidewalls and covering the top side of electronic device 1100. In some embodiments, adhesive 11-23A may couple the top portion of peripheral structures 11-57 to the top side of electronic device 1100. Adhesive 11-23A may include a thermal interface material (TIM) or an adhesive similar to adhesive 11-23. In some embodiments, peripheral structures 11-57 may lack a top portion and may only include peripheral sidewalls. In some embodiments, the sidewalls of peripheral structures 11-57 may be coupled to assembly substrates 11-56 via adhesive 11-23B. In some embodiments, adhesives 11-23B may include conductive adhesives, such as solder, that electrically couple peripheral structures 11-57 to portions of conductive structures, such as ground nodes, on the assembly substrate 11-56. In some embodiments, assembly interconnects 11-98 may be disposed on the underside of the assembly substrate 11-56. Assembly interconnects 11-98 may include, or be referred to as, conductive balls, conductive bumps, conductive posts, or conductive posts with solder caps.

When completed, the electronic assembly 1100A may include an electronic device 1100 having interconnecting dies 11-16 arranged in an upward orientation. When the electronic assembly 1100A is manufactured in a matrix configuration, a single-die cutting or sawing process may be performed to separate the individual assemblies.

Figure 14 shows a cross-sectional view of various illustrative examples of electronic device 1400, interconnecting dies 11-16, and electronic assembly 1400A according to this disclosure. The features, materials, structures, or processes of electronic device 1400, interconnecting dies 11-16, and electronic assembly 1400A may be similar to those of the example electronic device 1100, interconnecting dies 11-16, and electronic assembly 1100A shown in Figures 11-12. Example electronic device 1400 and electronic assembly 1400A, or similarly named portions thereof, may share any or all characteristics with any other device or assembly disclosed herein, or similarly named portions thereof.

In the example shown in Figure 14, the connecting dies 11-16 are positioned in a downward configuration, in which the connecting die interconnects 11-17 face the outer substrate 11-46 and the connecting die substrate 11-18 face the inner substrate 11-96.

Figures 15A to 15J illustrate exemplary methods of manufacturing exemplary electronic devices 1400 and exemplary electronic assemblies 1400A according to various configurations of this disclosure. The exemplary methods shown in Figures 15A to 15J are similar to the exemplary methods shown in Figures 13A to 13K, except that they use a downward-facing configuration of the connecting dies 11-16.

Figure 15A shows a cross-sectional view of the electronic assembly 1400A in an early stage of manufacturing. In the example shown in Figure 15A, device interconnects 11-14 may be formed or disposed on support carriers 11-46A. Device interconnects 11-14 may include or be referred to as pillars, rods, balls, leads, or bumps. In some examples, the features, materials, structures, or processes of Figure 15A may be similar to those of Example 600B shown in Figure 6B, Example 800B shown in Figure 8B, or the example shown in Figure 13B, except that device interconnects 11-14 are disposed on support carriers 11-46A without a substrate therebetween.

Figure 15B shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15B, the interconnect die 11-16 may be disposed on the support carrier 11-46A. In some embodiments, the adhesive 11-23 may be disposed between the interconnect die substrate 11-18 and the support carrier 11-46A or on the interconnect die substrate and the support carrier. In some embodiments, the adhesive 11-23 may include or be referred to as adhesive tape, adhesive film, or adhesive paste. In some examples, the features, materials, structures, or processes of FIG15B may be similar to those of Example 600C shown in FIG6C, Example 800C shown in FIG8C, or Example 13C shown in FIG13C, except that the connecting dies 11-16 are disposed on the support carriers 11-46A and there is no substrate therebetween.

In some embodiments, internal components 11-16z (FIG. 14) may be disposed on the support carrier 11-46A. In some embodiments, component interconnects 11-17z and component envelopes 11-19z may be attached to the support carrier 11-46A. Later, component interconnects 11-17z and component envelopes 11-19z may be coupled to the internal substrate 11-96, and the component body 11-15z may be coupled to the external substrate 11-46.

Figure 15C shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15C, an internal encapsulation 11-51 may be disposed on a support carrier 11-46A. The internal encapsulation 11-51 may cover not only the support carrier 11-46A but also the device interconnects 11-14 and the interconnect die 11-16. In some embodiments, the thickness of the internal encapsulation 11-51 may be greater than the thickness of the device interconnects 11-14 or the interconnect die 11-16. In this case, a thinning process may be performed, such as grinding or etching, to reduce the height of the internal encapsulation 11-51. In some embodiments, due to thinning processes, the top sides of device interconnects 11-14 and connecting dies 11-16 may be exposed through the internal encapsulation 11-51. In some embodiments, the top sides of connecting die interconnects 11-17 and connecting die encapsulations 11-19 may be exposed through the top side of the internal encapsulation 11-51. In some embodiments, the top sides of device interconnects 11-14 and connecting dies 11-16 may be coplanar with the top side of the internal encapsulation 11-51. In some embodiments, the top sides of the connecting grain interconnects 11-17 and the connecting grain encapsulations 11-19 may be coplanar with the top sides of the inner encapsulations 11-51. In some embodiments, the features, materials, structures, or processes of FIG15C may be similar to those of embodiments 600D and 600E shown in FIG6D and 6E, embodiments 800D and 800E shown in FIG8D and 8E, or the features, materials, structures, or processes of the embodiments shown in FIG13D.

Figure 15D shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15D, an outer substrate 11-46 may be formed or disposed on the device interconnect 11-14, the internal encapsulation 11-51, and the interconnect die 11-16. The outer substrate 11-46 may include a dielectric structure 11-47 and a conductive structure 11-48. In some embodiments, the dielectric structure 11-47 of the outer substrate 11-46 may contact the internal encapsulation 11-51 and the interconnect die encapsulation 11-19, or may be formed on the internal encapsulation and the interconnect die encapsulation. In some embodiments, the conductive structure 11-48 of the outer substrate 11-46 may be coupled to the device interconnect 11-14 or the interconnect die interconnect 11-17. Therefore, the interconnecting dies 11-16 can be electrically connected to the external substrate 11-46 via interconnecting die interconnects 11-17. In some embodiments, the features, materials, structures, or processes of FIG15D may be similar to those of Example 600A shown in FIG6A, Example 800A or 800F shown in FIG8A or 8F, or the features, materials, structures, or processes of the examples shown in FIG13A or 13E.

Figure 15E shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15E, external interconnects 11-92 may be formed or disposed on external substrates 11-46. In some embodiments, external interconnects 11-92 may be disposed on conductive structures 11-48 of external substrates 11-46. In some embodiments, external interconnects 11-92 may include or be referred to as conductive balls, conductive bumps, conductive pillars, or solder caps. In some embodiments, the features, materials, structures, or processes of Figure 15E may be similar to those of Example 600L shown in Figure 6L, Example 800M shown in Figure 8M, or the examples shown in Figure 13I.

Figure 15F shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15F, the support carrier 11-52A can be coupled over the external interconnect 11-92 or the external substrate 11-46 using an adhesive 223 that laterally defines the external interconnect 11-92, and the support carrier 11-46A can be removed. In some embodiments, the top side of the connection die 11-16, the internal encapsulation 11-51, and the device interconnect 11-14 can be exposed due to the removal of the support carrier 11-46A. In some embodiments, the adhesive 11-23 on the connection die 11-16 can be exposed through the internal encapsulation 11-51.

Figure 15G shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15G, the adhesive 11-23 on the interconnect dies 11-16 can be removed as needed. In some examples, the adhesive 11-23 can be removed by thinning processes such as grinding or etching. In some examples, the top sides of the device interconnects 11-14, the internal encapsulation 11-51, or the interconnect die substrate 11-18 can be made coplanar due to the thinning process. In some examples, the top side of the interconnect die substrate 11-18 can be exposed through the top side of the internal encapsulation 11-51. In some examples, the internal components 11-16z (Figure 14) can also be exposed through the internal encapsulation 11-51. In some embodiments, the top sides of the component interconnects 11-17z and component envelopes 11-19z of the internal components 11-16z may be exposed through the top side of the internal envelopes 11-51. In some embodiments, the features, materials, structures, or processes of FIG15G may be similar to those of embodiments 600D and 600E shown in FIG6D and 6E, embodiments 800D and 800E shown in FIG8D and 8E, or the features, materials, structures, or processes of the embodiments shown in FIG13D.

Figure 15H shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15H, an internal substrate 11-96 may be formed or disposed on the device interconnect 11-14, the internal encapsulation 11-51, and the connection die 11-16. The internal substrate 11-96 may include dielectric structures 11-97 and conductive structures 11-98. In some embodiments, the dielectric structure 11-97 of the internal substrate 11-96 may contact the internal encapsulation 11-51 and the connection die substrate 11-18, or may be formed on the internal encapsulation and the connection die substrate. In some embodiments, the conductive structure 11-98 of the internal substrate 11-96 may be coupled to the device interconnect 11-14 or the connection die substrate 11-18. Therefore, the internal substrate 11-96 can be electrically connected to the device interconnect 11-14 and the connection die 11-16. In some examples, the features, materials, structures or processes of FIG15H may be similar to those of Example 800F shown in FIG8F or the examples shown in FIG13E.

Figure 15I shows a cross-sectional view of the electronic assembly 1400A at a later stage of manufacturing. In the example shown in Figure 15I, electronic components 11-11 and 11-12 may be coupled to an internal substrate 11-96. In some embodiments, electronic components 11-11 or 11-12 may be similar to components 811a or 812a described herein. Electronic component 11-11 may include a set of component interconnects 11-11a having a relatively thin width or finer spacing and a set of component interconnects 11-11b having a relatively thick width or coarser spacing, and these sets of component interconnects 11-11a and 11-11b may be electrically connected to the conductive structure 11-98 of the internal substrate 11-96. Electronic components 11-12 may include a set of component interconnects 11-12a having a relatively thin width or finer spacing and a set of component interconnects 11-12b having a relatively thick width or coarser spacing, and these sets of component interconnects 11-12a and 11-12b may be electrically connected to the conductive structure 11-98 of the internal substrate 11-96.

In some embodiments, the bottom filler 11-61 may be additionally disposed between the electronic components 11-11, 11-12 and the internal substrate 11-96. The bottom filler 11-61 may be disposed between the top side of the electronic components 11-11 and 11-12 and the internal substrate 11-96, and may cover the lateral side of the electronic components 11-11 or 11-12. The bottom filler 11-61 may surround the lateral side of the component interconnects 11-11a, 11-11b, 11-12a, or 11-12b. Bottom filler 11-61 may be disposed between the electronic components 11-11 and 11-12 and the top side of the internal substrate 11-96, and may cover the lateral side of the electronic components 11-11 or 11-12. Bottom filler 11-61 may surround the lateral side of the component interconnects 11-11a, 11-11b, 11-12a, or 11-12b. In some embodiments, the features, materials, structures, or processes relating to the coupling of electronic components 11-11 and 11-12 in FIG15I may be similar to the features, materials, structures, or processes of Examples 600F and 600G shown in FIG6F to 6G, Examples 800G and 800H shown in FIG8G to 8H, or the examples shown in FIG13F.

In some embodiments, the outer encapsulation 11-52 may be disposed on the inner substrate 11-96 and electronic components 11-11 and 11-12. In some embodiments, the outer encapsulation 11-52 may cover the top side of the inner substrate 11-96, the top and (or lateral) sides of the electronic components 11-11 and 11-12, or the bottom filler 11-61. In some embodiments, the top side of the outer encapsulation 11-52 or the top side of the electronic components 11-11 and 11-12 may be thinned by grinding or etching. In some embodiments, the top side of the outer encapsulation 11-52 may be coplanar with the top side of the electronic components 11-11 and 11-12. In some embodiments, the top sides of electronic components 11-11 and 11-12 may be exposed through the top side of the outer enclosure 11-52. In some embodiments, the features, materials, structure, or process of the outer enclosure 11-52 shown in FIG15I may be similar to the features, materials, structure, or process of embodiments 600H and 600I shown in FIG6H and 6I, embodiments 800I and 800J shown in FIG8I and 8J, or the embodiment shown in FIG13G. In some embodiments, after the process of providing the outer enclosure 11-52, the support carrier 11-52A may be removed, and thus the external interconnect 11-92 may be exposed.

The electronic device 1400 can be completed after removing the support carriers 11-52A and adhesive 223. The electronic device 1400 may include interconnect dies 11-16 arranged downwards, in which high-density interconnect die substrates 11-18 face or are coupled to an inner substrate 11-96, and in which interconnect die interconnects 11-17 face or are coupled to an outer substrate 11-46. This downward-facing configuration allows the high-density interconnect dies 11-16 to electrically connect electronic components 11-11 and 11-12 to each other in a horizontal direction, and also allows the interconnect dies 11-16 to electrically connect electronic components 11-11 and 11-12 to the outer substrate 11-46 in a vertical direction for transmitting power or signals through the interconnect dies 11-16.

Figure 15J shows a cross-sectional view of the electronic assembly 1400A in a later stage of manufacturing. In the example shown in Figure 15J, the electronic device 1400 may be disposed on the assembly substrate 11-56. In some embodiments, external interconnects 11-92 of the electronic device 1400 may be electrically connected to the assembly substrate 11-56. In some embodiments, underfill 11-61A may be applied between the electronic device 1400 and the assembly substrate 11-56. In some embodiments, electronic components 11-58 (Figure 14) may be additionally disposed on the assembly substrate 11-56 and may include active devices such as processors, microcontrollers, memory, or transistor devices, or passive devices such as resistors, capacitors, inductors, or integrated passive devices (IPDs).

In some embodiments, peripheral structures 11-57 may be disposed on the assembly substrate 11-56. Peripheral structures 11-57 may include or be referred to as covers, shields, heat sinks, reinforcements, shrouds, or caps. In some embodiments, assembly interconnects 11-98 may be disposed on the underside of the assembly substrate 11-56. Assembly interconnects 11-98 may include or be referred to as conductive balls, conductive bumps, conductive posts, or conductive posts with solder caps. In some embodiments, the features, materials, structures, or processes of FIG15J may be similar to the features, materials, structures, or processes of the embodiments shown in FIG13J to 13K.

When completed, the electronic assembly 1400A may include an electronic device 1400 having interconnecting dies 11-16 arranged in a downward orientation. When the electronic assembly 1400A is manufactured in a matrix configuration, a single-die cutting or sawing process may be performed to separate the individual assemblies.

This document contains numerous illustrative figures illustrating various parts of a semiconductor device assembly (or package) and/or its manufacturing process. For clarity, these figures do not show all aspects of each example assembly. Any example assembly presented herein may share any or all characteristics with any or all other assemblies presented herein.

Various embodiments of this disclosure provide a semiconductor packaging structure and a method for manufacturing a semiconductor package. As a non-limiting example, various embodiments of this disclosure provide various semiconductor packaging structures and methods of manufacturing thereof, said semiconductor packaging structures including interconnecting dies that route electrical signals between a plurality of other semiconductor dies. Although the above has been described with reference to certain embodiments and examples, those skilled in the art will understand that various modifications and equivalents can be made without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt particular cases or materials to the teachings of this disclosure without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the specific examples disclosed, but rather that it includes all examples falling within the scope of the attached patent application.

100: Example Method / Method 105-190: Block 200A-1: Example 200A-2: Example 200A-3: Example 200A-4: Example 200B-1: Example 200B-2: Example 200B-3: Example 200B-4: Example 200B-5: Example 200B-6: Example 200B-7: Example 200C: Example 200D: Example 200E: Example 200F: Example 200G: Example 200H: Example 200I: Example 200J: Example 200K: Example 200L: Example 200M: Example 200N: Example 200O: Example 200P: Example 200Q: Example 201: Functional Grain 202: Functional Grain 203: Functional Grain 204: Functional Grain 211: Functional Grain / First Functional Grain 212: Functional Grain / Second Functional Grain 213: Grain Interconnection Structure / First Grain Interconnection Structure 214: Grain Interconnection Structure / Second Grain Interconnection Structure 216a: Connecting Grain 216b: Connecting Grain 216c: Connecting Grain 217: Connecting Grain Interconnection Structure 217b: Connecting Grain Interconnection Structure 221: Carrier 223: Adhesive 224: Underfill 225: Encapsulation Material 226: Encapsulation Material 226’: Encapsulation Material 226a: Encapsulation Material Portion 226b: Encapsulation Material Portion 231: Second Carrier 288: RD Structure 290: Support Layer 290a: Support Layer / Connecting Die 290b: Support Layer / Connecting Die 291: Substrate Dielectric Layer 292: First Conducting Trajectory 292b: First Conducting Trajectory 293: First Dielectric Layer 293b: First Dielectric Layer 294: Conductive Via 294b: Conductive Via 295: Second Conducting Trajectory 295b: Second Conducting Trajectory 296: Second Dielectric Layer 296b: Second Dielectric Layer 298: Redistribution (RD) Structure 298b: Redistribution (RD) Structure 299: Second-Connection Grain Interconnection Structure 300: Example Method / Method 305-390: Block 400A-1: Example 400A-2: Example 400A-3: Example 400A-4: Example 400B-1: Example 400B-2: Example 400C: Example 400D: Example 400E: Example 400F: Example 400G: Example 400H: Example 400H-2: Example 400I: Example 400J: Example 400K: Example 400L: Example 400M: Example 400N: Example 401: Functional Grain 402: Functional Grain 403: Functional Grain 404: Functional Grain 411: Functional Grain 412: Functional Grain 413: First Grain Interconnection Structure 414: Second Grain Interconnection Structure 416a: Connecting Grain 416b: Connecting Grain 417: Passivation Layer 421: First Carrier 423: Bottom Filler 424: Bottom Filler 426: Encapsulation Material 426’: Encapsulation Material 426a: Encapsulation Material Portion 426b: Encapsulation Material Portion 431: Second Carrier 488: Substrate 499: Interconnection Structure 500: Example Method / Method 505-590: Cube 600A: Example 600B: Example 600C: Example 600D: Example 600E: Example 600F: Example 600G: Example 600H: Example 600I: Example 600J: Example 600K: Example 600L: Example 600M: Structure 611a: Functional Grain 612a: Functional Grain 614: Second Grain Interconnection Structure 616b: Connecting Grain 617: Connecting Grain Interconnection Structure 621a: Block Carrier / First Carrier 646: RD Structure 646a: RD Structure / First Part of RD Structure 646b: RD Structure / Second part of the RD structure: 647: Dielectric layer 648: Conductive layer 651: Encapsulation material 651’: Encapsulation material 652: Encapsulation material 652’: Encapsulation material 652a: Encapsulation material portion 661: Bottom filler material 700: Example method / Method 705-790: Blocks 800A: Example 800B: Example 800C: Example 800D: Example 800E: Example 800F: Example 800G: Example 800H: Example 800I: Example 800J: Example 800K: Example 800L: Example 800M: Example 800N: Example 811a: Functional Grain 812a: Functional Grain 814: Vertical Interconnect Structure 816b: Connecting Grain 817: Interconnecting Grain Structure 821a: First Carrier / Block Carrier 846: RD Structure 846a: RD Structure / First Part of RD Structure 846b: RD Structure / Second Part of RD Structure 847: Dielectric Layer 848: Conductive Layer 851: Encapsulation Material / Pad 851’: Encapsulation Material 852: Interconnect Structure 852’: Encapsulation Material 852: Encapsulation Material Part 861: Bottom Filler Material 896: Second RD Structure / RD Structure 897: Dielectric Layer 898: Conductive Layer 900: Example Electronic Device 911: Functional Chip 912: Functional Chip 916: Connector Chip 930: Substrate 1000: Example Electronic Device 1030: Substrate 1100: Electronic Device 1100A: Electronic Assembly 11-11: Electronic Component 11-11a: Component Interconnect 11-11b: Component Interconnect 11-12: Electronic Component 11-12a: Component Interconnect / Component Interconnect Assembly 11-12b: Component Interconnect / Component Interconnect Assembly 11-14: Device Interconnect 11-15z: Component Body 11-16: Connector Chip 11-16A: Support Carrier 11-16z: Internal Components 11-17: Die Interconnects 11-17z: Component Interconnects 11-18: Die Interconnect Substrate 11-18z: Component Substrate 11-19: Die Interconnect Encapsulation 11-19z: Component Encapsulation 11-23: Adhesive 11-23A: Adhesive 11-23B: Adhesive 11-23z: Adhesive 11-46: External Substrate 11-46A: Support Carrier 11-47: Dielectric Structure 11-48: Conductive Structure 11-51: Internal Encapsulation 11-52: External Encapsulation 11-52A: Support Carrier 11-56: Assembly substrate 11-57: Peripheral structure 11-58: Electronic component/assembly 11-61: Underfill 11-61A: Underfill 11-92: External interconnects 11-96: Internal substrate 11-97: Dielectric structure 11-98: Conductive structure/assembly interconnects 1400: Electronic device 1400A: Electronic assembly

[Figure 1] A flowchart illustrating example methods of manufacturing electronic devices according to various forms of this disclosure.

[Figures 2A to 2Q] show cross-sectional views of various illustrative examples of electronic devices and examples of methods for manufacturing such electronic devices according to this disclosure.

[Figure 3] A flowchart illustrating example methods for manufacturing electronic devices according to various forms of this disclosure.

[Figures 4A to 4N] show cross-sectional views of various illustrative example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 5] A flowchart illustrating example methods for manufacturing electronic devices in various forms according to this disclosure.

[Figures 6A to 6M] show cross-sectional views of various illustrative examples of electronic devices and methods of manufacturing such electronic devices according to this disclosure.

[Figure 7] A flowchart illustrating example methods for manufacturing electronic devices according to various forms of this disclosure.

[Figures 8A to 8N] show cross-sectional views of various illustrative example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 9] shows a top view of various examples of electronic devices according to the present disclosure.

[Figure 10] shows a top view of various examples of electronic devices according to the present disclosure.

[Figure 11] shows a cross-sectional view of various illustrative examples of electronic devices, interconnecting chips, and electronic assemblies according to this disclosure.

[Figures 12A to 12E] show cross-sectional views illustrating example methods for manufacturing example interconnected grains according to various forms of this disclosure.

[Figures 13A to 13K] illustrate example methods of manufacturing example electronic devices and example electronic assemblies according to various forms of the present disclosure.

[Figure 14] shows a cross-sectional view of various illustrative examples of electronic devices, interconnecting chips, and electronic assemblies according to this disclosure.

[Figures 15A to 15J] illustrate example methods of manufacturing example electronic devices and example electronic assemblies in various forms according to this disclosure.

100: Instance methods/methods

105-190: Squares

Claims (23)

An electronic device includes: an upper signal redistribution structure, comprising a top side of the upper signal redistribution structure, a bottom side of the upper signal redistribution structure, and a plurality of horizontal sides of the upper signal redistribution structure; a lower signal redistribution structure, comprising a top side of the lower signal redistribution structure, a bottom side of the lower signal redistribution structure, and a plurality of horizontal sides of the lower signal redistribution structure; An electronic component includes a top side, a bottom side, and multiple lateral sides. The top side includes a signal redistribution structure, wherein a conductive structure of the signal redistribution structure is coupled to the bottom side of the upper signal redistribution structure, and multiple interconnection structures electrically couple the signal redistribution structure to the top side of the lower signal redistribution structure along the bottom side of the lower signal redistribution structure. Multiple vertical interconnection structures couple the bottom side of the upper signal redistribution structure to the top side of the lower signal redistribution structure at multiple locations laterally offset from the electronic component. A first semiconductor die includes a first die top side, a first die bottom side, and a plurality of first die lateral sides; A second semiconductor die includes a second die top side, a second die bottom side, and a plurality of second die lateral sides; A plurality of first die interconnect structures couple the first die bottom side and the second die bottom side to the top side of the upper signal redistribution structure, such that the first semiconductor die and the second semiconductor die are each electrically coupled to one or more of the vertical interconnect structures; A plurality of second die interconnect structures couple the first die bottom side and the second die bottom side to the top side of the upper signal redistribution structure, such that the first semiconductor die and the second semiconductor die are each electrically coupled to the electronic component; A bottom filler material located between the bottom side of the first grain and the top side of the upper signal redistribution structure, and also located between the bottom side of the second grain and the top side of the upper signal redistribution structure, wherein the bottom filler material laterally surrounds the first grain interconnect structure and the second grain interconnect structure; and an upper encapsulation material laterally surrounding the first semiconductor grain, the second semiconductor grain, and the bottom filler material. According to the electronic device of claim 1, wherein: the first semiconductor die and the second semiconductor die are each electrically coupled to the vertical interconnect structure via at least the first die interconnect structure and the upper signal redistribution structure; and the first semiconductor die and the second semiconductor die are each electrically coupled to the component signal redistribution structure via at least the second die interconnect structure and the upper signal redistribution structure. The electronic device according to claim 1, wherein each component interconnection structure includes a metal pillar. The electronic device according to claim 1, wherein the vertical interconnection structure vertically spans the electronic components. The electronic device according to claim 1 includes a lower encapsulating material that laterally surrounds the electronic component and the vertical interconnection structure. According to the electronic device of claim 5, wherein: the bottom side of the component is exposed from the lower encapsulating material, and the component interconnection structure electrically couples the component signal redistribution structure to the lower signal redistribution structure. The electronic device according to claim 1, wherein the bottom filler material covers at least a portion of the first grain lateral side and at least a portion of the second grain lateral side. The electronic device according to claim 1, wherein the electronic component includes a component envelope that encapsulates the underside of the component interconnection structure and the component signal redistribution structure. According to claim 1, in the electronic device, a first portion of the electronic component is located within the coverage area of the first semiconductor die, and a second portion of the electronic component is located within the coverage area of the second semiconductor die. An electronic device includes: a first signal redistribution structure, including a first redistribution structure first side and a second redistribution structure second side opposite to the first redistribution structure first side; a vertical interconnection structure on the first redistribution structure first side; an interconnection die on the first redistribution structure first side, including: an interconnection die signal redistribution structure, including a first side facing away from the first signal redistribution structure and a second side facing the first signal redistribution structure; an interconnection die interconnection member coupled to the second side of the interconnection die signal redistribution structure and the first side of the first redistribution structure; and an interconnection die encapsulation body encapsulating the interconnection die interconnection member and the second side of the interconnection die signal redistribution structure; and A second signal redistribution structure is provided on the vertical interconnect structure and on the first side of the interconnect die signal redistribution structure. The second signal redistribution structure includes a first side of the second redistribution structure facing away from the interconnect die and a second side of the second redistribution structure facing the interconnect die. The electronic device according to claim 10 includes a first semiconductor die coupled to a second side of the first rearrangement structure and a second semiconductor die coupled to the second side of the first rearrangement structure. The electronic device according to claim 10 includes an encapsulation material that encapsulates the vertical interconnect structure, the interconnecting die, a first side of the first redistribution structure, and a second side of the second redistribution structure. The electronic device according to claim 12, wherein the encapsulation material includes a side coplanar with the side of the connected die encapsulation. The electronic device according to claim 10 includes an adhesive layer that couples the first side of the interconnected die signal redistribution structure to the second side of the second redistribution structure. The electronic device according to claim 11 includes an encapsulation material encapsulating the first semiconductor die, the second semiconductor die, and the second side of the first rearrangement structure. The electronic device according to claim 10 includes a first semiconductor die coupled to a first side of the second rearrangement structure and a second semiconductor die coupled to the first side of the second rearrangement structure. The electronic device according to claim 16 includes an encapsulation material encapsulating the first semiconductor die, the second semiconductor die, and the first side of the second redistribution structure. According to the electronic device of claim 10, wherein: the second signal redistribution structure includes a dielectric structure and a conductive structure; the interconnecting die signal redistribution structure includes a dielectric structure and a conductive structure; and the conductive structure of the interconnecting die signal redistribution structure is in direct contact with the conductive structure of the second signal redistribution structure. A method of manufacturing an electronic device, the method comprising: providing an upper signal redistribution structure, the upper signal redistribution structure including a top side, a bottom side, and a plurality of horizontal sides; providing a lower signal redistribution structure, the lower signal redistribution structure including a top side, a bottom side, and a plurality of horizontal sides; An electronic component is provided, the lower electronic component including a top side, a bottom side, and multiple lateral sides, wherein the top side includes a signal redistribution structure, wherein a conductive structure of the signal redistribution structure is coupled to the bottom side of the upper signal redistribution structure, and wherein multiple interconnection structures electrically couple the signal redistribution structure to the top side of the lower signal redistribution structure along the bottom side of the signal redistribution structure; Multiple vertical interconnection structures are provided, the vertical interconnection structures coupling the bottom side of the upper signal redistribution structure to the top side of the lower signal redistribution structure at positions laterally offset from the electronic component; A first semiconductor die is provided, the first semiconductor die including a first top side, a first bottom side, and a plurality of first lateral sides; A second semiconductor die is provided, the second semiconductor die including a second top side, a second bottom side, and a plurality of second lateral sides; A plurality of first die interconnect structures are provided, the first die interconnect structures coupling the first bottom side and the second bottom side of the first die to the top side of the upper signal redistribution structure, such that the first semiconductor die and the second semiconductor die are each electrically coupled to one or more of the vertical interconnect structures; Provides a plurality of second die interconnect structures that couple the bottom sides of the first and second dies to the top side of the upper signal redistribution structure, such that the first and second semiconductor dies are each electrically coupled to the electronic component; Provides an underfill material located between the bottom sides of the first dies and the top side of the upper signal redistribution structure, and between the bottom sides of the second dies and the top side of the upper signal redistribution structure, wherein the underfill material laterally surrounds the first and second die interconnect structures; and Provides an upper encapsulation material laterally surrounding the first and second semiconductor dies and the underfill material. According to the method of claim 19, wherein: the first semiconductor die and the second semiconductor die are each electrically coupled to the vertical interconnect structure via at least the first die interconnect structure and the upper signal redistribution structure; and the first semiconductor die and the second semiconductor die are each electrically coupled to the component signal redistribution structure via at least the second die interconnect structure and the upper signal redistribution structure. The method according to claim 19 further comprises: providing a lower encapsulation material that laterally surrounds the electronic component and the vertical interconnect structure. According to the method of claim 21, each of the transverse sides of the upper signal redistribution structure is coplanar with the corresponding transverse side of the lower encapsulating material and coplanar with the corresponding transverse side of the upper encapsulating material. The electronic device of claim 19, wherein the electronic component includes a component encapsulation that encapsulates the underside of the component interconnection structure and the component signal redistribution structure.