TWI911965B - Semiconductor package and fabricating method thereof - Google Patents

Abstract

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Description

Semiconductor Packaging and Manufacturing Methods

This invention relates to semiconductor packaging and methods for manufacturing semiconductor packages. Cross-reference / merging of related applications

This application is a partial continuation-in-place of U.S. Patent Application No. 15/707,646, filed September 18, 2017, entitled "Semiconductor Package and Fabricating Method Thereof." U.S. Patent Application No. 15/707,646 is a partial continuation-in-place of U.S. Patent Application No. 15/594,313, filed May 12, 2017, also entitled "Semiconductor Package and Fabricating Method Thereof." U.S. Patent Application No. 15/594,313 is a partial continuation-in-place of U.S. Patent Application No. 15/594,313, filed July 11, 2016, entitled "Semiconductor Package and Fabricating Method Thereof." METHOD THEREOF" (now U.S. Patent No. 9,653,428), U.S. Patent Application No. 15/207,186 cited "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD" filed on January 27, 2016 THEREOF)", each of which is hereby incorporated by reference in its entirety.

This application relates to the following applications: U.S. Patent Application No. 14/686,725, filed April 14, 2015, entitled "SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH"; U.S. Patent Application No. 14/823,689, filed August 11, 2015, entitled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" (now U.S. Patent Application No. 9,543,242); and U.S. Patent Application No. 14/823,689, filed August 11, 2015, entitled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD". U.S. Patent Application No. 15/400,041 entitled “SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF”, filed on March 10, 2016, and U.S. Patent Application No. 15/066,724 entitled “SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF”, are incorporated herein by reference in their entirety.

Current semiconductor packaging and the methods used to form semiconductor packages are unsuitable, for example, leading to excessive costs, reduced reliability, or excessively large package sizes. Further limitations and drawbacks of conventional and traditional methods will become apparent to those skilled in the art when compared with the present disclosure as illustrated in the figures, which are described in the remainder of this application.

Various embodiments of this disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As a non-limiting example, various embodiments of this disclosure provide various semiconductor package structures and methods for manufacturing them, said semiconductor package structure including interconnecting dies that transmit electrical signals between a plurality of other semiconductor dies in a specific route.

The following discussion illustrates various forms of this disclosure by providing examples. These examples are non-limiting, and thus the scope of the various forms of this disclosure is not necessarily limited by any particular feature of the examples provided. In the following discussion, the terms “for example” and “exemplary” are non-limiting and are generally synonymous with “as an example and not a limitation”, “for example and not limiting”, etc.

As used in this article, "and/or" refers to any one or more items in a list connected by "and/or". For example, "x and/or y" represents any element in the three-element set {(x), (y), (x, y)}. In other words, "x and/or y" means "one or both of x and y". As another example, "x, y and/or z" represents any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and/or z" means "one or more of x, y, and z".

The terms used herein are for the purpose of describing specific examples only and are not intended to limit the scope of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “including,” “having,” etc., as used in this specification, indicate the presence of the stated features, wholes, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and/or groups thereof.

It should be understood that while the terms "first," "second," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, for example, without departing from the teachings of this disclosure, the first component, first part, or first portion discussed below may be referred to as the second component, second part, or second portion. Similarly, various spatial terms, such as "upper," "lower," "side," etc., may be used to distinguish one component from another in a relative manner. However, it should be understood that components may be oriented in different ways; for example, without departing from the teachings of this disclosure, a semiconductor device or package may be rotated laterally such that its "top" surface faces horizontally and its "side" surface faces vertically.

This disclosure provides various embodiments of a semiconductor device or package and a method of manufacturing the same, which can reduce costs, increase reliability, and/or improve the manufacturability of the semiconductor device or package.

The above and other variations of this disclosure will be described in and will become apparent from the following description of various embodiments. Various variations of this disclosure will now be presented with reference to the accompanying drawings, so that those skilled in the art can readily implement the various variations.

Figure 1 shows a flowchart of an example method 100 for manufacturing an electronic device (e.g., a semiconductor package, etc.). Example method 100 may share any or all features, for example, with any other example method discussed herein (e.g., example method 300 of Figure 3, example method 500 of Figure 5, example method 700 of Figure 7, etc.). The cross-sectional views shown in Figures 2A to 2Q illustrate various forms of example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to this disclosure. Figures 2A to 2Q may, for example, show example electronic devices in the various blocks (or steps) of method 100 of Figure 1. Figures 1 and Figures 2A to 2Q will now be discussed together. It should be noted that the order of the instance blocks in method 100 may be changed without departing from the scope of this disclosure.

Example method 100 may begin execution at block 105. Method 100 may begin execution in response to any of a variety of reasons or conditions, and non-limiting examples are provided herein. For example, method 100 may begin automatic execution in response to the arrival of components and/or manufacturing materials used during the execution of method 100, in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 100 may begin execution in response to an operator's command to begin. Additionally, for example, method 100 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 100 may include receiving, manufacturing, and/or preparing multiple functional dies at block 110. Block 110 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 110 may share any or all of the features of any of the functional die receiving, manufacturing, and/or preparing operations discussed herein. Various example states of block 110 are presented in Figure 2A.

Block 110 may include, for example, receiving multiple functional dies (or any portion thereof) from an upstream manufacturing process in the same facility or geographical location. Block 110 may also include, for example, receiving functional dies (or any portion thereof) from a supplier (e.g., from a foundry, etc.).

The received, manufactured, and/or prepared functional dies may include any of a variety of features. For example, although not shown, the received dies may include multiple different dies on the same wafer (e.g., a multi-project wafer (MPW)). An example of such a configuration is shown in Example 210A of Figure 2A of U.S. Patent Application No. 15/594,313, which is incorporated herein by reference in its entirety for all purposes. In this type of MPW configuration, the wafer may contain multiple functional dies of different types. For example, the first die may include a processor, and the second die may include a memory chip. As another example, the first die may include a processor, and the second die may include a coprocessor. Alternatively, for example, both the first and second dies may include a memory chip. Typically, the die may include active semiconductor circuitry. Although the various examples presented herein typically involve placing or attaching diced functional dies, such dies can also be interconnected before placement (e.g., as part of the same half-conductor wafer, as part of a reconstructed wafer, etc.).

Block 110 may, for example, include receiving functional dies in one or more corresponding wafers dedicated to a single type of die. For example, as shown in FIG. 2A, Example 200A-1 illustrates a wafer dedicated to an entire die 1, an example die of which is indicated by element symbol 211, and Example wafer 200A-3 illustrates a wafer dedicated to an entire die 2, an example die of which is indicated by element symbol 212. It should be understood that while the various examples shown herein generally involve first and second functional dies (e.g., die 1 and die 2), the scope of this disclosure extends to any number of functional dies of the same or different types (e.g., three dies, four dies, etc.). For example, in addition to or instead of functional semiconductor dies, the scope of this disclosure also extends to passive electronic components (e.g., resistors, capacitors, inductors, etc.).

Functional grains 211 and 212 may include grain interconnect structures. For example, as shown in FIG. 2A, the first functional grain 211 includes a first set of one or more grain interconnect structures 213 and a second set of one or more grain interconnect structures 214. Similarly, the second functional grain 212 may include such structures. Grain interconnect structures 213 and 214 may include any of a variety of grain interconnect structure features, and non-limiting examples thereof are provided herein.

The first grain interconnect structure 213 may include, for example, metal pillars (e.g., copper, aluminum, etc.) or connecting pads. The first grain interconnect structure 213 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, pillars, etc.

The first grain interconnect structure 213 can be formed in any of a variety of ways. For example, the first grain interconnect structure 213 can be plated onto the grain pad of the functional grain 211. As another example, the first grain interconnect structure 213 can be printed and reflowed, wire-bonded, etc. It should be noted that in some embodiments, the first grain interconnect structure 213 can be the grain pad of the first functional grain 211.

The first grain interconnect structure 213 can be capped, for example. For instance, the first grain interconnect structure 213 can be capped with solder. Or, for example, the first grain interconnect structure 213 can be capped with a metal layer (e.g., a metal layer other than solder, which forms a substituted solid solution or an intermetallic compound having copper). For example, the first grain interconnect structure 213 can be formed and/or connected as explained in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," the entire contents of which are hereby incorporated herein by reference. Additionally, for example, the first grain interconnect structure 213 may be formed and/or connected as explained in U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” the entire contents of which are hereby incorporated by reference.

The first grain interconnect structure 213 may include any of a variety of dimensional features. For example, in an exemplary embodiment, the first grain interconnect structure 213 may include a spacing of 30 micrometers (e.g., center-to-center spacing) and a diameter (or width, minor axis, or principal axis width, etc.) of 17.5 micrometers. As another example, in an exemplary embodiment, the first grain interconnect structure 213 may include a spacing in the range of 20 to 40 (or 30 to 40) micrometers and a diameter (or width, minor axis, or principal axis width, etc.) in the range of 10 to 25 micrometers. The first grain interconnect structure 213 may, for example, be 15 to 20 micrometers high.

The second grain interconnect structure 214 may, for example, share any or all of the features with the first grain interconnect structure 213. Some or all of the second grain interconnect structure 214 may, for example, be substantially different from the first grain interconnect structure 213.

The second grain interconnect structure 214 may include, for example, metal pillars (e.g., copper, aluminum, etc.) or connecting pads. The second grain interconnect structure 214 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, etc. The second grain interconnect structure 214 may be, for example, a general type of interconnect structure similar to the first grain interconnect structure 213, but it does not have to be. For example, both the first grain interconnect structure 213 and the second grain interconnect structure 214 may include copper pillars. As another example, the first grain interconnect structure 213 may include metal connecting pads, and the second grain interconnect structure 214 may include copper pillars.

The second grain interconnect structure 214 can be formed in any of a variety of ways. For example, the second grain interconnect structure 214 can be plated onto the grain pad of the functional grain 211. As another example, the second grain interconnect structure 214 can be printed and reflowed, wire-bonded, etc. The second grain interconnect structure 214 can be formed in the same process steps as the first grain interconnect structure 213, but such grain interconnect structures 213 and 214 can also be formed in separate steps and/or in overlapping steps.

For example, in a first embodiment, a first portion (e.g., a first half, the first third) of each of the second grain interconnects 214 can be formed in the same first electroplating operation as the first grain interconnect 213. Continuing with the first embodiment, a second portion (e.g., a second half, the remaining two-thirds, etc.) of each of the second grain interconnects 214 can then be formed in a second electroplating operation. For example, during the second electroplating operation, additional electroplating of the first grain interconnect 213 can be suppressed (e.g., by using a dielectric or protective shielding layer formed thereon, by removing electroplating signals, etc.). In another example scenario, the second grain interconnect structure 214 can be formed in a second electroplating process that is completely independent of the first electroplating process for forming the first grain interconnect structure 213, during which the first grain interconnect structure can be covered, for example, by a protective masking layer.

The second grain interconnect structure 214 may, for example, be uncapped. For instance, the second grain interconnect structure 214 may not be capped by solder. In an example scenario, the first grain interconnect structure 213 may be capped (e.g., capped by solder, capped by a metal layer, etc.), while the second grain interconnect structure 214 is uncapped. In another example scenario, both the first grain interconnect structure 213 and the second grain interconnect structure 214 are uncapped.

The second grain interconnect structure 214 may include any of a variety of dimensional features. For example, in an exemplary embodiment, the second grain interconnect structure 214 may include a spacing of 80 micrometers (e.g., center-to-center spacing) and a diameter (or width) of 25 micrometers or greater. As another example, in an exemplary embodiment, the second grain interconnect structure 214 may include a spacing in the range of 50 to 80 micrometers and a diameter (or width, minor axis, or principal axis width, etc.) in the range of 20 to 30 micrometers. Additionally, for example, in an exemplary embodiment, the second grain interconnect structure 214 may include a spacing in the range of 80 to 150 (or 100 to 150) micrometers and a diameter (or width, minor axis, or principal axis width, etc.) in the range of 25 to 40 micrometers. The second grain interconnect structure 214 can be, for example, 40 to 80 micrometers high.

It should be noted that functional grains (e.g., in wafer form, etc.) that already have one or more grain interconnection structures 213/214 (or any part thereof) formed thereon can be received.

It should also be noted that the functional grains (e.g., in wafer form) can be thinned from their original grain thickness (e.g., by grinding, mechanical and/or chemical thinning, etc.), but this is not necessary. For example, the functional grain wafers (e.g., the wafers shown in Examples 200A-1, 200A-2, 200A-3 and/or 200A-4) can be full-thickness wafers. As another example, the functional grain wafers (e.g., the wafers shown in Examples 200A-1, 200A-2, 200A-3, 200A-4, etc.) can be at least partially thinned to reduce the thickness of the resulting package while still achieving safe wafer handling.

Typically, block 110 may include receiving, manufacturing, and/or preparing multiple functional dies. Therefore, the scope of this disclosure should not be limited by any particular mode of receiving and/or manufacturing, nor by any particular feature of such functional dies.

Example method 100 may include receiving, manufacturing, and/or preparing interconnect dies at block 115. Block 115 may include receiving, manufacturing, and/or preparing multiple interconnect dies in any of various ways, and non-limiting examples thereof are provided herein. Various example states of block 115 are presented in Examples 200B-1 to Examples 200B-7 shown in Figures 2B-1 and 2B-2.

Block 115 may include, for example, receiving multiple interconnect dies from an upstream manufacturing process in the same facility or geographical location. Block 115 may also include, for example, receiving interconnect dies from a supplier (e.g., from a foundry, etc.).

The received, manufactured, and/or prepared interconnect dies may include any of a variety of features. For example, the received, manufactured, and/or prepared dies may include multiple interconnect dies on a wafer (e.g., a silicon or other semiconductor wafer, a glass wafer or panel, a metal wafer or panel, etc.). For example, as shown in Figure 2B-1, Example 200B-1 includes an entire wafer of interconnect dies, and an example interconnect die is shown by element symbol 216a. It should be understood that although the various examples shown herein generally relate to the use of a single interconnect die in a package, multiple interconnect dies (e.g., multiple interconnect dies having the same or different designs) may be used in a single electronic device package. Non-limiting examples of such configurations are provided herein.

In the examples illustrated herein (e.g., 200B-1 to 200B-4), the interconnect die may, for example, contain only electrical routing circuitry (e.g., no active semiconductor components and/or passive components). However, it should be noted that the scope of this disclosure is not limited thereto. For example, the interconnect die illustrated herein may include passive electronic components (e.g., resistors, capacitors, inductors, integrated passive devices (IPDs), etc.) and/or active electronic components (e.g., transistors, logic circuits, semiconductor processing components, semiconductor memory components, etc.) and/or optical components, etc.

Interconnect dies may include interconnect dies interconnect structures. For example, the example interconnect die 216a shown in FIG200B-1 includes interconnect dies interconnect structure 217. Interconnect dies interconnect structure 217 may include any of a variety of interconnect structure features, of which non-limiting examples are provided herein. Although this discussion generally presents all interconnect dies interconnect structures 217 as identical to each other, they may also differ from each other. For example, referring to FIG2B-1, the left portion of interconnect dies interconnect structure 217 may be the same as or different from the right portion of interconnect dies interconnect structure 217.

The interconnecting grain interconnect structure 217 and/or its formation may share any or all features with the first grain interconnect structure 213 and/or the second grain interconnect structure 214 and/or its formation discussed herein. In an exemplary embodiment, a first portion of the interconnecting grain interconnect structure 217 may include the spacing, layout, shape, size, and/or material characteristics of a corresponding first grain interconnect structure 213 that fits such a first portion to a first functional grain 211, and a second portion of the interconnecting grain interconnect structure 217 may include the spacing, layout, shape, size, and/or material characteristics of a corresponding first grain interconnect structure 213 that fits such a second portion to a second functional grain 212.

The interconnecting grain structure 217 may include, for example, metal pillars (e.g., copper, aluminum, etc.) or connecting pads. The interconnecting grain structure 217 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, pillars, etc.

The interconnecting die structure 217 can be formed in any of a variety of ways. For example, the interconnecting die structure 217 can be plated onto the die pad of the interconnecting die 216a. As another example, the interconnecting die structure 217 can be printed and reflowed, wire-bonded, etc. It should be noted that in some embodiments, the interconnecting die structure 217 can be the die pad of the interconnecting die 216a.

The interconnecting grain structure 217 can be capped, for example. For instance, the interconnecting grain structure 217 can be capped with solder. Or, for example, the interconnecting grain structure 217 can be capped with a metal layer (e.g., a metal layer forming a substituted solid solution or a copper intermetallic compound). For example, the interconnecting grain structure 217 can be formed and/or connected as explained in U.S. Patent Application No. 14/963,037, filed December 8, 2015, entitled "Transient Interface Gradient Bonding for Metal Bonds," the entire contents of which are hereby incorporated by reference. Additionally, for example, the interconnecting grain structure 217 may be formed and/or connected as explained in U.S. Patent Application No. 14/989,455, filed January 6, 2016, entitled “Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof,” the entire contents of which are hereby incorporated by reference.

The interconnecting die structure 217 can include any of a variety of dimensional features. For example, in an exemplary embodiment, the interconnecting die structure 217 may include a spacing of 30 micrometers (e.g., center-to-center spacing) and a diameter (or width, minor axis, or major axis width, etc.) of 17.5 micrometers. As another example, in an exemplary embodiment, the interconnecting die structure 217 may include a spacing in the range of 20 to 40 (or 30 to 40) micrometers and a diameter (or width, minor axis, or major axis width, etc.) in the range of 10 to 25 micrometers. The interconnecting die structure 217 may, for example, be 15 to 20 micrometers high.

In an example scenario, the interconnecting grain interconnection structure 217 may include a copper pillar that mates with the corresponding first grain interconnection structure 213 (e.g., metal connecting pad, conductive bump, copper pillar, etc.) of the first functional grain 211 and the second functional grain 212.

The interconnect die 216a (or its wafer 200B-1) can be formed in any of a variety of ways, and non-limiting examples are discussed herein. For example, referring to FIG. 2B-1, the interconnect die 216a (e.g., shown in example 200B-3) or its wafer (e.g., shown in example 200B-1) can include, for example, a support layer 290a (e.g., a silicon or other semiconductor layer, a glass layer, a metal layer, a plastic layer, etc.). A redistribution (RD) structure 298 can be formed on the support layer 290. The RD structure 298 can include, for example, a base dielectric layer 291, a first dielectric layer 293, a first conductive trace 292, a second dielectric layer 296, a second conductive trace 295, and an interconnect die interconnection structure 217.

The base dielectric layer 291 may, for example, be on the support layer 290. The base dielectric layer 291 may, for example, comprise an oxide layer, a nitride layer, or any of various inorganic dielectric materials. The base dielectric layer 291 may, for example, be formed according to specifications and/or may be natural. The base dielectric layer 291 may be referred to as a passivation layer. The base dielectric layer 291 may be or include, for example, a silicon dioxide layer formed using a low-pressure chemical vapor deposition (LPCVD) process. In other exemplary embodiments, the base dielectric layer 291 may be formed from any of various organic dielectric materials, many of which are provided herein.

The connecting die 216a (e.g., shown in Example 200B-3) or its wafer (e.g., shown in Example 200B-1) may also include, for example, a first conductive trace 292 and a first dielectric layer 293. The first conductive trace 292 may, for example, comprise a deposited conductive metal (e.g., copper, aluminum, tungsten, etc.). The first conductive trace 292 may be formed, for example, by sputtering, electroplating, electroless electroplating, etc. The first conductive trace 292 may be formed, for example, with a submicron or sub-two-micron spacing (or a center-to-center spacing). The first dielectric layer 293 may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It should be noted that in various embodiments, the first dielectric layer 293 may be formed prior to the first conductive trace 292, for example, by forming a hole, and then the hole is filled with the first conductive trace 292 or a portion thereof. In example embodiments that include copper conductive traces, the traces may be deposited using a double-drilling process.

In alternative components, the first dielectric layer 293 may comprise an organic dielectric material. For example, the first dielectric layer 293 may comprise bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, and equivalents and compounds thereof, but the scope of this disclosure is not limited thereto. Organic dielectric materials can be formed in any of various ways, such as chemical vapor deposition (CVD). In such alternative components, the first conductive traces 292 may, for example, have a spacing (or center-to-center spacing) of 2 to 5 micrometers.

The connecting die 216a (e.g., shown in Example 200B-3) or its wafer 200B-1 (e.g., shown in Example 200B-1) may also include, for example, a second conductive trace 295 and a second dielectric layer 296. The second conductive trace 295 may, for example, comprise a deposited conductive metal (e.g., copper, etc.). The second conductive trace 295 may, for example, be connected to a corresponding first conductive trace 292 via a corresponding conductive via 294 or a hole (e.g., in the first dielectric layer 293). The second dielectric layer 296 may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In alternative components, the second dielectric layer 296 may comprise an organic dielectric material. For example, the second dielectric layer 296 may include bismaleimide triazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin and its equivalents and compounds, but the scope of this disclosure is not limited thereto. The second dielectric layer 296 may be formed, for example, using a CVD process, but the scope of this disclosure is not limited thereto. It should be noted that various dielectric layers (e.g., the first dielectric layer 293, the second dielectric layer 296, etc.) may be formed from the same dielectric material and/or using the same process, but this is not required. For example, the first dielectric layer 293 may be formed from any inorganic dielectric material discussed herein, and the second dielectric layer 296 may be formed from any organic dielectric material discussed herein, and vice versa.

Although two sets of dielectric layers and conductive traces are shown in Figure 2B-1, it should be understood that the RD structure 298 connecting die 216a (e.g., shown in Example 200B-3) or its wafer (e.g., as shown in Example 200B-1) may include any number of such layers and traces. For example, the RD structure 298 may include only one dielectric layer and/or one set of conductive traces, three sets of dielectric layers and/or conductive traces, etc.

Interconnecting die interconnects 217 (e.g., conductive bumps, conductive balls, conductive pillars or struts, conductive pads or shims, etc.) can be formed on the surface of the RD structure 298. Examples of such interconnecting die interconnects 217 are shown in Figures 2B-1 and 2B-2, where the interconnecting die interconnects 217 are shown as being formed on the front (or top) surface of the RD structure 298 and electrically connected to corresponding second conductive traces 295 via conductive vias in the second dielectric layer 296. Such interconnecting die interconnects 217 can be used, for example, to couple the RD structure 298 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.), including, for example, the first functional die 211 and the second functional die 212 discussed herein.

The interconnecting die structure 217 may include, for example, any of a variety of conductive materials (e.g., any or a combination of copper, nickel, gold, etc.). The interconnecting die structure 217 may also include, for example, solder. As another example, the interconnecting die structure 217 may include solder balls or bumps, multi-ball solder pillars, elongated solder balls, metal (e.g., copper) core balls with a solder layer on a metal core, pillar structures (e.g., copper pillars, etc.), lead structures (e.g., lead-bonded leads), etc.

Referring to Figure 2B-1, Example 200B-1 of the wafer showing interconnect die 216a can be thinned to, for example, produce a thin interconnect die wafer with thin interconnect die 216b as shown in Example 200B-2. For example, the thin interconnect die wafer (e.g., as shown in Example 200B-2) can be thinned (e.g., by grinding, chemical and/or mechanical thinning, etc.) to a degree that still allows safe handling of the thin interconnect die wafer and/or its individual thin interconnect dies 216b but provides a low profile. For example, referring to Figure 2B-1, in an example embodiment where the support layer 290 comprises silicon, the thin interconnect die 216b can still include at least a portion of the silicon support layer 290. For example, the bottom (or back) surface of the thin interconnect die 216b may include sufficient non-conductive support layer 290, base dielectric layer 291, etc., to prevent conductive contact between the bottom surface of the remaining support layer 290 and the conductive layer on the top surface. In other embodiments, the thin interconnect die 216b may be thinned to substantially or completely remove the support layer 290. In such embodiments, conductive contacts on the bottom surface of the interconnect die 216b may still be blocked by the base dielectric 291.

For example, in one embodiment, the thin interconnect die wafer (e.g., as shown in Example 200B-2) or its thin interconnect die 216b may have a thickness of 50 micrometers or less. In another embodiment, the thin interconnect die wafer (or its thin interconnect die 216b) may have a thickness in the range of 20 to 40 micrometers. As will be discussed herein, the thickness of the thin interconnect die 216b may be less than the length of the second die interconnect structure 214 of the first die 211 and the second die 212, for example, such that the thin interconnect die 216b can be mounted between the carrier and the functional dies 211 and 212.

Two example interconnect die implementations, labeled “Interconnect Die Example 1” and “Interconnect Die Example 2”, are shown at 200B-5 in Figure 2B-2. Interconnect die example 1 can, for example, utilize an inorganic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and the semiconductor support layer 290. Interconnect die example 1 can, for example, be generated using Amkor Technology’s Silicon-Free Integrated Module (SLIM™) technology. The semiconductor support layer can, for example, be 30 to 100 μm (e.g., 70 μm) thick, and each layer (or sublayer or layer) of the RD structure (e.g., containing at least a dielectric layer and a conductive layer) can, for example, be 1 to 3 μm (e.g., 3 μm, 5 μm, etc.) thick. The total thickness of the resulting structure can be, for example, in the range of 33 to 109 μm (e.g., <80 μm, etc.). It should be noted that the scope of this disclosure is not limited to any particular size.

Interconnect die example 2 can, for example, utilize an organic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and semiconductor support layer 290. Interconnect die example 2 can, for example, be generated using Amkor Technology's silicon wafer integrated fan-out (SWIFT™) technology. The semiconductor support layer can, for example, be 30 to 100 μm (e.g., 70 μm) thick, and each layer (or sublayer or layer) of the RD structure (e.g., containing at least a dielectric layer and a conductive layer) can, for example, be 4 to 7 μm thick, 10 μm thick, etc. The total thickness of the resulting structure can, for example, be in the range of 41 to 121 μm (e.g., <80 μm, 100 μm, 110 μm, etc.). It should be noted that the scope of this disclosure is not limited to any particular size. It should also be noted that in various embodiment schemes, the support layer 290 of the interconnect die example 2 can be thinned (e.g., relative to the interconnect die example 1) to obtain the same or similar overall thickness.

The exemplary embodiments presented herein typically involve single-sided interconnect dies, which may, for example, have interconnect structures on only one side. However, it should be noted that the scope of this disclosure is not limited to such single-sided structures. For example, as shown in Examples 200B-6 and 200B-7, interconnect die 216c may include interconnect structures on both sides. Exemplary embodiments of such interconnect die 216c (e.g., as shown in Example 200B-7) and its wafer (e.g., as shown in Example 200B-6), which may also be referred to as double-sided interconnect dies, are shown in Figures 2B-2. The exemplary wafer (e.g., Example 200B-6) may, for example, share any or all of the features with the exemplary wafers shown in Figure 2B and discussed herein (e.g., Examples 200B-1 and/or 200B-2). For example, instance interconnect 216c may share any or all features with instance interconnects 216a and/or 216b shown in FIG. 2B-1 and discussed herein. For example, interconnect interconnect 217b may share any or all features with interconnect interconnect 217 shown in FIG. 2B-1 and discussed herein. For example, any or all of the redistribution (RD) structure 298b, base dielectric layer 291b, first conductive trace 292b, first dielectric layer 293b, conductive via 294b, second conductive trace 295b, and second dielectric layer 296b may share any or all of the features with the redistribution (RD) structure 298, base dielectric layer 291, first conductive trace 292, first dielectric layer 293, conductive via 294, second conductive trace 295, and second dielectric layer 296 shown in FIG. 2B-1 and discussed herein. Example interconnect die 216c also includes a second set of interconnect die interconnect structures 299 received and/or manufactured on the opposite side of interconnect die interconnect structure 217b. Such second interconnect die interconnect structures 299 may share any or all features with interconnect die interconnect structure 217. In example embodiments, the second interconnect die interconnect structure 299 may be formed first when RD structure 298b is deposited on a support structure (e.g., similar to support structure 290), and then removed, thinned, or planarized (e.g., by grinding, peeling, removal, etching, etc.).

Similarly, any or all of the exemplary methods and structures shown in U.S. Patent Application No. 15/594,313 can be performed by any such interconnecting die 216a, 216b and/or 216c, which is hereby incorporated herein by reference in its entirety.

It should be noted that one or more or all of the second interconnect die structures 299 may be isolated from other circuitry of the interconnect die 216c, which may also be referred to herein as dummy structures (e.g., dummy pillars, etc.), anchoring structures (e.g., anchor pillars, etc.). For example, any or all of the second interconnect die structures 299 may be formed solely for anchoring the interconnect die 216c to a carrier or RD structure or metal pattern in a later step. It should also be noted that one or more or all of the second interconnect die structures 299 may be electrically connected to traces, which may, for example, be connected to electronic device circuitry of the die attached to the interconnect die 216c. Such structures may be referred to, for example, as active structures (e.g., active pillars, etc.).

Typically, block 115 may include receiving, manufacturing, and/or preparing interconnecting dies. Therefore, the scope of this disclosure should not be limited by any particular feature of such receiving, manufacturing, and/or preparing or any particular feature of such interconnecting dies.

Example method 100 may include receiving, manufacturing, and/or preparing a first carrier at block 120. Block 120 may include any of the receiving, manufacturing, and/or preparing carriers in various ways, and non-limiting examples thereof are provided herein. For example, block 120 may share any or all of the features, for example, with other carrier receiving, manufacturing, and/or preparing steps discussed herein. Various example states of block 120 are shown at example 200C in FIG2C.

Block 120 may include, for example, receiving a carrier from an upstream manufacturing process in the same facility or geographical location. Block 120 may also include, for example, receiving a carrier from a supplier (e.g., from a foundry, etc.).

The received, manufactured, and/or prepared carrier 221 may include any of a variety of features. For example, carrier 221 may include a semiconductor wafer or panel (e.g., a typical semiconductor wafer, a low-grade semiconductor wafer utilizing silicon of a lower grade than the functional die discussed herein, etc.). As another example, carrier 221 may include metal, glass, plastic, etc. Carrier 221 may be, for example, reusable or destructible (e.g., single-use, multi-use, etc.).

The carrier 221 may include any of a variety of shapes. For example, the carrier may be wafer-shaped (e.g., circular, etc.), panel-shaped (e.g., square, rectangular, etc.), etc. The carrier 221 may have any of a variety of lateral dimensions and/or thicknesses. For example, the carrier 221 may have the same or similar lateral dimensions and/or thicknesses as the wafers of the functional grains and/or connecting grains discussed herein. As another example, the carrier 221 may have the same or similar thicknesses as the wafers of the functional grains and/or connecting grains discussed herein. The scope of this disclosure is not limited to any particular carrier characteristic (e.g., material, shape, size, etc.).

Example 200C shown in Figure 2C includes an adhesive material 223. The adhesive material 223 may include any of various types of adhesives. For example, the adhesive may be a liquid, paste, tape, etc.

Adhesive 223 may be of any size. For example, adhesive 223 may cover the entire top surface of the first carrier 221. Alternatively, adhesive may cover the central portion of the top surface of the first carrier 221 while leaving the outer edges of the top surface of the first carrier 221 uncovered. Or, for example, adhesive may cover the corresponding portion of the top surface of the first carrier 221 that corresponds in position to a future location of a functional die in a single electronic package.

The thickness of the adhesive 223 can be greater than the height of the second grain interconnect structure 214, and therefore also greater than the height of the first grain interconnect structure 213 (e.g., greater by 5%, 10%, 20%, etc.).

Instance carrier 221 may share any or all features with any carrier discussed herein. For example, but not limited to, a carrier may have no signal distribution layer, but may also include one or more signal distribution layers. Such a structure and instances of its formation are shown in instance 600A of Figure 6A and discussed herein.

Typically, block 120 may include receiving, manufacturing, and/or preparing a carrier. Therefore, the scope of this disclosure should not be limited by any particular conditions of receiving a carrier, any particular manner of manufacturing a carrier, and/or any particular manner of preparing such a carrier for use.

Example method 100 may include coupling (or mounting) a functional die to a carrier (e.g., coupling to the top surface of a non-conductive carrier, coupling to a metal pattern on the top surface of the carrier, coupling to an RD structure on the top surface of the carrier, etc.) at block 125. Block 125 may include performing such coupling in any of a variety of ways, and non-limiting examples are provided herein. For example, block 125 may share any or all of the features, for example, with other die mounting steps discussed herein. Various example states of block 125 are presented in example 200D shown in Figure 2D.

For example, functional dies 201-204 (e.g., any one of functional dies 211 and 212) can be received as individual dies. As another example, one or more functional dies 201-204 can be received on a single wafer, or one or more of functional dies 201-204 can be received on multiple corresponding wafers (e.g., as shown in examples 200A-1 and 200A-3, etc.), etc. In the case where one or two functional dies are received in wafer form, the functional dies can be diced from the wafer. It should be noted that if any functional die 201-204 is received on a single MPW, such a functional die can be diced from the wafer as an attachment device (e.g., connected to block silicon).

Block 125 may include placing functional grains 201-204 within the adhesive layer 223. For example, the second grain interconnect structure 214 and the first grain interconnect structure 213 may be fully (or partially) inserted into the adhesive layer 223. As discussed herein, the adhesive layer 223 may be thicker than the height of the second grain interconnect structure 214 such that when the bottom surface of the grains 201-204 contacts the top surface of the adhesive layer 223, the bottom end of the second grain interconnect structure 214 does not contact the carrier 221. However, in an alternative embodiment, the adhesive layer 223 may be thinner than the height of the second grain interconnect structure 214, but still thick enough to cover at least a portion of the first grain interconnect structure 213 when the grains 201-204 are placed on the adhesive layer 223.

Block 125 may include functional dies 201-204 placed using, for example, a die pick-and-place machine.

It should be noted that although the figures herein generally depict functional dies 201-204 (and their interconnections) as similar in size and shape, such symmetry is not required. For example, functional dies 201-204 may have different corresponding shapes and sizes, and may have different types and/or numbers of interconnections, etc. It should also be noted that functional dies 201-204 (or any so-called functional die discussed herein) may be semiconductor dies, but may also be any of various electronic components, such as passive electronic components, active electronic components, bare dies, packaged dies, etc. Therefore, the scope of this disclosure should not be limited to the characteristics of functional dies 201-204 (or any so-called functional die discussed herein).

Typically, block 125 may include coupling (or mounting) functional dies to a carrier. Therefore, the scope of this disclosure should not be limited by any particular manner of performing such coupling or any particular feature of such functional dies, interconnects, carriers, attachments, etc.

Example method 100 may include an encapsulation at block 130. Block 130 may include any of these encapsulations in various ways, and non-limiting examples are provided herein. Various instance forms of block 130 are presented in example 200E shown in Figure 2E. Block 130 may, for example, share any or all of the features with other encapsulations discussed herein.

Block 130 may include, for example, performing wafer (or panel) level molding processes. As discussed herein, any or all of the process steps discussed herein can be performed at the panel or wafer level before the individual modules are cut. Referring to the example embodiment 200E shown in FIG2E, encapsulation material 226' may cover at least part (or all) of the top surface of adhesive 223, the top surface of functional dies 201-204, and the side surfaces of functional dies 201-204. Encapsulation material 226' may also, for example, cover any portion of the second die interconnect structure 214, the first die interconnect structure 213, and the bottom surfaces of functional dies 201-204 exposed from 223 (if any such components are exposed).

Encapsulation material 226' may include any of the various types of encapsulation materials, such as molding materials, any dielectric materials presented herein, etc.

Although the encapsulation material 226' (as shown in FIG. 2E) is shown as covering the top surface of the functional grains 201-204, any or all of such top surfaces (or any corresponding portion of such top surfaces) may be exposed from the encapsulation material 226 (as shown in FIG. 2F). Block 130 may include, for example, the initial formation of an encapsulation material 226 in which the top surface of the grains is exposed (e.g., using film-assisted molding, grain sealing molding, etc.); forming an encapsulation material 226' and then performing a thinning process (e.g., performed at block 135) to thin the encapsulation material 226' to a point sufficient to expose the top surface of any or all functional grains 201-204; forming an encapsulation material 226' and then performing a thinning process (e.g., performed at block 135) to thin the encapsulation material but still retaining a portion of the encapsulation material 226' covering the top surface of any or all functional grains 201-204 (or any corresponding portion thereof); etc.

Typically, block 130 may include an encapsulation. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such encapsulation or the characteristics of any particular type of encapsulation material or its configuration.

Example method 100 may include grinding encapsulating material at block 135. Block 135 may include performing such grinding (or any thinning or planarization) in any of various ways, of which non-limiting examples are provided herein. Block 135 may, for example, share any or all of the features with other grinding (or thinning) blocks (or steps) discussed herein. Various example forms of block 135 are presented in example 200F shown in Figure 2F.

As discussed herein, in various embodiment examples, the encapsulating material 226' may initially be formed to a thickness greater than the final desired thickness. In such embodiment examples, block 135 may be executed to grind (or otherwise thin or planarize) the encapsulating material 226'. In embodiment 200F shown in FIG. 2F, the encapsulating material 226' has been ground to form the encapsulating material 226. The top surface of the ground (or thinned or planarized) encapsulating material 226 is coplanar with the top surfaces of the functional grains 201-204, thus exposing the functional grains from the encapsulating material 226. It should be noted that in various embodiment examples, one or more of the functional grains 201-204 may be exposed, while one or more of the functional grains 201-204 may remain covered by the encapsulating material 226. It should be noted that, if performed, this type of polishing operation does not require exposing the top surface of the functional grains 201-204.

In an example embodiment, block 135 may include grinding (or thinning or planarizing) the encapsulation material 226' and the back face of any or all functional grains 201-204, thereby achieving coplanarity between the top surface of the encapsulation material 226 and one or more of the functional grains 201-204.

Typically, block 135 may include abrasive encapsulating material. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of performing such abrasion (or thinning or planarization).

Example method 100 may include an attached second carrier at block 140. Block 140 may include any of the attached second carriers in various ways, and non-limiting examples are provided herein. For example, block 140 may share any or all of the features with any carriers discussed herein. Figure 2G illustrates various example states of block 140.

As shown in Example 200G of Figure 2G, the second carrier 231 can be attached to the top surface of the encapsulation material 226 and/or the top surface of the functional dies 201-204. It should be noted that the assembly may still be in wafer (or panel) form at this time. The second carrier 231 can include any of a variety of features. For example, the second carrier 231 can include a glass carrier, a silicon (or semiconductor) carrier, a metal carrier, a plastic carrier, etc. The cube 140 can include the second carrier 231 attached (or coupled or mounted) in any of a variety of ways. For example, the cube 140 can include attaching the second carrier 231 using an adhesive, a mechanical attachment mechanism, a vacuum attachment, etc.

Typically, block 140 may include a second carrier attached. Therefore, the scope of this disclosure should not be limited by any particular manner of the attachment of a carrier or by any particular type of carrier.

Example method 100 may include removal of the first carrier at block 145. Block 145 may include removal of the first carrier in any of various ways, and non-limiting examples are provided herein. For example, block 145 may share any or all of the features with any carrier removal process discussed herein. Various example states of block 145 are presented in example 200H shown in Figure 2H.

For example, Example 200H of Figure 2H shows the removal of the first carrier 221 (e.g., compared to Example 200G of Figure 2G). Block 145 may include performing this type of carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, or laser release, etc.).

For example, block 145 may include removing the adhesive layer 223 used at block 125 to couple the functional dies 201-204 to the first carrier 221. For example, such adhesive layer 223 may be removed together with the first carrier 221 in a single-step or multi-step process. For example, in an exemplary embodiment, block 145 may include pulling the first carrier 221 from the functional dies 201-204 and the encapsulation material 226, wherein the adhesive (or a portion thereof) is removed together with the first carrier 221. For example, block 145 may include the removal of adhesive layer 223 (e.g., the entire adhesive layer 223 and/or any portion of adhesive layer 223 remaining after the removal of the first carrier 221) from functional grains 201-204 (e.g., from the bottom surface of functional grains 201-204, from the interconnection structure of the first grain 213 and/or the second grain 214, etc.) and encapsulation material 226 using solvents, heat, light, or other cleaning techniques.

Typically, block 145 may include the removal of the first carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of removing the carrier or the characteristics of any particular type of carrier.

Example method 100 may include attaching (or coupling or mounting) a connection die to a functional die at block 150. Block 150 may include performing such attachment in any of a variety of ways, and non-limiting examples of this are provided herein. Block 150 may, for example, share any or all of the features with any die attachment process discussed herein. Various example states of block 150 are shown at Figure 2I.

For example, the grain interconnection structure 217 of the first interconnecting die 216b (e.g., any or all of such interconnecting dies) can be mechanically and electrically connected to the corresponding first grain interconnection structure 213 of the first functional die 201 and the second functional die 202.

Such interconnects can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In an exemplary embodiment, the first grain interconnect 213 and/or the connecting grain interconnect 217 may include a solder cap (or other solder structure) that can be reflowed to perform the connection. Such a solder cap can be reflowed, for example, by quality reflow, thermocompression bonding (TCB), etc. In another exemplary embodiment, the connection can be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without the use of solder. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, entitled "Transient Interface Gradient Bonding for Metal Bonds," filed December 8, 2015, and U.S. Patent Application No. 14/989,455, entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof," filed January 6, 2016, the entire contents of each of which are hereby incorporated by reference. The first grain interconnect structure 213 can be attached to the connecting grain interconnect structure 217 using any of the various techniques (e.g., quality reflow, thermo-press bonding (TCB), direct metal-to-metal intermetal bonding, conductive adhesive, etc.).

As shown in Example 200I, the first inter-die interconnect structure 213 of the first connecting die 201 is connected to the corresponding inter-die interconnect structure 217 of the connecting die 216b, and the first inter-die interconnect structure 213 of the second connecting die 202 is connected to the corresponding inter-die interconnect structure 217 of the connecting die 216b. During connection, the connecting die 216b provides electrical connection between the various inter-die interconnect structures of the first functional die 201 and the second functional die 202 via the RD structure 298 (e.g., as shown in Example 200B-3 of FIG. 2B-1).

In Example 200I shown in FIG2I, the height of the second grain interconnect structure 214 may, for example, be greater than (or equal to) the combined height of the first grain interconnect structure 213, the connecting grain interconnect structure 217, the RD structure 298, and any support layer 290b connecting the grain 216b. Such a height difference may, for example, provide space for a buffer material (e.g., underfill, etc.) between the connecting grain 216b and another substrate (e.g., as shown in Example 200N of FIG2N and discussed herein).

It should be noted that although the example interconnect die (216b) is shown as a single-sided interconnect die (e.g., similar to example interconnect die 216b in FIG. 2B-1), the scope of this disclosure is not limited thereto. For example, any or all of such example interconnect dies 216b may be double-sided (e.g., similar to example interconnect die 216c in FIG. 2B-2).

Typically, block 150 may include attaching (or coupling or mounting) a connection die to a functional die. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such attachment or the characteristics of any particular type of attachment structure.

Example method 100 may include underfilling of the interconnecting die at block 155. Block 155 may include performing this type of underfilling in any of a variety of ways, of which non-limiting examples are provided herein. Block 155 may, for example, share any or all of the features with any underfilling process discussed herein. Various example forms of block 155 are presented in example 200J shown in Figure 2J.

It should be noted that an underfill can be applied between the interconnect die 216b and the functional dies 201-204. In the case of using pre-applied underfill (PUF), such PUF can be applied to the functional dies 201-204 and/or to the interconnect die 216b before the interconnect structure 217 is coupled to the first die interconnect structure 213 of the functional dies 201-204 (e.g., at block 150).

Following the attachment performed at block 150, block 155 may include forming an underfill material (e.g., capillary underfill, etc.). As shown in the example embodiment 200J of FIG. 2J, the underfill material 223 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom surface of the connecting grain 216b (e.g., orientation as shown in FIG. 2J), and/or at least a portion (if not all) of the side surface of the connecting grain 216b. The underfill material 223 may also, for example, surround the connecting grain interconnect structure 217 and the first grain interconnect structure 213 of the functional grains 201-204. The underfill material 223 may additionally, for example, cover the top surface of the functional grains 201-204 in the region corresponding to the first grain interconnect structure 213 (orientation as shown in FIG. 2J).

It should be noted that in various implementations of example method 100, the bottom fill performed at block 155 can be skipped. For example, the bottom fill for the connecting grains can be performed at another block (e.g., at block 175, etc.). Or, for example, this type of bottom fill can be omitted entirely.

Typically, block 155 may include underfill for interconnecting dies. Therefore, the scope of this disclosure should not be limited to the features of any particular manner of performing this type of underfill or the features of any particular type of underfill.

Example method 100 may include the removal of a second carrier at block 160. Block 160 may include the removal of a second carrier in any of various ways, and non-limiting examples of this are provided herein. For example, block 160 may share any or all of the features with any carrier removal process discussed herein (e.g., with respect to block 145, etc.). Examples 200K shown in Figure 2K present various instance forms of block 160.

For example, the embodiment 200K shown in Figure 2K does not include the second carrier 231 of the embodiment 200J shown in Figure 2J. It should be noted that such removal may include, for example, cleaning the surface, removing adhesive (if used), etc.

Typically, block 160 may include the removal of a second carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such carrier removal or the characteristics of any particular type of carrier or carrier material being removed.

Example method 100 may include a single-piece cut at block 165. Block 165 may include performing such a single-piece cut in any of various ways, and non-limiting examples of this are discussed herein. Block 165 may, for example, share any or all of the features with any single-piece cut discussed herein. Example 200L shown in Figure 2L presents various instance forms of block 165.

As discussed herein, the example components shown can be formed on a wafer or panel containing multiple such components (or modules). For example, Example 200K shown in FIG2K has two components (left and right) bonded together by encapsulation material 226. In such example embodiments, the wafer or panel can be diced (or cut into pieces) to form individual components (or modules). In Example 200L of FIG2L, the encapsulation material 226 is sawed (or cut, broken, pulled, diced, or otherwise cut) into two encapsulation material portions 226a and 226b, each corresponding to a corresponding electronic device.

In the example embodiment 200L shown in Figure 2L, only the encapsulation material 226 needs to be trimmed. However, block 165 can include trimming any of various materials (if there is a single-piece cutting line (or trimming line)). For example, block 165 can include trimming underfill material, carrier material, functional and/or interconnecting die material, substrate material, etc.

Typically, block 165 can include single-piece cuts. Therefore, the scope of this disclosure should not be limited to any particular method of single-piece cutting.

Example method 100 may include mounting to a substrate at block 170. Block 170 may, for example, include performing such attachment in any of various ways, of which non-limiting examples are provided herein. For example, block 170 may share any or all features with any mounting (or attachment) steps discussed herein (e.g., attaching interconnects, attaching die backsides, etc.). Various example states of block 170 are presented in Example 400M shown in Figure 4M.

Substrate 288 may include any of a variety of features, and non-limiting examples are provided herein. For example, substrate 288 may include a packaging substrate, an interposer, a motherboard, a printed circuit board, a functional semiconductor die, a stacking redistribution structure of another device, etc. Substrate 288 may include, for example, a coreless substrate, an organic substrate, a ceramic substrate, etc. Substrate 288 may include, for example, one or more dielectric layers (e.g., organic and/or inorganic dielectric layers) and/or conductive layers formed on a semiconductor (e.g., silicon, etc.) substrate, a glass or metal substrate, a ceramic substrate, etc. Substrate 288 may, for example, share any or all of the features with the RD structure 298 of FIG. 2B-1, the RD structure 298b of FIG. 2B-2, any RD structure discussed herein, etc. The substrate 288 may include, for example, a single package substrate, or may include multiple substrates coupled together (e.g., in a panel or wafer) and subsequently diced.

In Example 200M shown in Figure 2M, block 170 may include welding (e.g., using quality reflow, thermoforming, laser welding, etc.) the second grain interconnect structure 214 of functional grains 201-202 to a corresponding pad (e.g., bonding pad, trace, connecting pad, etc.) or other interconnect structure (e.g., pillar, support, ball, bump, etc.) of substrate 288.

It should be noted that in the embodiment where interconnect die 216b is a double-sided interconnect die similar to interconnect die 216c, block 170 may also include a corresponding pad or other interconnect structure for connecting the second set of interconnect die interconnect structures 299 to the substrate 288. However, in embodiment 200M of FIG2M, interconnect die 216b is a single-sided interconnect die. It should be noted that, as discussed herein, since the second grain interconnect structure 214 of functional grains 201-202 is taller than the combined height of the first grain interconnect structure 213, the connecting grain interconnect structure 217, and the support layer 290b of the connecting grain 216b, a gap exists between the back surface of the connecting grain 216b (the bottom surface of the connecting grain 216b in FIG. 2M) and the top surface of the substrate 288. As shown in FIG. 2N, this gap can be filled with an underfill material.

Typically, block 170 includes mounting (or attaching or coupling) components (or modules) that are monolithically cut at block 165 to the substrate. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular type of mounting (or attachment) or any particular mounting (or attachment) structure.

Example method 100 may include underfilling at block 175 between the substrate and the component (or module) mounted thereon at block 170. Block 175 may include underfilling performed in any of various ways, and non-limiting examples thereof are provided herein. Block 175 may, for example, share any or all of the features with any underfill (or encapsulation) process discussed herein (e.g., with respect to block 155, etc.). Various forms of block 175 are presented in example 200N shown in FIG. 2N.

Block 175 may include, for example, performing capillary underfill or injected underfill treatment after installation at block 170. Alternatively, in a scenario utilizing pre-applied underfill (PUF), such PUF may be applied to the substrate, the substrate's metal pattern, and/or its interconnections prior to such installation. Block 175 may also include performing such underfill using a molding underfill process.

As shown in Example Embodiment 200N of Figure 2N, the underfill material 291 (e.g., any underfill material discussed herein) may completely or partially cover the top surface of the substrate 288. The underfill material 291 may also, for example, surround the second grain interconnect structure 214 (and/or the corresponding substrate pad) of the functional grains 201-202. The underfill material 291 may, for example, cover the bottom surface of the functional grains 201-202, the bottom surface of the connecting grain 216b, and the bottom surface of the encapsulation material 226a. The underfill material 291 may also, for example, cover the side surface of the connecting grain 216b and/or the exposed lateral surface of the underfill 223 between the connecting grain 216b and the functional grains 201-202. The bottom filler material 291 may, for example, cover the side surfaces of the encapsulation material 226a and/or the functional grains 201-202 (e.g., all or part of them).

In an embodiment where the bottom filler 223 is not formed, a bottom filler material 291 can be formed instead of the bottom filler 223. For example, referring to embodiment 200N, more bottom filler material 291 can be used instead of bottom filler material 223 in embodiment 200N.

In one embodiment where bottom filler 223 is formed, bottom filler material 291 can be a different type of bottom filler material than bottom filler material 223. In another embodiment, bottom filler materials 223 and 291 can both be the same type of material.

Similar to block 155, you can also skip block 175, for example, leaving space at another block location to be filled with another bottom filler (e.g., a molded bottom filler).

Typically, block 175 includes a bottom fill. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of bottom fill or any particular bottom fill material.

Instance method 100 may include execution continuation processing at block 190. Such continuation processing may include any of a variety of features, of which non-limiting examples are provided herein. For example, block 190 may include returning the execution flow of instance method 100 to any of its blocks. As another example, block 190 may include directing the execution flow of instance method 100 to any other method block (or step) discussed herein (e.g., with respect to instance method 300 of Figure 3, instance method 500 of Figure 5, etc.).

For example, the cube 190 may include an interconnection structure 299 (e.g., a conductive ball, a bump, a pillar, etc.) formed on the bottom surface of the substrate 288.

For example, as shown in Example 2000 of FIG. 20, block 190 may include encapsulating material 225. This encapsulating material 225 may, for example, cover the top surface of substrate 288, the side surface of bottom filler 224, the side surface of encapsulating material 226a, and/or the side surface of functional grains 201-202. In Example 2000 shown in FIG. 20, the top surfaces of encapsulating material 225, encapsulating material 226a, and/or functional grains 201-202 may be coplanar.

As discussed herein, underfill 224 may not be formed (e.g., as the underfill formed at block 175). In this case, encapsulating material 225 may be used instead of the underfill. An example 200P of such a structure and method is provided at Figure 2P. In example embodiment 200P, compared to example embodiment 200O shown in Figure 20, the underfill 224 of example embodiment 200O is replaced by encapsulating material 225 as the underfill.

As discussed herein, bottom filler 223 (e.g., as formed at block 155) and bottom filler 224 may not be formed. In this case, encapsulating material 225 may be used instead. An example embodiment 200Q of this type of structure and method is provided at FIG2Q. In contrast to example embodiment 200P shown in FIG2P, in example embodiment 200Q, the bottom filler 223 of example embodiment 200P is replaced with encapsulating material 225.

It should be noted that in any of the example embodiments 200O, 200P, and 200Q shown in Figures 2O, 2P, and 2Q, the side faces of the encapsulation material 225 and the substrate 288 may be coplanar.

In the example method 100 shown in Figures 1 and 2A-2Q, various grain interconnect structures (e.g., first grain interconnect structure 213, second grain interconnect structure 214, connecting grain interconnect structure 217 (and/or 299), etc.) are typically formed during the receiving, manufacturing, and/or preparation processes of the grains. For example, such various grain interconnect structures can typically be formed before their respective grains are integrated into the assembly. However, the scope of this disclosure should not be limited by the timing of such example embodiments. For example, any or all of the various grain interconnect structures can be formed after their respective grains are integrated into the assembly. An example method 300 showing the formation of grain interconnect structures at different stages will now be discussed.

Figure 3 shows a flowchart of an example method 300 for manufacturing an electronic device (e.g., a semiconductor package, etc.). Example method 300 may share any or all features with, for example, any other example method discussed herein (e.g., example method 100 of Figure 1, example method 500 of Figure 5, example method 700 of Figure 7, etc.). Figures 4A-4N show cross-sectional views illustrating various forms of example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to the present disclosure. Figures 4A-4N may illustrate example electronic devices, for example, in the various blocks (or steps) of method 300 of Figure 3. Figures 3 and 4A-4N will now be discussed together. It should be noted that the order of the instance blocks in method 300 may be changed without departing from the scope of this disclosure.

Example method 300 may begin execution at block 305. Method 300 may begin execution in response to any of a variety of reasons or conditions, and non-limiting examples are provided herein. For example, method 300 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 300 may begin execution in response to an operator command to begin. Additionally, for example, method 300 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 300 may include receiving, manufacturing, and/or preparing multiple functional dies at block 310. Block 310 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 310 may share any or all of the features with block 110 of example method 100 shown in FIG. 1 and discussed herein. Various forms of block 310 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A.

Block 310 may, for example, include receiving multiple functional dies from an upstream manufacturing process in the same facility or geographical location. Block 310 may also, for example, include receiving functional dies from a supplier (e.g., from a foundry, etc.). Block 310 may also, for example, include any or all features that form multiple functional dies.

In an exemplary embodiment, block 310 may share any or all features with block 110 of exemplary method 100 of FIG1, but does not have the first grain interconnect structure 213 and the second grain interconnect structure 214. It will be seen that such grain interconnect structures may be formed later in exemplary method 300 (e.g., at block 347, etc.). Although not shown in FIG4A, each of the functional grains 411-412 may, for example, include grain pads and/or under-bump metallization structures on which such grain interconnect structures may be formed.

The functional dies 411-412 shown in FIG4A may, for example, share any or all features with the functional dies 211-212 shown in FIG2A (e.g., without the first die interconnect structure 213 and the second die interconnect structure 214). For example, but not limited to, the functional dies 411-412 may include features of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Typically, block 310 may include receiving, manufacturing, and/or preparing multiple functional dies. Therefore, the scope of this disclosure should not be limited to any particular mode of performing such receiving, manufacturing, and/or preparation, nor to any particular feature of such functional dies.

Example method 300 may include receiving, manufacturing, and/or preparing interconnect dies at block 315. Block 315 may include receiving, manufacturing, and/or preparing one or more interconnect dies in any of various ways, of which non-limiting examples are provided herein. Block 315 may, for example, share any or all of the features with block 115 of example method 100 shown in FIG1 and discussed herein. Various example states of block 315 are presented in examples 400B-1 and 400B-2 shown in FIG4B.

The interconnecting dies 416a and/or 416b (or their wafers) may include, for example, an interconnecting die interconnect structure 417. The interconnecting die interconnect structure 417 may include any of a variety of features. For example, the formation of the interconnecting die interconnect structure 417 and/or any form thereof may have any or all of the features of the interconnecting die interconnect structure 217 and/or its formation shown in Figures 2B-1 to 2B-2 and discussed herein.

The interconnecting dies 416a and/or 416b (or their wafers) can be formed in any of a variety of ways, and non-limiting examples thereof are provided herein, for example, with respect to interconnecting dies 216a, 216b and/or 216c of Figures 2B-1 to 2B-2.

Typically, block 315 may include receiving, manufacturing, and/or preparing a connection die. Therefore, the scope of this disclosure should not be limited to any particular feature of performing such receiving, manufacturing, and/or preparation, nor to any particular feature of such a connection die.

Example method 300 may include receiving, manufacturing, and/or preparing a first carrier at block 320. Block 320 may include receiving, manufacturing, and/or preparing a first carrier in any of various ways, of which non-limiting examples are provided herein. Block 320 may share any or all features, for example, with other carrier receiving, manufacturing, and/or preparation steps discussed herein (e.g., with block 120 of example method 100 of FIG. 1).

Various instances of block 320 are presented in example 400C shown in Figure 4C. For example, carrier 421 may share any or all features with carrier 221 of Figure 2C. As another example, adhesive 423 may share any or all features with adhesive 223 of Figure 2C. However, it should be noted that since adhesive 423 does not receive the grain interconnection structure of functional grains (e.g., at block 325), adhesive 423 need not be as thick as adhesive 223.

Typically, block 320 may include receiving, manufacturing, and/or preparing a first carrier. Therefore, the scope of this disclosure should not be limited by any particular conditions of receiving a carrier, any particular manner of manufacturing a carrier, and/or any particular manner of preparing such a carrier for use.

Example method 300 may include coupling (or mounting) a functional die to a carrier (e.g., coupling to the top surface of a non-conductive carrier, coupling to a metal pattern on the top surface of the carrier, coupling to an RD structure on the top surface of the carrier, etc.) at block 325. Block 325 may include performing such coupling in any of a variety of ways, and non-limiting examples are provided herein. For example, block 325 may share any or all features, for example, with other die mounting steps discussed herein (e.g., at block 125 of example method 100 of FIG. 1, etc.).

Various instance types of block 325 are presented in instance 400D shown in Figure 4D. Instance 400D may share any or all features with instance 200D of Figure 2D. For example, functional grains 401-404 (e.g., instances of grains 411 and/or 412) may share any or all features with functional grains 201-204 of Figure 2D (e.g., instances of grains 211 and/or 212) (e.g., grain interconnect structures 213 and 214 do not extend into adhesive 223).

In Example 400D, the corresponding active surfaces of functional grains 401-404 are shown coupled to adhesive 423, but the scope of this disclosure is not limited to this type of orientation. In alternative embodiments, the corresponding non-active surfaces of functional grains 401-404 may be mounted to adhesive 423 (e.g., where functional grains 404-404 may have through-silicon vias or other structures for later connection to connecting grains, etc.).

Typically, block 325 may include coupling functional dies to the carrier. Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which such coupling is performed.

Example method 300 may include an envelope at block 330. Block 330 may include such an envelope in any of various ways, and non-limiting examples of this are provided herein. For example, block 330 may share any or all features with other envelopes discussed herein (e.g., block 130 of example method 100 of FIG1, etc.).

Various instance forms of block 330 are presented in instance 400E shown in Figure 4E. For example, encapsulating material 426' (and/or its formation) may share any or all features with encapsulating material 226' (and/or its formation) of Figure 2E.

Typically, block 330 may include an encapsulation. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 300 may include grinding (or otherwise thinning or planarizing) the encapsulating material at block 335. Block 335 may include performing such grinding (or any thinning or planarization process) in any of various ways, and non-limiting examples of this are provided herein. For example, block 335 may share any or all of the features with other grinding (or thinning or planarization) discussed herein (e.g., with block 135 of example method 100 of FIG. 1, etc.).

Various instance forms of block 335 are presented in instance 400F shown in Figure 4F. The encapsulating material 426 (and/or its formation) of the instance milled (or thinned or planarized, etc.) may share any or all features with the encapsulating material 226 (and/or its formation) of Figure 2F.

Typically, block 335 may include grinding (or otherwise thinning or planarizing) the encapsulating material. Therefore, the scope of this disclosure should not be limited to the features of any particular method of performing such grinding (or thinning or planarizing).

Example method 300 may include an attached second carrier at block 340. Block 340 may include any of the attached second carriers in various ways, and non-limiting examples of such attachments are provided herein. For example, block 340 may share any or all of the features with any carrier discussed herein (e.g., with block 140 of example method 100 of FIG1).

Various instance types of block 340 are shown in instance 400G shown in Figure 4G. The second carrier 431 (and/or its attachments) may, for example, share any or all features with the second carrier 231 of Figure 2G.

Typically, block 340 may include a second carrier attached. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of performing this type of attachment and/or the characteristics of any particular type of second carrier.

Example method 300 may include removal of the first carrier at block 345. Block 345 may include removal of the first carrier in any of various ways, and non-limiting examples thereof are provided herein. For example, block 345 may share any or all features with any carrier removal discussed herein (e.g., block 145 of example method 100 shown in FIG. 1).

Various instance states of block 345 are shown in instance 400H in Figure 4H-1. For example, the first carrier 421 has been removed relative to instance 400G.

Typically, block 345 may include the removal of the first carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of performing such removal.

Example method 300 may include forming an interconnection at block 347. Block 347 may include any of the forming interconnections in various ways, and non-limiting examples of such forming interconnections are provided herein. For example, block 347 may share any or all features with other forming interconnection processes (or steps) or blocks discussed herein (e.g., with respect to block 110 shown in Figure 1 and example method 100 discussed herein).

Various instance forms of block 347 are shown at instance 400H-2 in Figure 4H-2. The first grain interconnect structure 413 (and/or its formation) of Figure 4H-2 may share any or all features with the first grain interconnect structure 213 (and/or its formation) of Figure 2A. Similarly, the second grain interconnect structure 414 (and/or its formation) of Figure 4H-2 may share any or all features with the second grain interconnect structure 214 (and/or its formation) of Figure 2A.

Example embodiment 400H-2 includes a passivation layer 417 (or a re-passivation layer). Although not shown in the example embodiment of FIG. 2A and/or other example embodiments presented herein, such example embodiments may also include such a passivation layer 417 (e.g., between functional grains and grain interconnects and/or around the substrate of the grain interconnects, between connecting grains and connecting grain interconnects and/or around the substrate of the connecting grain interconnects, etc.). For example, if such a passivation layer 417 has not been formed prior to block 347, block 347 may include forming such a passivation layer 417. It should be noted that the passivation layer 417 may also be omitted.

In an example implementation, where functional grains are received or formed by an external inorganic dielectric layer, the passivation layer 417 may include an organic dielectric layer (e.g., any organic dielectric layer discussed herein).

The passivation layer 417 (and/or its formation) may include features of any passivation (or dielectric) layer (and/or its formation) discussed herein. The first grain interconnect structure 413 and the second grain interconnect structure 414 may be electrically connected to the functional grains 401-404, for example, through corresponding vias in the passivation layer 417.

Although a passivation layer 417 is shown on the molding layer 426 and the functional grains 401-404, the passivation layer 417 may also be formed only on the functional grains 401-404 (e.g., at block 310). In this type of embodiment, the outer surface of the passivation layer 417 (e.g., the upward-facing surface of the passivation layer 417 in FIG. 4H-2) may be coplanar with the corresponding surface of the encapsulation material 426 (e.g., the upward-facing surface of the encapsulation material 426 in FIG. 4H-2).

Typically, block 347 may include the formation of interconnected structures. Therefore, the scope of this disclosure should not be limited by any particular manner of such formation or any particular feature of interconnected structures.

Example method 300 may include attaching (or coupling or mounting) a connection die to a functional die at block 350. Block 350 may include performing such attachment in any of a variety of ways, and non-limiting examples thereof are provided herein. For example, block 350 may share any or all of the features, for example, with any die attachment discussed herein (e.g., with block 150 of example method 100 of FIG1).

Various instance types of block 350 are presented in example 400I shown in Figure 4I. The interconnection of connecting dies 416b, functional dies 401-404 and/or such dies to each other may, for example, share any or all features with the interconnection of connecting dies 216b, functional dies 201-204 and/or such dies to each other in example 200I shown in Figure 2I.

Typically, block 350 may include attaching a connection die to a functional die. Therefore, the scope of this disclosure should not be limited by the features of any particular manner of performing such attachments and/or the features of any particular structure used to perform such attachments.

Example method 300 may include underfilling of the interconnecting grains at block 355. Block 355 may include performing such underfilling in any of a variety of ways, of which non-limiting examples are provided herein. Block 355 may, for example, share any or all features with any underfilling discussed herein (e.g., with blocks 155 and/or 175, etc., of example method 100 of FIG1).

Various instance forms of block 355 are presented in example 400J shown in Figure 4J. For example, the bottom filler 423 (and/or its formation) of Figure 4J may share any or all features with the bottom filler 223 (and/or its formation) of Figure 2J. It should be noted that, as with any bottom filler discussed herein, various instance embodiments may omit the performance of such bottom fillers.

Typically, block 355 may include underfill for connecting grains. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill material.

Example method 300 may include the removal of a second carrier at block 360. Block 360 may include the removal of a second carrier in any of various ways, and non-limiting examples thereof are provided herein. For example, block 360 may share any or all features with any carrier removal discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1, with block 345, etc.).

In instance 400K shown in Figure 4K, various instance forms of block 360 are presented. For example, comparing Figure 4K with Figure 4J, the second carrier 431 has been removed.

Typically, a block 360 may include the removal of a second carrier. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of performing such removal.

Example method 300 may include a granular cut at block 365. Block 365 may include performing such a granular cut in any of various ways, of which non-limiting examples are discussed herein. Block 365 may, for example, share any or all features with any granular cut discussed herein (e.g., as discussed with respect to block 165 of example method 100 of FIG1).

Various instance forms of block 365 are presented in instance 400L shown in Figure 4L. The monolithic cut structure (e.g., corresponding to two encapsulation material portions 426a and 426b) may share any or all features with the monolithic cut structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b).

Typically, a block 365 may include single-piece cuts. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of single-piece cutting.

Example method 300 may include mounting to a substrate at block 370. Block 370 may, for example, include performing such mounting (or coupling or attachment) in any of various ways, of which non-limiting examples are provided herein. For example, block 370 may share any or all features with any mounting (or coupling or attachment) discussed herein (e.g., block 170, etc., with respect to example method 100 shown in FIG. 1).

The example 400M shown in Figure 4M presents various instance styles of block 370. For example, substrate 488 (and/or attachment to substrate 288 of this type) may share any or all features with substrate 288 (and/or attachment to substrate 288 of this type) in example 200M of Figure 2M.

Typically, block 370 may include mounting to a substrate. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of mounting to a substrate or any particular type of substrate.

Example method 300 may include underfilling at block 375 between the substrate and the component (or module) mounted thereon. Block 375 may include underfilling performed in any of a variety of ways, of which non-limiting examples are provided herein. Block 375 may, for example, share any or all features with any underfill (or encapsulation) process discussed herein (e.g., with respect to block 355, blocks 155 and 175, etc., of example method 100 of FIG. 1).

Various forms of block 375 are presented in example 400N shown in Figure 4N. The bottom fill 424 (and/or its formation) may share any or all features, for example, with the bottom fill 224 (and/or its formation) shown in example 200N of Figure 2N. It should be noted that, as with any bottom fill discussed herein, the bottom fill of block 375 may be skipped or may be performed at different points in the method.

Typically, block 375 may include bottom fill between the substrate and the components mounted to the substrate. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular manner of mounting to the substrate or any particular type of substrate.

Instance method 300 may include execution of continuation processing at block 390. Such continuation processing may include any of a variety of features, of which non-limiting instances are provided herein. For example, block 390 may share any or all features with block 190 of instance method 100 of Figure 1 discussed herein.

For example, block 390 may include returning the execution flow of instance method 300 to any of its blocks. As another example, block 390 may include directing the execution flow of instance method 300 to any other method block (or step) discussed herein (e.g., with respect to instance method 100 of Figure 1, instance method 500 of Figure 5, instance method 700 of Figure 7, etc.).

For example, the cube 390 may include an interconnection structure 499 (e.g., a conductive ball, a bump, a pillar, etc.) formed on the bottom surface of the substrate 488.

For example, as shown in Example 200O of FIG2O, Example 200P of FIG2P and Example 200Q of FIG2Q, block 390 may include forming encapsulation material and/or bottom filler (or skip forming encapsulation material and/or bottom filler).

In the various embodiment examples discussed herein, the functional die is mounted to the carrier before the interconnect die is attached to the functional die. The scope of this disclosure is not limited to this type of mounting sequence. Non-limiting examples will now be presented in which the interconnect die is mounted to the carrier before the interconnect die is attached to the functional die.

Figure 5 shows a flowchart of an example method 500 for manufacturing an electronic device according to various forms of the present disclosure. Example method 500 may share any or all features, for example, with any other example method discussed herein (e.g., example method 100 of Figure 1, example method 300 of Figure 3, example method 700 of Figure 7, etc.). Figures 6A-6M show cross-sectional views illustrating example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to the present disclosure. Figures 6A-6M may illustrate example electronic devices, for example, in the blocks (or steps) of method 500 of Figure 5. Figures 5 and 6A-6M will now be discussed together. It should be noted that the order of the instance blocks in Method 500 may be changed without departing from the scope of this disclosure.

Example method 500 may begin execution at block 505. Method 500 may begin execution in response to any of a variety of causes or conditions, and non-limiting examples are provided herein. For example, method 500 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 500 may begin execution in response to an operator command. Additionally, for example, method 500 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 500 may include receiving, manufacturing, and/or preparing multiple functional dies at block 510. Block 510 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 510 may share any or all features with block 310 of example method 300 shown in FIG. 3 and discussed herein. Various forms of block 510 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A. It should be noted that block 510 may also share any or all features, for example, with block 110 of example method 100 shown in FIG. 1 and discussed herein.

The functional dies 611a and 612a (and/or their formations) shown in many figures in Figures 6A-6M may share any or all features with, for example, the functional dies 411 and 412 (and/or their formations) of Figure 4A, and the functional dies 211-212 (and/or their formations) of Figure 2A. For example, but not limited to, functional dies 611 and 612 may include features of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Typically, block 510 may include receiving, manufacturing, and/or preparing multiple functional dies. Therefore, the scope of this disclosure should not be limited to any particular mode of performing such receiving and/or manufacturing, nor to any particular feature of such functional dies.

Example method 500 may include receiving, manufacturing, and/or preparing interconnect dies at block 515. Block 515 may include receiving and/or manufacturing multiple interconnect dies in any of various ways, and non-limiting examples of this are provided herein. For example, block 515 may share any or all features with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example states of block 515 are presented in examples 200B-1 and 200B-7 shown in FIG. 2B-1 to 2B-2. It should be noted that block 515 may also share any or all features with block 315 of example method 300 shown in FIG. 3 and discussed herein.

The interconnecting grains 616b and interconnecting grain interconnects 617 (and/or their formation) shown in many of the figures in Figures 6A-6M may share any or all of the features, for example, with the interconnecting grains 216b and interconnecting grain interconnects 217 (and/or their formation) of Figures 2B-1 to 2B-2.

It should be noted that the interconnecting grain interconnect structure 617 (and/or its formation) may, for example, share any or all features with the first grain interconnect structure 213 (and/or its formation). For example, in an exemplary embodiment, instead of forming a first grain interconnect structure such as the first grain interconnect structure 213 of FIG. 2A on the functional grains 211/212, the same or similar interconnecting grain interconnect structure 617 may be formed on the interconnecting grain 616b.

Typically, block 515 may include receiving, manufacturing, and/or preparing interconnecting dies. Therefore, the scope of this disclosure should not be limited to any particular feature of such receiving, manufacturing, and/or preparing or any particular feature of such interconnecting dies.

Example method 500 may include at block 520 a carrier having a signal redistribution (RD) structure (or distribution structure) thereon. Block 520 may include performing such receiving, manufacturing and/or preparation in any of various ways, and non-limiting examples thereof are provided herein.

Block 520 may share any or all features with any or all carriers that are received, manufactured, and/or prepared (e.g., block 120 with respect to example method 100 of FIG1, block 320 with respect to example method 300 of FIG3, etc.). Various instance forms of block 520 are provided in example 600A of FIG6A.

As discussed herein, any or all carriers discussed herein may include, for example, only bulk materials (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal redistribution (RD) structures on (or instead of bulk materials). Block 520 provides examples of receiving, manufacturing, and/or preparing such carriers.

Block 520 may include an RD structure 646a formed on a block carrier 621a in any of various ways, of which non-limiting examples are presented herein. In an exemplary embodiment, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to a second grain interconnect structure 614 (formed later), which will ultimately connect to functional grains 611 and 612 (connected later).

Figure 6A illustrates an example in which the RD structure 646a includes three dielectric layers 647 and three conductive layers 648. This number of layers is merely an example, and the scope of this disclosure is not limited thereto. In another embodiment, the RD structure 646a may include only a single dielectric layer 647 and a single conductive layer 648, two dielectric layers and two conductive layers, etc. The example redistribution (RD) structure 646a is formed on a bulk carrier material 621a.

The dielectric layer 647 can be formed from any of the various materials (e.g., _Si3N4 , _SiO2 , _SiON , PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 647 can be formed using any of the various processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 647 can be patterned, for example, to expose various surfaces (e.g., exposing the lower traces or pads of the conductive layer 648).

The conductive layer 648 can be formed from any of various materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 648 can be formed using any of various processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 646a may include, for example, conductors exposed at its outer surface (e.g., at the top surface of example 600A). Such exposed conductors may be used, for example, for attaching (or forming) grain interconnect structures (e.g., at block 525, etc.). In such embodiments, the exposed conductors may include pads and may include, for example, under-bump metal (UBM) formed thereon to enhance the attachment (or formation) of the grain interconnect structures. Such under-bump metal may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

Examples of redistribution structures and/or their formation are provided in U.S. Patent Application No. 14/823,689, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”, filed August 11, 2015; and in U.S. Patent Application No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; each of the above applications is hereby incorporated herein by reference in its entirety.

The redistribution structure 646a may, for example, perform fan-out redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to be formed) die interconnect structure 614 to locations outside the coverage areas of the functional dies 611 and 612 to which such die interconnect structure 614 will be attached. Alternatively, the redistribution structure 646a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to be formed) die interconnect structure 614 to locations within the coverage areas of the (to be connected) connecting die 616b and/or to locations within the coverage areas of the (to be connected) functional dies 611 and 612. The redistribution structure 646a can also provide, for example, connectivity between functional dies 611 and 612 (e.g., in addition to the connectivity provided by the connecting die 616b).

In various implementation schemes, block 520 may include a first portion 646a that forms only the entire RD structure 646, wherein a second portion 646b of the entire RD structure 646 may be formed later (e.g., at block 570).

Typically, block 520 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure thereon. Therefore, the scope of this disclosure should not be limited to any particular manner of manufacturing such a carrier and/or signal redistribution structure or any particular feature of such a carrier and/or signal redistribution structure.

Example method 500 may include forming a high-grain interconnect structure on the RD structure (e.g., as provided at block 520) at block 525. Block 525 may include forming a high-grain interconnect structure on the RD structure in any of various ways, and non-limiting examples thereof are provided herein.

Block 525 may share any or all features (e.g., second grain interconnection features, etc.) with any or all functional grain receiving, manufacturing and/or preparation discussed herein (e.g., the formation of block 110 and second grain interconnection structure 214 and/or the formation of first grain interconnection structure 213 in respect of example method 100 of FIG1, the formation of block 347 and second grain interconnection structure 414 in respect of example method 347 of FIG3, etc.).

Various instance forms of block 525 are provided in example 600B of Figure 6B. The high interconnect structure 614 (and/or its formation) may share any or all features with the second grain interconnect structure 214 (and/or its formation) of Figure 2A and/or with the second grain interconnect structure 414 (and/or its formation) of Figure 4H-2.

Typically, block 525 may include a high-grain interconnect structure formed on the RD structure (e.g., as provided at block 520). Therefore, the scope of this disclosure should not be limited by the features of any particular manner of forming such a high-grain interconnect structure and/or the features of any particular type of high interconnect structure.

Example method 500 may include mounting a connection die to the RD structure at block 530 (e.g., as provided at block 520). Block 530 may include performing such mounting (or attachment or coupling) in any of various ways, and non-limiting examples of this are provided herein. Block 530 may, for example, share any or all features with any die attachment discussed herein (e.g., block 325 with respect to example method 300 shown in FIG. 3 and discussed herein, block 125 with respect to example method 100 shown in FIG. 1 and discussed herein, etc.). Various example forms of block 530 are presented in example 600C shown in FIG. 6C.

Block 530 may, for example, include attaching the back side of the connecting die 616b to the RD structure 646a using a die-attach adhesive (e.g., tape, liquid, paste, etc.). Although a dielectric layer coupling the connecting die 616b to the RD structure 646a is shown in FIG. 6C, in other embodiments, the back side of the connecting die 616b may be coupled to a conductive layer (e.g., to provide additional structural support for enhanced heat dissipation).

Additionally, as discussed herein, any interconnecting die discussed herein may be double-sided. In such example embodiments, the back-side interconnection may be electrically connected to the corresponding interconnection of the RD structure 646a (e.g., pads, interconnecting pads, bumps, etc.).

Typically, block 530 may include mounting a connector die to the RD structure (e.g., as provided at block 520). Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which the connector die is mounted.

Example method 500 may include an encapsulation at block 535. Block 535 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. Block 535 may, for example, share any or all of the features with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, etc.). Various example states of block 535 are shown in FIG. 6D.

Block 535 may include, for example, performing wafer (or panel) level molding processes. As discussed herein, any or all of the process steps discussed herein can be performed at the panel or wafer level before the individual modules are diced. Referring to the example embodiment 600D shown in Figure 6D, the encapsulation material 651' may cover at least part (or all) of the top surface of the RD structure 646a, the tall pillars 614, the interconnecting die interconnects 617, the top surface (or active surface or front surface) of the connecting die 616b, and the side surface of the connecting die 616b.

Although the encapsulating material 651' (as shown in FIG. 6D) is shown to cover the top end of the high interconnect structure 614 and the top end of the connecting grain interconnect structure 617, any or all of these ends may be exposed from the encapsulating material 651' (as shown in FIG. 6E). Block 535 may, for example, include initially forming the encapsulating material 651', where the top ends of various interconnects are exposed or protruding (e.g., using film-assisted molding, grain sealing molding, etc.). Alternatively, block 535 may include forming the encapsulating material 651' followed by a thinning (or planarization or grinding) process (e.g., performed at block 540) to thin the encapsulating material 651' sufficiently to expose the top surfaces of any or all of the high interconnect structure 614 and the connecting grain interconnect structure 617, etc.

Typically, block 535 may include an encapsulation. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such encapsulation or the characteristics of any particular type of encapsulation material or its configuration.

Example method 500 may include a grinding encapsulating material and/or various interconnections at block 540. Block 540 may include performing such grinding (or any thinning or planarization) in any of various ways, and non-limiting examples of this are provided herein. Various example forms of block 540 are presented in example 600E shown in Figure 6E. Block 540 may, for example, share any or all of the features with other grinding (or thinning or planarization) blocks (or steps) discussed herein.

As discussed herein, in various embodiment schemes, the encapsulating material 651' may initially be formed to a thickness greater than the final required thickness, and/or the high interconnect structure 614 and the interconnecting grain interconnect structure 617 may initially be formed to a thickness greater than the final required thickness. In such embodiment schemes, block 540 may be executed to grind (or otherwise thin or planarize) the encapsulating material 651', the high interconnect structure 614, and/or the interconnecting grain interconnect structure 617. In embodiment 600E shown in FIG. 6E, the encapsulating material 651, the high interconnect structure 614, and/or the interconnecting grain interconnect structure 617 have been ground to produce the encapsulating material 651 and the interconnect structures 613 and 617 (as shown in FIG. 6E). The top surfaces of the milled encapsulating material 651, the top surfaces of the highly interconnected structure 614, and/or the top surfaces of the grain interconnected structure 617 may, for example, be coplanar.

It should be noted that in various implementation schemes, such as by using chemical or mechanical processes that make the encapsulating material 651 thinner than the interconnecting structures 614 and/or 617, or by using film-assisted and/or sealing molding processes at block 535, the top surface of the high interconnecting structure 614 and/or the top surface of the connecting grain interconnecting structure 617 may protrude from the top surface of the encapsulating material 651.

Typically, block 540 may include milled (or thinned or planarized) encapsulating material and/or various interconnect structures. Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which such milling (or thinning or planarization) is performed.

Example method 500 may include attaching (or coupling or mounting) a functional die to a high interconnect structure and connecting the die interconnect structure at block 545. Block 545 may include performing such attachment in any of a variety of ways, and non-limiting examples of this are provided herein. Block 545 may, for example, share any or all of the features with any die attachment process discussed herein. Various example states of block 545 are presented in example 600F shown in Figure 6F.

For example, the grain interconnect structure (e.g., pads, bumps, etc.) of the first functional grain 611a can be mechanically and electrically connected to the corresponding high interconnect structure 614 and connected to the corresponding connecting grain interconnect structure 617. Similarly, the grain interconnect structure (e.g., pads, bumps, etc.) of the second functional grain 612a can be mechanically and electrically connected to the corresponding high interconnect structure 614 and connected to the corresponding connecting grain interconnect structure 617.

Such interconnect structures can be connected in any of a variety of ways. For example, connections can be made by soldering. In an exemplary embodiment, the corresponding interconnect structures of the high-grain interconnect structure 614, the connecting grain interconnect structure 617, and/or the first functional grain 611a and the second functional grain 612a may include solder caps (or other solder structures) that can be reflowed to make connections. Such solder caps can be reflowed, for example, by quality reflow, thermocompression bonding (TCB), etc. In another exemplary embodiment, connections can be made by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without the use of solder. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, entitled "Transient Interface Gradient Bonding for Metal Bonds," filed December 8, 2015, and U.S. Patent Application No. 14/989,455, entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof," filed January 6, 2016, the entire contents of each of which are hereby incorporated by reference. The functional grain interconnect structure can be attached to the high interconnect structure 614 and the connecting grain interconnect structure 617 using any of the various techniques (e.g., quality reflow, thermo-press bonding (TCB), direct metal-to-metal intermetal bonding, conductive adhesive, etc.).

As shown in Example Embodiment 600F, a first interconnecting die 617 of the connecting die 616b is connected to a corresponding interconnecting structure of the first functional die 611a, and a second interconnecting die 617 of the connecting die 616b is connected to a corresponding interconnecting structure of the second functional die 612a. During connection, the connecting die 616b provides electrical connections between the various die interconnecting structures of the first functional die 611a and the second functional die 612a via the RD structure 298 of the connecting die 616b (e.g., as shown in Example 200B-4 of FIG. 2B-1).

In Example 600F shown in Figure 6F, the height of the high interconnect structure 614 may be, for example, equal to (or greater than) the combined height of the connecting die interconnect structure 217 and the support layer 290b of the connecting die 616b, as well as the adhesive or other components used to attach the connecting die 616b to the RD structure 646a.

Typically, block 545 may include attaching (or coupling or mounting) functional dies to a high interconnect structure and connecting die interconnect structures. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such attachments or the characteristics of any particular type of attachment structure.

Example method 500 may include underfilling of the functional grain at block 550. Block 550 may include performing such underfilling in any of various ways, and non-limiting examples thereof are provided herein. Block 550 may, for example, share any or all features with any underfilling discussed herein (e.g., with blocks 155 and/or 175 of example method 100 of FIG. 1, with blocks 355 and/or 375 of example method 300 of FIG. 3, etc.). Various example states of block 550 are presented in example 600G shown in FIG. 6G.

It should be noted that an underfill material can be applied between the functional grains 611a and 612a and the encapsulation material 651. In the case of using pre-applied underfill material (PUF), such PUF can be applied to the functional grains 611a and 612a, and/or to the top exposed ends of the encapsulation material 651 and/or the interconnect structures 614 and 617 before coupling the functional grains.

Following the attachment performed at block 545, block 550 may include forming an underfill material (e.g., capillary underfill, injected underfill, etc.). As shown in the example embodiment 600G of FIG. 6G, underfill material 661 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom surfaces of functional grains 611a and 612a (e.g., orientation as shown in FIG. 6G), and/or at least a portion (if not all) of the sides of functional grains 611a and 612a. Underfill material 661 may also, for example, cover most (or all) of the top surface of encapsulation material 651. Underfill material 661 may also, for example, surround the corresponding interconnect structures of functional grains 611a and 612a to which the high interconnect structure 614 and the connecting grain interconnect structure 617 are attached. In an example embodiment where the ends of the high interconnect structure 614 and/or the connecting grain interconnect structure 617 protrude from the encapsulation material 651, the bottom filler material 661 may also surround such protrusions.

It should be noted that in various implementations of instance method 500, the bottom fill performed at block 550 can be skipped. For example, the bottom fill of the functional grain can be performed at another block (e.g., at block 555, etc.). Or, for example, this type of bottom fill can be omitted entirely.

Typically, block 550 may include underfilling of functional grains. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill material.

Example method 500 may include an encapsulation at block 555. Block 555 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. For example, block 555 may share any or all features with other encapsulation blocks (or steps) discussed herein (e.g., with block 535, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, etc.).

Various instance forms of block 555 are presented in instance 600H shown in Figure 6H. For example, encapsulating material 652' (and/or its formation) may share any or all features with encapsulating material 226' (and/or its formation) of Figure 2E, encapsulating material 426 (and/or its formation) of Figure 4K, encapsulating material 651 (and/or its formation) of Figure 6D, etc.

Encapsulating material 652' covers the top surface of encapsulating material 651, covers the side surface of bottom filler 661, covers at least some (if not all) of the side surfaces of functional grains 611a and 612b, covers the top surface of functional grains 611a and 612b, etc.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226' in FIG. 2E, etc.), encapsulation material 652' need not initially be formed to cover the top surfaces of functional grains 611a and 612a. For example, block 555 may include encapsulation material 652' formed using film-assisted molding, sealing molding, etc.

Typically, block 555 may include an encapsulation. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 500 may include grinding (or otherwise thinning or planarizing) the encapsulating material at block 560. Block 560 may include performing such grinding (or any thinning or planarization process) in any of various ways, and non-limiting examples of this are provided herein. For example, block 560 may share any or all of the features with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of example method 100 of FIG. 1, with block 335 of example method 300 of FIG. 3, with block 540, etc.).

Various instances of block 560 are presented in example 600I shown in Figure 6I. The encapsulating material 652 (and/or its formation) of the example milled (or thinned or planarized, etc.) may share any or all features with encapsulating material 226 (and/or its formation) of Figure 2F, encapsulating material 426 (and/or its formation) of Figure 4F, encapsulating material 651 (and/or its formation) of Figure 6E, etc.

Block 560 may include, for example, a polished encapsulating material 652 and/or functional grains 611a and 612a, such that the top surface of the encapsulating material 652 is coplanar with the top surface of the functional grain 611a and/or with the top surface of the functional grain 612a.

Typically, block 560 may include milling (or otherwise thinning or planarizing) encapsulating material. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of performing such milling (or thinning or planarizing).

Example method 500 may include a removal carrier at block 565. Block 565 may include any removal carrier in various ways, and non-limiting examples are provided herein. For example, block 565 may share any or all features with any carrier removal process discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1, with blocks 345 and/or 360 of example method 300 of FIG. 3, etc.). Various example states of block 565 are shown in example 600J of FIG. 6J.

For example, Example 600J of FIG6J shows the removal of the first carrier 621a (e.g., compared to Example 600I of FIG6I). Block 565 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, or laser release, etc.). As another example, if an adhesive layer was used, for example, at block 520 during the formation of the RD structure 646a, then block 565 may include removing the adhesive layer.

It should be noted that in various embodiment schemes, such as those shown and discussed herein with respect to example methods 100 and 300 of Figures 1 and 3, a second carrier (e.g., coupled to encapsulation material 652 and/or coupled to functional grains 611a and 612a) may be utilized. In other embodiment schemes, various tooling structures may be used instead of a carrier.

Typically, block 565 may include a removal carrier. Therefore, the scope of this disclosure should not be limited by the characteristics of any particular method of removing a carrier or the characteristics of any particular type of carrier.

Example method 500 may include a completion signal redistribution (RD) structure at block 570. Block 570 may include any completion RD structure in various ways, and non-limiting examples of such structures are provided herein. Block 570 may share any or all features with, for example, block 520 (e.g., regarding the RD structure formation state of block 520). Various states of block 570 are illustrated in example 600K shown in Figure 6K.

As discussed in this paper, for example, regarding block 520, the carrier may have been (but not necessarily) received (or manufactured or prepared) only to form a portion of the desired RD structure. In such an instance scenario, block 570 may include completing the formation of the RD structure.

Referring to FIG6K, block 570 may include a second portion 646b of the RD structure formed on a first portion 646a of the RD structure (e.g., the first portion 646a of the RD structure has been received, manufactured, or prepared at block 520). Block 570 may, for example, include a second portion 646b of the RD structure formed in the same manner as the first portion 646a of the RD structure.

It should be noted that in various embodiments, the first portion 646a and the second portion 646b of the RD structure can be formed using different materials and/or different fabrication processes. For example, the first portion 646a of the RD structure can be formed using an inorganic dielectric layer, while the second portion 646b of the RD structure can be formed using an organic dielectric layer. As another example, the first portion 646a of the RD structure can be formed with a finer pitch (or finer traces, etc.), while the second portion 646b of the RD structure can be formed with a coarser pitch (or coarser traces, etc.). As yet another example, the first portion 646a of the RD structure can be formed using a back-to-office (BEOL) semiconductor wafer fabrication (fab) process, while the second portion 646b of the RD structure can be formed using a post-fab electronic device packaging process. Furthermore, the first part 646a and the second part 646b of the RD structure can be formed at different geographical locations.

Similar to the first part 646a of the RD structure, the second part 646b of the RD structure can have any number of dielectric layers and/or conductive layers.

As discussed herein, interconnect structures can be formed on RD structure 646b. In such an embodiment, block 565 may include forming under-bump metallization (UBM) on the exposed pad to enhance the formation (or attachment) of such interconnect structures.

Typically, block 570 may include a complete signal redistribution (RD) structure. Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which a signal redistribution structure is formed or the features of any particular type of signal distribution structure.

Example method 500 may include forming an interconnected structure on a redistributed structure at block 575. Block 575 may include forming an interconnected structure in any of a variety of ways, and non-limiting examples of such forms are provided herein. For example, block 575 may form an interconnected structure that shares any or all of the features discussed herein.

Various instance forms of block 575 are presented in instance 600L shown in Figure 6L. Instance interconnect structure 652 (e.g., package interconnect structure, etc.) may include features of any of the various interconnect structures. For example, package interconnect structure 652 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive posts, leads, etc.

Block 575 may include interconnection structure 652 formed in any of various ways. For example, interconnection structure 652 may be glued and/or printed on RD structure 646b (e.g., glued and/or printed to its corresponding pad 651 and/or UBM) and then reflowed. As another example, interconnection structure 652 (e.g., conductive ball, conductive bump, post, lead, etc.) may be pre-formed before attachment and then attached to RD structure 646b (e.g., attached to its corresponding pad 651) via, for example, reflow, electroplating, epoxy bonding, wire bonding, etc.

It should be noted that, as described above, the pad 651 of the RD structure 646b can be formed of under-bump metal (UBM) or any metallization to facilitate the formation of the interconnect structure 652 (e.g., construction, attachment, coupling, deposition, etc.). For example, such UBM formation can be performed at block 570 and/or block 575.

Typically, block 575 can be included in a redistributed structure to form an interconnected structure. Therefore, the scope of this disclosure should not be limited by any particular manner of forming such an interconnected structure or any particular feature of the interconnected structure.

Example method 500 may include a granular cut at block 580. Block 580 may include performing such a granular cut in any of various ways, of which non-limiting examples are discussed herein. Block 580 may, for example, share any or all features with any granular cut discussed herein (e.g., as discussed with respect to example method 100 of FIG. 1, as discussed with respect to example method 300 of FIG. 3, etc.).

Various instance forms of block 580 are presented in example 600M shown in Figure 6M. The monolithic cut structure (e.g., corresponding to encapsulation material portion 652a) may share any or all features with, for example, the monolithic cut structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b), and the monolithic cut structure of Figure 4L (e.g., corresponding to two encapsulation material portions 426a and 426b).

Typically, block 580 can include single-piece cuts. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of single-piece cutting.

Instance method 500 may include execution of continuation processing at block 590. Such continuation processing may include any of a variety of features, and non-limiting examples are provided herein. For example, block 590 may share any or all features with block 190 of instance method 100 of Figure 1, block 390 of instance method 300 of Figure 3, etc.

For example, block 590 may include returning the execution flow of instance method 500 to any of its blocks. As another example, block 590 may include directing the execution flow of instance method 500 to any other method block (or step) discussed herein (e.g., with respect to instance method 100 of Figure 1, instance method 300 of Figure 3, instance method 700 of Figure 7, etc.).

For example, as shown in Example 200O of FIG2O, Example 200P of FIG2P and Example 200Q of FIG2Q, block 590 may include forming an encapsulation material and/or a bottom filler (or skip forming an encapsulation material and/or a bottom filler).

As discussed herein, functional dies and interconnect dies can be mounted to a substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in Figures 9 and 10.

Figure 7 shows a flowchart of an example method 700 for manufacturing an electronic device according to various forms of the present disclosure. Example method 700 may share any or all features, for example, with any other example method discussed herein (e.g., example method 100 of Figure 1, example method 300 of Figure 3, example method 500 of Figure 5, etc.). Figures 8A-8N show cross-sectional views illustrating example electronic devices (e.g., semiconductor packages, etc.) and example methods for manufacturing example electronic devices according to various forms of the present disclosure. Figures 8A-8N may illustrate example electronic devices, for example, in the blocks (or steps) of method 700 of Figure 7. Figures 7 and 8A-8N will now be discussed together. It should be noted that the order of the instance blocks in method 700 can be changed without departing from the scope of this disclosure. In the example implementation, method 700 of Figure 7 can be considered similar to the method of Figure 5, but with the addition of block 742 for forming the second distribution structure.

Example method 700 may begin execution at block 705. Method 700 may begin execution in response to any of a variety of causes or conditions, and non-limiting examples are provided herein. For example, method 700 may begin automatic execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, etc. As another example, method 700 may begin execution in response to an operator command. Additionally, for example, method 700 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 700 may include receiving, manufacturing, and/or preparing multiple functional dies at block 710. Block 710 may include receiving, manufacturing, and/or preparing multiple functional dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 710 may share any or all features with block 510 of example method 500 shown in FIG. 5 and discussed herein, and with block 310 of example method 300 shown in FIG. 3 and discussed herein, etc. Various forms of block 710 are presented in examples 400A-1 to 400A-4 shown in FIG. 4A. It should be noted that block 710 may also share any or all features, for example, with block 110 of example method 100 shown in FIG. 1 and discussed herein.

Functional dies 811a and 812a (and/or their formations) shown in many figures in Figures 8A-8N may share any or all features with functional dies 611a and 612a (and/or their formations), functional dies 411 and 412 (and/or their formations), functional dies 211 and 212 (and/or their formations), etc. For example, but not limited to, functional dies 811a and 812a may include features of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Typically, block 710 may include receiving, manufacturing, and/or preparing multiple functional dies. Therefore, the scope of this disclosure should not be limited to any particular mode of performing such receiving and/or manufacturing, nor to any particular feature of such functional dies.

Example method 700 may include receiving, manufacturing, and/or preparing interconnect dies at block 715. Block 715 may include receiving, manufacturing, and/or preparing multiple interconnect dies in any of various ways, and non-limiting examples thereof are provided herein. For example, block 715 may share any or all features with block 115 of example method 100 shown in FIG. 1 and discussed herein. Various example states of block 715 are presented in examples 200B-1 and 200B-7 shown in FIG. 2B-1 to 2B-2. It should be noted that block 715 may also share any or all features, for example, with block 315 of example method 100 shown in FIG. 3 and discussed herein, and with block 515 of example method 500 shown in FIG. 5, etc.

The interconnecting grains 816b and interconnecting grain interconnects 817 (and/or their formation) shown in many of the figures in Figures 8A-8N may share any or all of the features, for example, with the interconnecting grains 216b and interconnecting grain interconnects 217 (and/or their formation) of Figures 2B-1 to 2B-2.

It should be noted that the interconnecting grain interconnect structure 817 (and/or its formation) may, for example, share any or all features with the first grain interconnect structure 213 (and/or its formation). For example, in an exemplary embodiment, instead of forming a first grain interconnect structure such as the first grain interconnect structure 213 of FIG. 2A on the functional grains 211/212, the same or similar interconnecting grain interconnect structure 817 may be formed on the interconnecting grain 816b.

Typically, block 715 may include receiving, manufacturing, and/or preparing interconnecting dies. Therefore, the scope of this disclosure should not be limited to any particular feature of such receiving, manufacturing, and/or preparing or any particular feature of such interconnecting dies.

Example method 700 may include at block 720 a carrier having a signal redistribution (RD) structure (or distribution structure) thereon. Block 720 may include performing such receiving, manufacturing and/or preparation in any of various ways, and non-limiting examples thereof are provided herein.

Block 720 may share any or all features with any or all carriers that are received, manufactured, and/or prepared (e.g., block 120 for example method 100 of Figure 1, block 320 for example method 300 of Figure 3, block 520 for example method 500 of Figure 5, etc.). Various instance forms of block 720 are provided in example 800A of Figure 8A.

As discussed herein, any or all carriers discussed herein may include, for example, only bulk materials (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal redistribution (RD) structures on (or instead of bulk materials). Block 720 provides examples of receiving, manufacturing, and/or preparing such carriers.

Block 720 may include an RD structure 846a formed on a block carrier 821a in any of various ways, of which non-limiting examples are presented herein. In exemplary embodiments, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to a vertical interconnect structure 814 (formed laterally), which will ultimately connect to a second distribution structure 896 and/or functional dies 811 and 812 (connected laterally). Thus, the RD structure 846a may be coreless. However, it should be noted that in various alternative embodiments, the RD structure 846a may be a cored structure.

Figure 8A illustrates an example in which the RD structure 846a includes three dielectric layers 847 and three conductive layers 848. This number of layers is merely an example, and the scope of this disclosure is not limited thereto. In another embodiment, the RD structure 846a may include only a single dielectric layer 847 and a single conductive layer 848, two dielectric layers and two conductive layers, etc. The example redistribution (RD) structure 846a is formed on a bulk carrier material 821a.

The dielectric layer 847 can be formed from any of the various materials (e.g., _Si3N4 , _SiO2 , _SiON , PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 847 can be formed using any of the various processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 847 can be patterned, for example, to expose various surfaces (e.g., exposing the lower traces or pads of the conductive layer 848).

The conductive layer 848 can be formed from any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 848 can be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 846a may include, for example, conductors exposed at its outer surface (e.g., at the top surface of example 800A). Such exposed conductors may be used, for example, for attaching (or forming) grain interconnect structures (e.g., at block 725, etc.). In such embodiments, the exposed conductors may include pads and may include, for example, under-bump metal (UBM) formed thereon to enhance the attachment (or formation) of the grain interconnect structures. Such under-bump metal may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

Examples of redistribution structures and/or their formation are provided in U.S. Patent Application No. 14/823,689, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”, filed August 11, 2015; and in U.S. Patent Application No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; each of the above applications is hereby incorporated herein by reference in its entirety.

The redistribution structure 846a may, for example, perform fan-out redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to be formed) vertical interconnect structure 814 to locations outside the coverage areas of functional dies 811 and 812 to be attached via such vertical interconnect structure 814. Alternatively, the redistribution structure 846a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the (to be formed) vertical interconnect structure 814 to locations within the coverage areas of the (to be connected) connecting die 816b and/or to locations within the coverage areas of the (to be connected) functional dies 811 and 812. The redistribution structure 846a can also provide, for example, connectivity between various signals between functional dies 811 and 812 (e.g., in addition to the connectivity provided by the connecting die 816b).

In various implementation schemes, block 720 may include a first portion 846a that forms only the entire RD structure 846, wherein a second portion 846b of the entire RD structure 846 may be formed later (e.g., at block 770).

Typically, block 720 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure thereon. Therefore, the scope of this disclosure should not be limited to any particular manner of manufacturing such a carrier and/or signal redistribution structure or any particular feature of such a carrier and/or signal redistribution structure.

Example method 700 may include forming a vertical interconnect structure on the RD structure (e.g., as provided at block 720) at block 725. Block 725 may include forming a vertical interconnect structure on the RD structure in any of various ways, and non-limiting examples thereof are provided herein. It should be noted that the vertical interconnect structure may also be referred to herein as a high bump, high pillar, high strut, grain interconnect structure, functional grain interconnect structure, etc.

Block 725 may share any or all features (e.g., second grain interconnection formation features, etc.) with any or all functional grain receiving, manufacturing and/or preparation discussed herein (e.g., the formation of block 110 and second grain interconnection structure 214 and/or first grain interconnection structure 213 in respect of example method 100 of FIG1, the formation of block 347 and second grain interconnection structure 414 in respect of example method 347 of FIG3, block 525 in respect of example method 500 of FIG5, etc.).

Various instances of block 725 are provided in example 800B of Figure 8B. The vertical interconnect structure 814 (and/or its formation) may share any or all features with the second grain interconnect structure 214 (and/or its formation) of Figure 2A and/or with the second grain interconnect structure 414 (and/or its formation) of Figure 4H-2. Additionally, the vertical interconnect structure 814 (and/or its formation) may share any or all features with the interconnect structure 614 (and/or its formation) of Figure 6B.

Typically, block 725 may include a vertical interconnection formed on an RD structure (e.g., as provided at block 720). Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which such a vertical interconnection is formed and/or the features of any particular type of vertical interconnection.

Example method 700 may include mounting a connection die to the RD structure at block 730 (e.g., as provided at block 720). Block 730 may include performing such mounting (or attachment or coupling) in any of various ways, and non-limiting examples of this are provided herein. Block 730 may, for example, share any or all features with any die attachment discussed herein (e.g., block 530 of example method 500 shown in FIG. 5 and discussed herein, block 325 of example method 300 shown in FIG. 3 and discussed herein, block 125 of example method 100 shown in FIG. 1 and discussed herein, etc.). Various example forms of block 730 are presented in example 800C shown in FIG. 8C.

Block 730 may, for example, include attaching the back side of the connecting die 816b to the RD structure 846a using a die-attach adhesive (e.g., tape, liquid, paste, etc.). Although a dielectric layer coupling the connecting die 816b to the RD structure 846a is shown in FIG8C, in other embodiments, the back side of the connecting die 816b may be coupled to a conductive layer (e.g., to enhance heat dissipation, provide additional structural support, etc.).

Additionally, as discussed herein, any interconnecting die discussed herein can be double-sided. In such example embodiments, the back-side interconnect can be electrically connected to the corresponding interconnect of the RD structure 846a (e.g., pads, interconnecting pads, bumps, etc.).

Typically, block 730 may include mounting a connector die to the RD structure (e.g., as provided at block 720). Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which the connector die is mounted.

Example method 700 may include an encapsulation at block 735. Block 735 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. For example, block 735 may share any or all of the features with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, with block 530 of example method 500 of FIG. 5, etc.). Various example states of block 735 are shown in FIG. 8D.

Block 735 may include, for example, performing wafer (or panel) level molding processes. As discussed herein, any or all of the process steps discussed herein can be performed at the panel or wafer level prior to the individual modules being diced. Referring to the example embodiment 800D shown in Figure 8D, encapsulation material 851' may cover at least part (or all) of the top surface of RD structure 846a, vertical interconnect structure 814, die interconnect structure 817, top surface (or active surface or front surface) of die 816b, and side surface of die 816b.

Although the encapsulating material 851' (as shown in FIG. 8D) is shown to cover the top ends of the vertical interconnect structure 814 and the connecting grain interconnect structure 817, any or all of these ends may be exposed from the encapsulating material 851' (as shown in FIG. 8E). Block 735 may, for example, include initially forming the encapsulating material 851' with the top ends of various interconnects exposed or protruding (e.g., using film-assisted molding, grain sealing molding, etc.). Alternatively, block 735 may include forming the encapsulating material 851' followed by a thinning (or planarization or grinding) process (e.g., performed at block 740) to thin the encapsulating material 851' sufficiently to expose the top surfaces of any or all of the vertical interconnect structure 814 and the connecting grain interconnect structure 817, etc.

Typically, block 735 may include an encapsulation. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such encapsulation or the characteristics of any particular type of encapsulation material or its configuration.

Example method 700 may include a grinding encapsulating material and/or various interconnections at block 740. Block 740 may include performing such grinding (or any thinning or planarization) in any of various ways, and non-limiting examples of this are provided herein. Various example forms of block 740 are presented in example 800E shown in Figure 8E. Block 740 may, for example, share any or all of the features with other grinding (or thinning or planarization) blocks (or steps) discussed herein.

As discussed herein, in various embodiment schemes, the encapsulation material 851' may initially be formed to a thickness greater than the final required thickness, and/or the vertical interconnect structure 814 and the interconnect grain interconnect structure 817 may initially be formed to a thickness greater than the final required thickness. In such embodiment schemes, block 740 may be executed to grind (or otherwise thin or planarize) the encapsulation material 851', the vertical interconnect structure 814, and/or the interconnect grain interconnect structure 817. In embodiment 800E shown in FIG8E, the encapsulation material 851, the vertical interconnect structure 814, and/or the interconnect grain interconnect structure 817 have been ground to produce the encapsulation material 851, the vertical interconnect structure 814, and the interconnect grain interconnect structure 817 (as shown in FIG8E). The top surfaces of the milled encapsulating material 851, the top surfaces of the vertical interconnect structure 814, and/or the top surfaces of the connecting grain interconnect structure 817 may, for example, be coplanar.

It should be noted that in various implementation schemes, such as by using chemical or mechanical processes that make the encapsulation material 851 thinner than the vertical interconnect structure 814 and/or the connecting grain interconnect structure 817, or by using film-assisted and/or sealing molding processes at block 735, the top surface of the vertical interconnect structure 814 and/or the top surface of the connecting grain interconnect structure 817 may protrude from the top surface of the encapsulation material 851.

Typically, block 740 may include milled (or thinned or planarized) encapsulating material and/or various interconnect structures. Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which such milling (or thinning or planarization) is performed.

Example method 700 may include forming a second signal redistribution (RD) structure (or distribution structure) at block 742. Block 742 may include performing such formation in any of a variety of ways, and non-limiting examples of this are provided herein.

Block 742 may share any or all features with any or all signal distribution structures discussed herein (e.g., block 120 for instance method 100 of Figure 1, block 320 for instance method 300 of Figure 3, block 520 for instance method 500 of Figure 5, block 720, etc.). Various instance forms of block 742 are provided in instance 800F of Figure 8F.

As discussed herein, the example structure 800E generated by block 740 may include a top surface, which includes the top surface of encapsulating material 851, exposed top surfaces of vertical interconnects 814 and/or connecting grain interconnects 817, exposed top side surfaces of vertical interconnects 814 and/or connecting grain interconnects 817, etc. Block 742 may, for example, include forming a second signal redistribution structure on any or all of these surfaces.

Block 742 may include a second RD structure formed on top of structure 800E in any of various ways, such as in a non-limiting example. In exemplary embodiments, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections between vertical interconnect structures 814 and/or connecting die interconnect structures 817 laterally and/or vertically to electrical components mounted therein (e.g., semiconductor dies, passive electrical components, shielding components, etc., distributed to, for example, dies 811 and 812). Figure 8F shows an example in which the second RD structure 896 includes three dielectric layers 897 and three conductive layers 898. This number of layers is merely an example, and the scope of this disclosure is not limited thereto. In another embodiment, the second RD structure 896 may consist of only a single dielectric layer 897 and a single conductive layer 898, two dielectric layers and two conductive layers, etc. Therefore, the second RD structure 896 may be coreless. However, it should be noted that in various alternative embodiments, the second RD structure 896 may be a cored structure. In another embodiment, the second distribution (or distribution) structure 896 may consist of only a single vertical metal structure (e.g., one or more layers), such as a bump-under metallization structure.

The dielectric layer 897 can be formed from any of the following materials (e.g., Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy resin, or other insulating materials). The dielectric layer 897 can be formed using any of the following processes (e.g., PVD, CVD, printing, spin coating, spraying, sintering, thermal oxidation, etc.). The dielectric layer 897 can be patterned, for example, to expose various surfaces (e.g., exposing the lower traces or pads of the conductive layer 898).

The conductive layer 898 can be formed from any of various materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 898 can be formed using any of various processes (e.g., electrolytic electroplating, electroless electroplating, CVD, PVD, etc.).

The second RD structure 896 may, for example, include conductors exposed at its outer surface (e.g., at the top surface of example 800F). Such exposed conductors may be used, for example, for the attachment (or formation) of electrical components and/or their attachment structures (e.g., at block 745, etc.). Such exposed conductors may, for example, include pad structures, under-bump metallization structures, etc. In such embodiments, the exposed conductors may include pads and may, for example, include under-bump metallization (UBM) formed thereon to enhance the attachment (or formation) of components and/or their interconnection structures. Such under-bump metallization may, for example, include one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

Examples of redistribution structures and/or their formation are provided in U.S. Patent Application No. 14/823,689, entitled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”, filed August 11, 2015; and in U.S. Patent Application No. 8,362,612, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; each of the above applications is hereby incorporated herein by reference in its entirety.

The second RD structure 896 may, for example, perform at least some fan-out redistribution of electrical connections or signals, moving the electrical connections or signals laterally from at least a portion of the interconnect structure 817 and/or the vertical interconnect structure 814 (attached to the bottom surface of the second RD structure 896) to a location outside the coverage area of the interconnect structure 817 (or interconnect 816b) and/or the vertical interconnect structure 814. Alternatively, the second RD structure 896 may perform at least some fan-in redistribution of electrical connections or signals, moving the electrical connections or signals laterally from at least a portion of the interconnect structure 817 and/or the vertical interconnect structure 814 to a location inside the coverage area of the interconnect structure 817 (or interconnect 816b) and/or the vertical interconnect structure 814. The second RD structure 896 can also provide, for example, connectivity between functional dies 811 and 812 for various signals (e.g., in addition to the connectivity provided by the connecting die 816b, in addition to the connectivity provided by the RD structure 846a, etc.).

Although instance block 742 is described as forming the second RD structure layer by layer, it should be noted that the second RD structure can be received in a pre-formed format and then attached to block 742 (e.g., by welding, gluing with epoxy resin, etc.).

Typically, block 742 may include a second redistribution (RD) structure. Therefore, the scope of this disclosure should not be limited by any particular manner of manufacturing such carriers and/or signal redistribution structures or any particular feature of such carriers and/or signal redistribution structures.

Example method 700 may include attaching (or coupling or mounting) a functional die to a second distribution (RD) structure (e.g., as formed at block 742) at block 745. Block 745 may include performing such attachment in any of various ways, and non-limiting examples of this are provided herein. Block 745 may, for example, share any or all of the features with any die attachment process discussed herein. Various example states of block 745 are presented in example 800G shown in Figure 8G.

For example, the grain interconnect structure of the first functional grain 811a (e.g., pads, bumps, etc.) can be mechanically and electrically connected to the corresponding conductors of the second RD structure 896 (e.g., pads, under-bump metal, exposed traces, etc.). For example, the grain interconnect structure of the first functional grain 811a can be electrically connected to the corresponding vertical interconnect structure 814 and/or electrically connected to the corresponding connecting grain interconnect structure 817 via the conductors of the second RD structure 896. Similarly, the grain interconnect structure of the second functional grain 812a (e.g., pads, bumps, etc.) can be mechanically and electrically connected to the corresponding conductors of the second RD structure 896 (e.g., pads, under-bump metal, exposed traces, etc.). For example, the grain interconnection structure of the second functional grain 812a can be electrically connected to the corresponding vertical interconnection structure 814 and/or electrically connected to the corresponding connecting grain interconnection structure 817 through the conductor of the second RD structure 896.

Such interconnection structures of functional grains can be connected in any of a variety of ways. For example, connections can be performed by soldering. In an exemplary embodiment, the interconnection structure of functional grains 811a and 812a may include a solder cap (or other solder structure) that can be reflowed by quality reflow, thermo-press bonding (TCB), etc. Similarly, the under-mask metal of the second RD structure 896 may already have (e.g., at block 742) a solder cap (or other solder structure) that can be reflowed by quality reflow, thermo-press bonding (TCB), etc. In another exemplary embodiment, connections can be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without the use of solder and/or by utilizing one or more intermediate non-solder metal layers. Examples of such connections are provided in U.S. Patent Application No. 14/963,037, entitled "Transient Interface Gradient Bonding for Metal Bonds," filed December 8, 2015, and U.S. Patent Application No. 14/989,455, entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof," filed January 6, 2016, the entire contents of each of which are hereby incorporated by reference. The functional grain interconnect structure can be attached to the second RD structure 896 using any of a variety of techniques (e.g., quality reflow, thermo-press bonding (TCB), direct metal-to-metal intermetal bonding, conductive adhesive, etc.).

As shown in Example Embodiment 800G, the first interconnecting die 817 of the connecting die 816b is connected to the corresponding interconnecting structure of the first functional die 811a via the second RD structure 896, and the second interconnecting die 817 of the connecting die 816b is connected to the corresponding interconnecting structure of the second functional die 812a via the second RD structure 896. During connection, the connecting die 816b (e.g., combined with the second RD structure 896) provides electrical connection between the various die interconnecting structures of the first functional die 811a and the second functional die 812a via the RD structure 298 of the connecting die 816b (e.g., as shown in Example 200B-4 of FIG. 2B-1).

In Example 800G shown in FIG8F, the height of the vertical interconnect structure 814 may, for example, be equal to (or greater than) the combined height of the support layer 290b of the connecting die interconnect structure 217 and the connecting die 816b, and the adhesive or other components used to attach the connecting die 816b to the RD structure 846a. Therefore, the second RD structure 896 may, for example, include a generally planar lower surface, a generally uniform thickness, and a generally planar upper surface.

Typically, block 745 may include attaching (or coupling or mounting) a functional die to a second RD structure. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such attachment or the characteristics of any particular type of attachment structure.

Example method 700 may include underfilling of the functional grain at block 750. Block 750 may include performing such underfilling in any of a variety of ways, of which non-limiting examples are provided herein. Block 750 may share any or all features with any underfilling discussed herein, for example (e.g., with blocks 155 and/or 175 of example method 100 of FIG. 1, with blocks 355 and/or 375 of example method 300 of FIG. 3, with block 550 of example method 500 of FIG. 5, etc.). Various example states of block 750 are presented in example 800H shown in FIG. 8H.

It should be noted that an underfill material can be applied between the functional dies 811a and 812a and the second RD structure 896. In the case of using a pre-applied underfill material (PUF), such a PUF can be applied to the functional dies 811a and 812a before coupling the functional dies 811a and 812a, and/or to the second RD structure 896 and/or the top exposed conductors of the second RD structure 896 (e.g., pads, under-bump metallization, exposed traces, etc.).

Following the attachment performed at block 745, block 750 may include forming an underfill material (e.g., capillary underfill, injected underfill, etc.). As shown in the exemplary embodiment 800H of FIG8H, the underfill material 861 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom surfaces of functional grains 811a and 812a (e.g., orientation as shown in FIG8H), and/or at least a portion (if not all) of the side surfaces of functional grains 811a and 812a. The underfill material 861 may also, for example, cover most (or all) of the top surface of the second RD structure 896. The bottom filler material 861 may also surround, for example, the corresponding interconnection structures (e.g., pads, bumps, etc.) of the functional grains 811a and 812a to which the corresponding interconnection structures (e.g., pads, connecting pads, traces, under-bump metallization, etc.) of the second RD structure 896 are attached. In an example embodiment where the ends of the interconnection structures of the second RD structure 896 protrude from the top surface of the second RD structure 896 (e.g., the surface of the top dielectric layer), the bottom filler material 861 may also surround such protrusions.

It should be noted that in various implementations of instance method 700, the bottom fill performed at block 750 can be skipped. For example, the bottom fill of the functional grain can be performed at another block (e.g., at block 755, etc.). Or, for example, this type of bottom fill can be omitted entirely.

Typically, block 750 may include underfill for functional grains. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing this type of underfill or the characteristics of any particular type of underfill material.

Example method 700 may include an encapsulation at block 755. Block 755 may include any of the various ways in which such an encapsulation is performed, and non-limiting examples of this are provided herein. For example, block 755 may share any or all features with other encapsulation blocks (or steps) discussed herein (e.g., with block 735, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, with blocks 535 and 555 of example method 500 of FIG. 5, etc.).

Various instance forms of block 755 are presented in example 800I shown in Figure 8I. For example, encapsulating material 852’ (and/or its formation) may share any or all features with encapsulating material 226’ (and/or its formation) of Figure 2E, encapsulating material 426 (and/or its formation) of Figure 4K, encapsulating materials 651 and 652’ (and/or their formations) of Figures 6D and 6H, encapsulating material 851 of Figure 8E, etc.

Encapsulating material 852' covers the top surface of the second RD structure 896, covers the side surfaces of the underfill 861, covers the top surface of the underfill 861 (e.g., between grains 811a and 812a), covers at least some (if not all) of the side surfaces of the functional grains 811a and 812a, covers the top surface of the functional grains 811a and 812a, etc. In other embodiments, encapsulating material 852' may replace the underfill 861, thus providing underfill between the functional grains 811a and/or 812a and the second RD structure 896.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226' in FIG. 2E, etc.), encapsulation material 852' need not initially be formed to cover the top surfaces of functional grains 811a and 812a. For example, block 755 may include encapsulation material 852' formed using film-assisted molding, sealing molding, etc.

Typically, block 755 may include an encapsulation. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, etc.

Example method 700 may include grinding (or otherwise thinning or planarizing) the encapsulating material at block 760. Block 760 may include performing such grinding (or any thinning or planarization process) in any of various ways, and non-limiting examples of this are provided herein. For example, block 760 may share any or all of the features with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of example method 100 of FIG. 1, with block 335 of example method 300 of FIG. 3, with blocks 540 and 555 of example method 500 of FIG. 5, with block 735, etc.).

Various instances of block 760 are presented in example 800J shown in Figure 8J. The encapsulating material 852 (and/or its formation) of the example milled (or thinned or planarized, etc.) may share any or all features with encapsulating material 226 (and/or its formation) of Figure 2F, encapsulating material 426 (and/or its formation) of Figure 4F, encapsulating materials 651 and 652 (and/or their formation) of Figures 6E and 6I, encapsulating material 851, etc.

The block 760 may include, for example, a polished encapsulating material 852 and/or functional grains 811a and 812a, such that the top surface of the encapsulating material 852 is coplanar with the top surface of the functional grain 811a and/or with the top surface of the functional grain 812a.

Typically, block 760 may include milled (or otherwise thinned or planarized) encapsulating material. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of performing such milling (or thinning or planarization).

Example method 700 may include a removal carrier at block 765. Block 765 may include any removal carrier in various ways, and non-limiting examples of this are provided herein. For example, block 765 may share any or all features with any carrier removal process discussed herein (e.g., with blocks 145 and/or 160 of example method 100 of FIG. 1, with blocks 345 and/or 360 of example method 300 of FIG. 3, with block 565 of example method 500 of FIG. 5, etc.). Various example states of block 765 are shown in example 800K of FIG. 8K.

For example, Example 800K of Figure 8K shows the removal of the first carrier 821a (e.g., compared to Example 800J of Figure 8J). Block 765 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, or laser release, etc.). Again, for example, if an adhesive layer was utilized, for example, at block 720 during the formation of the RD structure 846a, then block 765 may include removing the adhesive layer.

It should be noted that in various embodiment schemes, such as those shown and discussed herein with respect to example methods 100 and 300 of Figures 1 and 3, a second carrier (e.g., coupled to encapsulation material 852 and/or coupled to functional grains 811a and 812a) may be utilized. In other embodiment schemes, various tooling structures may be used instead of a carrier.

Typically, block 765 may include a removal carrier. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of removing carriers or the characteristics of any particular type of carrier.

Example method 700 may include a complete signal redistribution (RD) structure at block 770 (e.g., if the RD structure 846a is not fully formed at block 820). Block 770 may include any complete RD structure in various ways, and non-limiting examples thereof are provided herein. Block 770 may share any or all features with block 720, for example (e.g., with respect to the RD structure formation pattern of block 720). Various patterns of block 770 are presented in example 800L shown in Figure 8L.

As discussed in this paper, for example, with respect to block 720, the carrier may have been (but not necessarily) received (or manufactured or prepared) only to form a portion of the desired RD structure. In such an instance scenario, block 770 may include completing the formation of the RD structure.

Referring to Figure 8L, block 770 may include a second portion 846b of the RD structure formed on a first portion 846a of the RD structure (e.g., the first portion 846a of the RD structure has been received, manufactured, or prepared at block 720). Block 770 may, for example, include a second portion 846b of the RD structure formed in the same manner as the first portion 846a of the RD structure.

It should be noted that in various embodiments, the first portion 846a and the second portion 846b of the RD structure can be formed using different materials and/or different fabrication processes. For example, the first portion 846a of the RD structure can be formed using an inorganic dielectric layer, while the second portion 846b of the RD structure can be formed using an organic dielectric layer. As another example, the first portion 846a of the RD structure can be formed with a finer pitch (or finer traces, etc.), while the second portion 846b of the RD structure can be formed with a coarser pitch (or coarser traces, etc.). As yet another example, the first portion 846a of the RD structure can be formed using a back-end semiconductor wafer fabrication (fab) process, while the second portion 846b of the RD structure can be formed using a post-fab electronic device packaging process. In addition, the first part 846a and the second part 846b of the RD structure can be formed at different geographical locations.

Similar to the first part 846a of the RD structure, the second part 846b of the RD structure can have any number of dielectric layers and/or conductive layers.

As discussed in this paper, interconnect structures can be formed on RD structure 846b. In such an embodiment, block 765 may include forming under-bump metallization (UBM) on the exposed pad to enhance the formation (or attachment) of such interconnect structures.

Typically, block 770 may include a complete signal redistribution (RD) structure. Therefore, the scope of this disclosure should not be limited to the features of any particular manner in which a signal redistribution structure is formed or the features of any particular type of signal distribution structure.

Example method 700 may include forming an interconnected structure on a redistributed structure at block 775. Block 775 may include forming an interconnected structure in any of a variety of ways, and non-limiting examples of such forms are provided herein. For example, block 775 may form an interconnected structure that shares any or all of the features discussed herein.

Various instance forms of block 775 are presented in instance 800M shown in Figure 8M. Instance interconnect structure 852 (e.g., package interconnect structure, etc.) may include features of any of the various interconnect structures. For example, package interconnect structure 852 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive posts, leads, etc.

Block 775 may include interconnect structures 852 formed in any of various ways. For example, interconnect structures 852 may be glued and/or printed onto RD structure 846b (e.g., glued and/or printed to its corresponding pads 851 and/or UBM) and then reflowed. As another example, interconnect structures 852 (e.g., conductive balls, conductive bumps, posts, leads, etc.) may be pre-formed before attachment and then attached to RD structure 846b (e.g., to its corresponding pads 851) via, for example, reflow, electroplating, epoxy, wire bonding, etc.

It should be noted that, as described above, the pad 851 of the RD structure 846b can be formed of under-bump metal (UBM) or any metallization to facilitate the formation of the interconnect structure 852 (e.g., construction, attachment, coupling, deposition, etc.). For example, such UBM formation can be performed at block 770 and/or block 775.

Typically, block 775 can be included in a redistributed structure to form an interconnected structure. Therefore, the scope of this disclosure should not be limited by any particular manner of forming such an interconnected structure or any particular feature of the interconnected structure.

Example method 700 may include a granular cut at block 780. Block 780 may include performing such a granular cut in any of various ways, of which non-limiting examples are discussed herein. Block 780 may, for example, share any or all features with any granular cut discussed herein (e.g., as discussed with respect to example method 100 of FIG. 1, as discussed with respect to example method 300 of FIG. 3, as discussed with respect to example method 500 of FIG. 5, etc.).

Various instances of block 780 are presented in example 800N shown in Figure 8N. The monolithic cut structure (e.g., corresponding to encapsulation material portion 852a) may share any or all features with, for example, the monolithic cut structure of Figure 2L (e.g., corresponding to two encapsulation material portions 226a and 226b), the monolithic cut structure of Figure 4L (e.g., corresponding to two encapsulation material portions 426a and 426b), and the monolithic cut structure of Figure 6M 600M.

Typically, a block 780 may include cuts. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of cut.

Instance method 700 may include execution of continuation processing at block 790. Such continuation processing may include any of a variety of features, and non-limiting examples are provided herein. For example, block 790 may share any or all features with block 190 of instance method 100 of Figure 1, block 390 of instance method 300 of Figure 3, block 590 of instance method 500 of Figure 5, etc.

For example, block 790 may include returning the execution flow of instance method 700 to any of its blocks. As another example, block 790 may include directing the execution flow of instance method 700 to any other method block (or step) discussed herein (e.g., with respect to instance method 100 of Figure 1, instance method 300 of Figure 3, instance method 500 of Figure 5, etc.).

For example, as shown in Example 200O of FIG2O, Example 200P of FIG2P and Example 200Q of FIG2Q, block 790 may include forming encapsulation material and/or bottom filler (or skip forming encapsulation material and/or bottom filler).

As discussed herein, functional dies and interconnect dies can be mounted to a substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in Figures 9 and 10.

Figure 9 shows a top view of an example electronic device 900 according to various forms of this disclosure. The example electronic device 900 may, for example, share any or all features with any or all electronic devices discussed herein. For example, functional chips 911 and 912 may share any or all features with any or all functional chips (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, etc.) discussed herein. As another example, interconnect chip 916 may share any or all features with any or all interconnect chips (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, etc.) discussed herein. Additionally, for example, substrate 930 may share any or all features with any or all substrates and/or RD structures (288, 488, 646, 846, 896, etc.) discussed herein.

Figure 10 shows a top view of an example electronic device of various forms according to this disclosure. Example electronic device 1000 may, for example, share any or all features with any or all electronic devices discussed herein. For example, functional dies (functional dies 1 to functional dies 10) may share any or all features with any or all functional dies discussed herein (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, 911, 912, etc.). For example, interconnect dies (interconnect dies 1 to interconnect dies 10) may share any or all features with any or all interconnect dies (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, 916, etc.) discussed herein. Additionally, for example, substrate 1030 may share any or all features with any or all substrates and/or RD structures (288, 488, 646, 846, 896, 930, etc.) discussed herein.

Although the illustrations discussed herein typically include interconnecting dies between two functional dies, the scope of this disclosure is not limited thereto. For example, as shown in Figure 10, interconnecting die 9 is connected to three functional dies (e.g., functional die 2, functional die 9, and functional die 10), for example, by electrically connecting each of these functional dies to each other. Thus, a single interconnecting die can couple multiple functional dies (e.g., two functional dies, three functional dies, four functional dies, etc.).

Furthermore, although the illustrations discussed herein typically include functional dies connected to only one interconnect die, the scope of this disclosure is not limited thereto. For example, a single functional die may be connected to two or more interconnect dies. For instance, as shown in Figure 10, functional die 1 is connected to many other functional dies via many corresponding interconnect dies.

The discussion herein includes numerous illustrative figures illustrating various parts of a semiconductor device assembly (or package) and/or its manufacturing process. For clarity, these figures do not show all configurations of each example assembly. Any example assembly presented herein may share any or all features with any or all other assemblies presented herein.

In summary, various embodiments of this disclosure provide a semiconductor packaging structure and a method for manufacturing a semiconductor package. As a non-limiting example, various embodiments of this disclosure provide various semiconductor packaging structures and methods for manufacturing them, said semiconductor packaging structures including interconnecting dies that transmit electrical signals between a plurality of other semiconductor dies along a specific route. Although the foregoing has been described with reference to certain embodiments and examples, those skilled in the art will understand that various changes and equivalents can be made without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt specific conditions or materials to the teachings of this invention without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the specific instances disclosed, but rather that it will include all instances falling within the scope of the appended claims.

100: Example Method / Method 105: Block 110: Block 115: Block 120: Block 125: Block 130: Block 135: Block 140: Block 145: Block 150: Block 155: Block 160: Block 165: Block 170: Block 175: Block 190: Block 200A-1: Example 200A-2: Example 200A-3: Example / Example Wafer 200A-4: Example 200B-1: Example / Wafer 200B-2: Example 200B-3: Example 200B-4: Example 200B-5: Example 200B-6: Example 200B-7: Example 200C: Example 200D: Example 200E: Example 200F: Example 200G: Example 200H: Example 200I: Example 200J: Example 200K: Example 200L: Example 200M: Example 200N: Example 200O: Example / Example Implementation Scheme 200P: Example / Example Implementation Scheme 200Q: Example / Example Implementation Scheme 201: Functional Grain 202: Functional Grain 203: Functional Grain 204: Functional Grain 211: Example Grain / Functional Grain / First Functional Grain / First Grain 212: Example Grain / Functional Grain / Second Functional Grain / Second Grain 213: Grain Interconnection Structure / First Grain Interconnection Structure 214: Grain Interconnection Structure / Second Grain Interconnection Structure 216a: Example Connecting Grain / Connecting Grain 216b: Thin Connecting Grain / Connecting Grain 216c: Connecting Grain 217: Connecting Grain Interconnection Structure 217b: Connecting Grain Interconnection Structure 221: Carrier 223: Adhesive Material / Adhesive Layer / Underfill 224: Underfill 225: Encapsulation Material 226: Encapsulation Material 226’: Encapsulation Material 226a: Encapsulation Material Portion 226b: Encapsulation Material Portion 231: Second Carrier 288: Substrate 290: Support Layer 290a: Support Layer 290b: Support Layer 291: Base Dielectric Layer 291b: Base Dielectric Layer 292: First Conductive Trajectory 292b: First Conductive Trajectory 293: First Dielectric Layer 293b: First Dielectric Layer 294: Conductive Via 294b: Conductive Via 295: Second Conductive Trajectory 295b: Second Conductive Trajectory 296: Second Dielectric Layer 296b: Second Dielectric Layer 298: Redistribution (RD) Structure 298b: Redistribution (RD) Structure 299: Second-Group Interconnection Grain Interconnection Structure / Second-Group Interconnection Grain Interconnection Structure 300: Example Method / Method 305: Block 310: Block 315: Block 320: Block 325: Block 330: Block 335: Block 340: Block 345: Block 347: Block 350: Block 355: Block 360: Block 365: Block 370: Block 375: Block 390: Block 400A-1: Example 400A-2: Example 400A-3: Example 400A-4: Example 400B-1: Example 400B-2: Example 400C: Example 400D: Example 400E: Example 400F: Example 400G: Example 400H: Example 400H-2: Example / Example Implementation Plan 400I: Example 400J: Example 400K: Example 400L: Example 400M: Example 400N: Example 401: Functional Grain 402: Functional Grain 403: Functional Grain 404: Functional Grain 411: Functional Grain 412: Functional Grain 413: First grain interconnection structure 414: Second grain interconnection structure 416a: Connecting grain 416b: Connecting grain 417: Connecting grain interconnection structure / passivation layer 421: Carrier 423: Adhesive / underfiller 424: Underfiller 426: Encapsulation material 426’: Encapsulation material 426a: Encapsulation material portion 426b: Encapsulation material portion 431: Second carrier 488: Substrate 500: Example method / method 505: Block 510: Block 515: Block 520: Block 525: Block 530: Block 535: Block 540: Square 545: Square 550: Square 555: Square 560: Square 565: Square 570: Square 575: Square 580: Square 590: Square 600A: Example 600B: Example 600C: Example 600D: Example 600E: Example 600F: Example 600G: Example 600H: Example 600I: Example 600J: Example 600K: Example 600L: Example 600M: Example 611a: First functional grain 612a: Second functional grain 614: Pillar / Interconnection Structure 616b: Connecting Diode 617: Interconnecting Diode Interconnection Structure / Interconnection Structure 621a: Bulk Carrier 646a: Redistribution (RD) Structure 646b: RD Structure 647: Dielectric Layer 648: Conductive Layer 651: Encapsulation Material 651’: Encapsulation Material 652: Auxiliary Interconnection Structure 652’: Encapsulation Material 652a: Encapsulation Material Portion 661: Bottom Filler Material 700: Example Method / Method 705: Block 710: Block 715: Block 720: Block 725: Block 730: Block 735: Block 740: Square 742: Square 745: Square 750: Square 755: Square 760: Square 765: Square 770: Square 775: Square 780: Square 790: Square 800A: Example 800B: Example 800C: Example 800D: Example 800E: Example 800F: Example 800G: Example 800H: Example 800I: Example 800J: Example 800K: Example 800L: Example 800M: Example 800N: Example 811a: Functional Grain 812a: Functional Die 814: Vertical Interconnect Structure 816b: Connecting Die 817: Interconnecting Die Structure 821a: Bulk Carrier 846a: Redistribution (RD) Structure / First Part 846b: Redistribution (RD) Structure / Second Part 847: Dielectric Layer 848: Conductive Layer 851: Encapsulation Material 851’: Encapsulation Material 852: Encapsulation Material 852’: Encapsulation Material 852a: Encapsulation Material Portion 861: Bottom Filler Material 896: Second Redistribution (RD) Structure 897: Dielectric Layer 898: Conductive Layer 900: Example Electronic Device 911: Functional Die 912: Functional die 916: Connector die 930: RD structure 1000: Example electronic device 1030: Substrate

[Figure 1] shows a flowchart of an example method for manufacturing an electronic device according to various forms of the present disclosure.

The cross-sectional views shown in Figures 2A to 2Q illustrate various types of example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 3] shows a flowchart of an example method for manufacturing an electronic device according to various forms of the present disclosure.

The cross-sectional views shown in Figures 4A to 4N illustrate various types of example electronic devices and example methods of manufacturing example electronic devices according to the present disclosure.

[Figure 5] shows a flowchart of an example method for manufacturing an electronic device according to various forms of the present disclosure.

The cross-sectional views shown in Figures 6A to 6M illustrate various examples of electronic devices and methods of manufacturing such electronic devices according to the present disclosure.

[Figure 7] shows a flowchart of an example method for manufacturing an electronic device according to various forms of the present disclosure.

The cross-sectional views shown in Figures 8A to 8N illustrate various examples of electronic devices and methods of manufacturing such electronic devices according to the present disclosure.

[Figure 9] shows a top view of various examples of electronic devices according to the present disclosure.

[Figure 10] shows a top view of various examples of electronic devices according to the present disclosure.

200Q: Case Studies/Case Study Implementation Plans

201: Functional Grains

202: Functional Grains

213: Grain Interconnection Structure / First Grain Interconnection Structure

214: Grain Interconnection Structure / Second Grain Interconnection Structure

216b: Thin connect grains / Connecting grains

225: Encapsulation Material

288:Substrate

299: Second set of interconnected grain structures / Second interconnected grain structure

Claims (22)

An electronic device includes: a signal redistribution structure including a top side and a bottom side of the signal redistribution structure; a vertical interconnect structure coupled to the bottom side of the signal redistribution structure; a connection die including a top side and a bottom side of the connection die; a connection die interconnect structure coupled from the top side of the connection die to the bottom side of the signal redistribution structure; a first conductor pad and a second conductor pad on the top side of the signal redistribution structure, wherein the second conductor pad is configured with a spacing smaller than that of the first conductor pad; and The lower encapsulating material laterally surrounds at least a portion of the connecting grains and each vertical interconnect structure. The electronic device as described in claim 1, wherein the lower encapsulation material contacts one or more interconnected die structures. The electronic device as claimed in claim 1, wherein the lower encapsulation material contacts each vertical interconnect, the interconnect die, and one or more interconnect die interconnects. The electronic device as claimed in claim 1 includes: a first electronic component coupled to the top side of the signal redistribution structure via a first plurality of the first conductor pads and a first plurality of the second conductor pads; and a second electronic component coupled to the top side of the signal redistribution structure via a second plurality of the first conductor pads and a second plurality of the second conductor pads. The electronic device as claimed in claim 4, wherein the interconnect die includes an electrical connector that couples the first electronic component to the second electronic component via coupling to the second conductor pad, respectively. The electronic device as described in claim 4, wherein: each vertical interconnect includes a top end and a bottom end; and the first electronic component and the second electronic component are coupled to one or more of the top ends of the vertical interconnect via coupling to the first conductor pad, respectively. The electronic device as described in claim 4 includes: an upper encapsulating material located above the top side of the signal redistribution structure; and wherein the upper encapsulating material laterally surrounds the first electronic component and the second electronic component. The electronic device as described in claim 7, wherein the transverse side of the signal redistribution structure, the transverse side of the lower encapsulating material, and the transverse side of the upper encapsulating material are coplanar. The electronic device as claimed in claim 1, wherein the top side of the lower encapsulating material is coplanar with the top side of at least one of the vertical interconnect structures and the top side of at least one of the interconnecting grain structures. The electronic device as claimed in claim 1, wherein the transverse side of the signal redistribution structure and the transverse side of the lower encapsulating material are coplanar. The electronic device as described in claim 1 includes an external interconnect structure that couples the lower end of the vertical interconnect structure. An electronic device includes: a signal redistribution structure, including a first side of the signal redistribution structure, a second side of the signal redistribution structure opposite to the first side, and a lateral side of the signal redistribution structure between the first side and the second side; a vertical interconnection structure, wherein each vertical interconnection structure includes a first end of the vertical interconnection structure coupled to the second side of the signal redistribution structure, a second end of the vertical interconnection structure opposite to the first end, and a lateral side of the vertical interconnection structure between the first end and the second end; A connecting die includes a first connecting die side, a second connecting die side opposite to the first connecting die side, and a connecting die lateral side between the first connecting die side and the second connecting die side; A connecting die interconnect structure, wherein each connecting die interconnect structure includes a first end of the connecting die interconnect structure coupled to the second side of the signal redistribution structure, a second end of the connecting die interconnect structure coupled to the first connecting die side, and a connecting die interconnect structure lateral side between the first end of the connecting die interconnect structure and the second end of the connecting die interconnect structure; A first conductor pad and a second conductor pad, both located on the first side of the signal redistribution structure, wherein the second conductor pad is spaced at a smaller interval than the first conductor pad; and a first encapsulating material, which laterally surrounds the grain-connecting side and the lateral side of the vertical interconnect structure of each vertical interconnect structure. The electronic device as claimed in claim 12, wherein the first encapsulating material contacts one or more interconnected die structures on the side side. The electronic device as claimed in claim 12, wherein the first encapsulating material contacts the vertical interconnect side, the interconnect die side, and the interconnect die interconnect side. The electronic device as claimed in claim 12 includes: a first electronic component coupled to a first plurality of the first conductor pads and a first plurality of the second conductor pads; and a second electronic component coupled to a second plurality of the first conductor pads and a second plurality of the second conductor pads. The electronic device as claimed in claim 15, wherein the interconnect die includes an electrical connector that couples the first electronic component to the second electronic component via coupling to the second conductor pad, respectively. The electronic device as claimed in claim 15, wherein the first electronic component and the second electronic component are coupled to the vertical interconnection side via their respective couplings to the first conductor pad. The electronic device as claimed in claim 15 includes a second encapsulating material that laterally surrounds the lateral side of the first electronic component and the lateral side of the second electronic component. The electronic device as claimed in claim 18, wherein the transverse side of the signal redistribution structure, the transverse side of the first encapsulating material, and the transverse side of the second encapsulating material are coplanar. The electronic device as claimed in claim 12, wherein a first side of the first encapsulating material is coplanar with at least one first end of a vertical interconnect structure and at least one first end of a connecting grain interconnect structure. The electronic device as claimed in claim 20, wherein the signal redistribution structure side-by-side and the first encapsulating material side-by-side are coplanar. The electronic device as described in claim 12 includes an external interconnect structure coupled to the second end of the vertical interconnect structure.