TWI860913B - Pcie testing device with versatile and method thereof - Google Patents

Abstract

A PCIe testing device with versatile and method thereof is disclosed. By utilizing an interposer card and connecting cables to electrically link a Unit Under Test (UUT) and a general adapter card device. This general adapter card device comprises multiple connectors designed for linking a dummy PCIe and a IOB (Input/Output Basic) board. It also supplies power to both the interposer card and the IOB board. Following this, a controller executes multiple testing commands to evaluate the signals within a circuit loop formed by the UUT, interposer card, connecting cables, general adapter card device, and dummy PCIe. Within this setup, the general adapter card device tests differential signals, ground signals, and conventional input/output signals, while routing non-conventional input/output signals to the IOB board for further testing. The mechanism is to help to improve testing efficiency and reduce testing costs.

Description

Universal PCIe testing device and method thereof

The present invention relates to a PCIe testing device and a method thereof, and in particular to a universal PCIe testing device and a method thereof.

In recent years, with the popularization and vigorous development of semiconductor technology, various electronic products have sprung up like mushrooms after rain. However, electronic products have many components and complex circuits. How to ensure the quality of the products has always been one of the problems that manufacturers are eager to solve.

Generally speaking, to ensure that the product is good, various testing methods are used. For example, in traditional server testing, the first method is to use the server's motherboard with installed components, such as hard drives of various specifications for testing; the second method is to use a specially made adapter card with components for testing. However, the first method has the disadvantages of time-consuming testing and high cost; the second method requires customized development for each specification, so it also has the disadvantages of time-consuming and high cost. Therefore, the traditional method has the problems of low testing efficiency and high testing costs. Therefore, there is an urgent need for a solution that can reduce customized development time, increase the reusability of adapter cards, and reduce testing costs.

In summary, it can be seen that the prior art has long had the problem of low testing efficiency and high testing costs, so it is necessary to propose improved technical means to solve this problem.

The present invention discloses a universal PCIe testing device and method thereof.

First, the present invention discloses a universal PCIe test device, which is applied in the environment of testing a unit under test (UUT). The UUT is connected to multiple dummy storage devices and includes a test interface to provide multiple test signals. The test interface has a slot for electrical connection. The PCIe test device includes: an intermediary card, an input/output carrier board and a universal adapter card device. One end of the intermediary card allows insertion into a slot that matches the specification, and the other end of the intermediary card is connected to a corresponding connection line. The input/output carrier board includes an input/output connector, a SATA connector and a power connector to receive multiple out-of-band (Sideband) signals to perform functional testing, wherein the out-of-band signals include IIC functions, clock signals and unconventional input/output signals. Next, the universal riser card device includes: multiple connectors and a controller. The connectors include a first connector, a second connector, a third connector, a fourth connector, and a fifth connector. The first connector is a PCIe interface for connecting a virtual PCIe card. The first connector and the second connector are electrically connected to each other through multiple first wires. The second connector is connected to the connection wires to electrically connect the universal riser card device, the intermediary card, and the unit to be tested when the intermediary card is inserted into one of the slots. The second connector and the third connector are electrically connected to each other through multiple second wires. The third connector is connected to the input/output connector. The fourth connector and the SATA connector are electrically connected to each other, the fifth connector and the power connector are electrically connected to each other to provide power to the intermediate card and the input/output carrier board; and the controller is electrically connected to the connectors and executes multiple test instructions to enable the universal adapter card device to test multiple differential signals, multiple ground signals and out-of-band signals provided by the unit under test as test signals, wherein when the out-of-band signal is abnormal, the out-of-band signal is sequentially transmitted to the input/output carrier board through the second connector, the second wire, the third connector and the input/output connector to perform a functional test.

In addition, the present invention also discloses a universal PCIe testing method, which is applied to the environment of testing a unit to be tested, wherein the unit to be tested is connected to a plurality of virtual storage devices, and comprises a test interface to provide a plurality of test signals, wherein the test interface has a corresponding slot for electrical connection, and the steps include: inserting one end of an intermediary card into the slot that matches the specification, and connecting the other end of the intermediary card to a corresponding connection line; electrically connecting the connection line to a universal adapter card device, and the universal adapter card device The device includes a plurality of connectors and a controller, wherein the connector includes a first connector, a second connector, a third connector, a fourth connector and a fifth connector, the first connector and the second connector are electrically connected to each other through a plurality of first wires, the second connector and the third connector are electrically connected to each other through a plurality of second wires, when the connecting wire is connected to the second connector and the intermediate card is inserted into one of the slots, the universal adapter card device, the intermediate card and the unit to be tested are electrically connected to each other The input/output carrier board and the universal riser card device are electrically connected to each other, wherein the input/output carrier board includes an input/output connector, a SATA connector and a power connector, the input/output connector and the third connector are electrically connected to each other, the SATA connector and the fourth connector are electrically connected to each other, and the power connector and the fifth connector are electrically connected to each other to provide power to the intermediate card and the input/output carrier board; the first connector of the PCIe interface is connected to the virtual PC Ie card; and the controller executes a plurality of test instructions, so that the universal adapter card device tests a plurality of differential signals, a plurality of ground signals and a plurality of out-of-band signals provided by the unit under test as test signals, wherein when the out-of-band signal is abnormal, the out-of-band signal is sequentially transmitted to the input/output carrier board through the second connector, the second wire, the third connector and the input/output connector to perform a functional test, wherein the out-of-band signal includes an IIC function, a clock signal and an abnormal input/output signal.

The device and method disclosed in the present invention are as described above. The difference from the prior art is that the present invention electrically connects the unit to be tested and the universal riser card device through an intermediary card and a connection line. The universal riser card device includes a plurality of connectors for connecting the virtual PCIe card and the input/output carrier board, and providing the power required by the intermediary card and the input/output carrier board. The controller then executes a plurality of test instructions to test the signal to be tested on the circuit loop formed by the unit to be tested, the intermediary card, the connection line, the universal riser card device and the virtual PCIe card. The universal riser card device tests differential signals, ground signals and conventional input/output signals, and transmits unconventional input/output to the input/output carrier board for testing.

Through the above-mentioned technical means, the present invention can achieve the technical effect of improving test efficiency and reducing test costs.

The following will be used in conjunction with drawings and embodiments to explain the implementation of the present invention in detail, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

Please refer to "Figure 1" first. "Figure 1" is a device block diagram of the universal PCIe test device of the present invention, which is applied to the environment of testing the unit under test 101. The unit under test 101 is connected to multiple virtual storage devices 102, and includes a test interface (i.e., PCIe interface) to provide multiple test signals. The test interface has a corresponding slot 103 (such as MICO, Slimline connector, etc.) for electrical connection. The PCIe test device 100 includes: an intermediary card 110, an input/output carrier board 120, and a universal adapter card device 130. Among them, one end of the intermediary card 110 allows insertion into the slot 103 that matches the specification, and the other end of the intermediary card 110 is connected to the corresponding connection line 111. In actual implementation, the present invention does not limit the type of the slot 103, that is, various slot types capable of providing the intermediate card 110 for insertion are within the scope of application of the present invention.

The input/output carrier board 120 includes an input/output connector 121, a SATA connector 122, and a power connector 123. The input/output carrier board 120 is used to receive a plurality of out-of-band signals to perform functional tests, wherein the out-of-band signals include IIC functions, clock signals (CLK), and unconventional input/output signals. In other words, the input/output carrier board 120 is responsible for testing signals with related functions, such as IIC, CLK, SPI (Serial Peripheral Interface)/UART (Universal Asynchronous Receiver/Transmitter), JTAG (Joint Test Action Group), power (Power), and other signals.

Next, the universal riser card device 130 includes: a plurality of connectors 131 and a controller 132. The connectors 131 include a first connector 131a, a second connector 131b, a third connector 131c, a fourth connector 131d, and a fifth connector 131e. The first connector 131a is a standard PCIe interface for connecting a virtual PCIe card, which can be tested by a boundary scan. In actual implementation, a virtual PCIe card is an interface card that is inserted into the first connector 131a to simulate an actual PCIe interface card, thereby allowing the PCIe interface to be tested.

The first connector 131a and the second connector 131b are electrically connected to each other via a plurality of first wires 133a, and the second connector 131b is connected to the connection wires, so that when the intermediate card 110 is inserted into one of the slots 103, the universal adapter card device 130, the intermediate card 110 and the unit under test 101 are electrically connected to each other, the second connector 131b and the third connector 131c are electrically connected to each other via a plurality of second wires 133b, the third connector 131c and the input/output connector 121 are electrically connected to each other, the fourth connector 131d and the SATA connector 122 are electrically connected to each other, and the fifth connector 131e and the power connector 123 are electrically connected to each other to provide power to the intermediate card 110 and the input/output carrier 120. In actual implementation, these connectors can be MCIO (Mini Cooledge IO), Slimline, etc.

The controller 132 is electrically connected to the connector 131 and executes a plurality of test instructions, so that the universal adapter card device 130 tests a plurality of differential signals, a plurality of ground signals and out-of-band signals provided by the unit under test 101 as test signals. When the out-of-band signal is abnormal, the universal adapter card device 130 sequentially transmits the out-of-band signal to the input/output carrier board 120 through the second connector 131b, the second wire 133b, the third connector 131c and the input/output connector 121 to perform a functional test. Taking differential signal testing as an example, the virtual PCIe card, the first connector 131a of the universal riser card device 130, the first wire 133a and the second connector 131b, the connection line 111, the intermediate card 110, the unit under test 101 and the virtual storage device 102 sequentially form a signal loop. The virtual PCIe card sends a test vector on the transmission line (TX) of the differential signal for the virtual storage device 102 to receive, and the virtual storage device 102 sends a test vector on the reception line (RX) of the differential signal for the virtual PCIe card to receive, so as to complete the differential signal test. Taking the test ground signal as an example, the ground pin of the unit under test 101 can be electrically connected to the ground pin of the virtual PCIe card through the intermediate card 110 and its corresponding connection line 111, and after sending a high potential, it is ensured to return to a low potential. Taking the test of out-of-band signals as an example, assuming that the connection line 111 includes a first IIC signal and a second IIC signal, when testing the IIC function of the out-of-band signal, the controller 132 allocates the first IIC signal to the fourth connector 131d, i.e., the IIC connection pin (IIC Connect) and the input/output (Dummy PCIe IO) of the virtual PCIe card, and allocates the second IIC signal to the input/output (or Retimer IO) of the virtual PCIe card and the third connector 131c (IO Connect); assuming that the connection line 111 includes a first clock signal and a second clock signal, the controller 132 allocates the first clock signal to the clock pin (Dummy PCIe CLK) and the output/input pin (Dummy PCIe CLK) of the virtual PCIe card. IO), and distributes the second clock signal to the input/output pins (Dummy PCIe IO) of the virtual PCIe card and the third connector 131c. In addition, when the out-of-band signal is irregular, the input/output carrier 120 can perform integrated bus circuit (Inter-Integrated Circuit, IIC) function test and serial peripheral interface (Serial Peripheral Interface, SPI)/universal asynchronous receiver/transmitter (UART) function test, etc., which will be further explained with the help of figures later. It is particularly important to note that, as mentioned above, the input/output carrier board 120 is responsible for testing signals with relevant functions, while the universal adapter card device 130 is responsible for testing conventional input/output signals, such as: enable signal (EN), power good signal (PG), reset signal (RST), PCIe reset (PRST), etc.

It should be particularly noted that, in actual implementation, the present invention may be partially or completely implemented based on hardware, for example, it may be implemented through hardware components such as integrated circuit chips, system on chip (SoC), field programmable gate array (FPGA), complex programmable logic device (CPLD), etc. The test instructions can be written by assembly language instructions, instruction set architecture instructions, machine instructions, machine-related instructions, microinstructions, firmware instructions, or any combination of one or more programming languages, wherein the programming languages include object-oriented programming languages, such as Common Lisp, Python, C++, Objective-C, Smalltalk, Delphi, Java, Swift, C#, Perl, Ruby and PHP, as well as conventional procedural programming languages, such as C language or similar programming languages.

Please refer to "FIG. 2A" and "FIG. 2B", which are flowcharts of a universal PCIe test method of the present invention, which is applied to an environment for testing a unit under test 101, wherein the unit under test 101 is connected to a plurality of virtual storage devices 102, and comprises a test interface to provide a plurality of test signals, wherein the test interface has a corresponding slot 103 for electrical connection, and the steps include: inserting one end of an intermediary card 110 into the slot 103 of a specification that matches, and connecting the other end of the intermediary card 110 to a corresponding connection line 111 (step 210); electrically connecting the connection line 111 to a universal adapter card device 130, and the universal adapter card device 130; The adapter card device 130 includes a plurality of connectors 131 and a controller 132, wherein the connectors 131 include a first connector 131a, a second connector 131b, a third connector 131c, a fourth connector 131d, and a fifth connector 131e. The first connector 131a and the second connector 131b are electrically connected to each other via a plurality of first wires 133a, and the second connector 131b and the third connector 131c are electrically connected to each other via a plurality of second wires 133b. When the connection line 111 is connected to the second connector 131b and the intermediary card 110 is inserted into one of the slots 103, the universal adapter card device 130 is electrically connected to the second connector 131b. 30. The intermediate card 110 and the unit under test 101 are electrically connected to each other (step 220); the input/output carrier 120 and the universal riser card device 130 are electrically connected to each other, wherein the input/output carrier 120 includes an input/output connector 121, a SATA connector 122 and a power connector 123, the input/output connector 121 and the third connector 131c are electrically connected to each other, the SATA connector 122 and the fourth connector 131d are electrically connected to each other, and the power connector 123 and the fifth connector 131e are electrically connected to each other to provide power to the intermediate card 110 and the input/output carrier 120 (step 230); the P The first connector 131a of the PCIe interface is connected to the virtual PCIe card (step 240); and the controller 132 executes a plurality of test instructions to enable the universal adapter device 130 to test a plurality of differential signals, a plurality of ground signals and a plurality of out-of-band signals provided by the unit under test 101 as test signals. When the out-of-band signal is abnormal, the out-of-band signal is sequentially transmitted to the input/output carrier 120 through the second connector 131b, the second wire 133b, the third connector 131c and the input/output connector 121 to perform a functional test. The out-of-band signal includes an IIC function, a clock signal and an abnormal input/output signal (step 250). Through the above steps, the test unit 101 and the universal adapter card device 130 can be electrically connected through the intermediate card 110 and the connection line 111. The universal adapter card device 130 includes a plurality of connectors 131 for connecting the virtual PCIe card and the input/output carrier 120, and providing the power required by the intermediate card 110 and the input/output carrier 120. Then, the controller 132 executes a plurality of test operations. The test command is used to test the signal to be tested on the circuit loop formed by the unit to be tested 101, the intermediate card 110, the connection line 111, the universal riser card device 130 and the virtual PCIe card, wherein the universal riser card device 130 tests the differential signal, the ground signal and the conventional input/output signal, and transmits the unconventional input/output to the input/output carrier board 120 for testing.

The following is explained in the form of an embodiment in conjunction with "Figure 3" and "Figure 4". Please refer to "Figure 3" first. "Figure 3" is a schematic diagram of using multiple intermediary cards to perform testing simultaneously in the present invention. In actual implementation, in addition to using a single intermediary card for testing as shown in "Figure 1", multiple intermediary cards (such as: first intermediary card 310a, second intermediary card 310b) and multiple universal adapter card devices (130a, 130b) can also be used simultaneously as shown in "Figure 3" to test multiple interfaces to be tested on the unit to be tested 101. These intermediary cards (such as the first intermediary card 310a and the second intermediary card 310b) may be of different specifications, such as MCIO to Slimline x8, Slimline x4 to x8, Nearstack to Slimline x8 or the like, for electrically connecting to the unit under test 101. Among them, x4 and x8 refer to different bandwidths, such as quadruple bandwidth and octave bandwidth.

As shown in FIG. 4, FIG. 4 is a schematic diagram of the pins of the connection line to which the present invention is applied. In actual implementation, the number of pins of the connection line 111 is less than or equal to 74, of which 32 are used to transmit differential signals, 24 are used to transmit ground signals, 4 (two groups) are used to transmit IIC signals, 4 (two groups) are used to transmit clock signals, and 10 are used to transmit other out-of-band signals, for a total of 74 wires corresponding to the same number of pins. In other words, the out-of-band signal can transmit two sets of IIC signals (i.e., the first IIC signal and the second IIC signal) through four wires, wherein the first IIC signal is assigned to the fourth connector 131d (i.e., IIC Connect) and the input/output (IO) of the virtual PCIe card (Dummy PCIe) by default. When the IIC signal on the unit under test 101 has an IIC slave, the fourth connector 131d is connected to the SATA connector 122 of the input/output carrier 120 to perform IIC read/write related tests; if the IIC signal on the unit under test 101 is simply transferred to the virtual storage device slot (e.g., NVMe) of the unit under test 101, In addition, the second IIC signal is assigned to the input/output of the virtual PCIe card and the third connector 131c (IO Connect) by default. When the IIC signal on the unit under test 101 is simply transferred to the virtual storage device slot (such as NVMe Slot) of the unit under test 101, the virtual PCIe card and the virtual storage device are also used to perform IO testing. On the contrary, if there is an IIC slave terminal, the third connector 131c is connected to the input/output connector 121 of the input/output carrier board 120 to perform IIC read and write related tests.

In addition, the out-of-band signal can also transmit two sets of clock (CLK) signals through four wires, namely: the first clock signal and the second clock signal, wherein the first clock signal is assigned to the CLK and IO pins of the virtual PCIe card by default. When there is a clock source (Clock Source) on the first clock signal on the unit under test 101, the clock test pin of the virtual PCIe card is used to read the 100M clock signal frequency. On the contrary, if the first clock signal on the unit under test 101 is simply transferred to the virtual storage device slot (such as: NVMe Slot) of the unit under test 101, the virtual PCIe card (such as: Dummy PCIe) and virtual storage devices (such as Dummy NVMe) for IO testing. Next, the second clock signal is assigned to the input/output (Dummy PCIe IO) of the virtual PCIe card and the third connector 131c by default. If the second clock signal on the unit under test 101 is simply transferred to the virtual storage device slot of the unit under test 101, the virtual PCIe card and the virtual storage device are used to perform an IO test. Conversely, if there is a clock source on the second clock signal on the unit under test 101, the third connector 131c and the connection line are used to transfer to the clock test pin on the input/output connector 121 of the input/output carrier 120 to perform a clock signal test.

Finally, out-of-band signals can also transmit other input/output signals through 10 wires, and are pre-assigned to the input/output of the virtual PCIe card and the third connector 131c. If these signals are only conventional EN, PG, RST, PRST and other related IO signals on the unit under test 101, the IO of the virtual PCIe card is used to perform the corresponding transceiver test. If the SIDEBAND Pin has IIC, CLK, SPI, JTAG, Power and other related functional tests on the UUT, the third connector is used with a cable to transfer to the corresponding functional pins on the input/output connector 121 of the input/output carrier board 120 for related signal testing.

In summary, the difference between the present invention and the prior art is that the unit to be tested and the universal adapter card device are electrically connected through the intermediate card and the connection line. The universal adapter card device includes multiple connectors for connecting the virtual PCIe card and the input/output carrier board, and providing the power required by the intermediate card and the input/output carrier board. Then, the controller executes multiple test instructions to connect the unit to be tested, the intermediate card, the connection line, and the universal adapter card device. The signal to be tested is tested on the circuit loop formed by the adapter card device and the virtual PCIe card. The universal adapter card device tests the differential signal, the ground signal and the conventional input/output signal, and transmits the unconventional input/output to the input/output carrier board for testing. This technical means can solve the problems existing in the previous technology, thereby achieving the technical effect of improving the test efficiency and reducing the test cost.

Although the present invention is disclosed as above with the aforementioned embodiments, they are not used to limit the present invention. Anyone skilled in similar techniques can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be subject to the scope of the patent application attached to this specification.

100: PCIe test device 101: unit under test 102: virtual storage device 103: slot 110: intermediary card 111: connection line 120: input/output carrier 121: input/output connector 122: SATA connector 123: power connector 130,130a,130b: universal riser card device 131: connector 131a: first connector 131b: second connector 131c: third connector 131d: fourth connector 131e: fifth connector 132: controller 133a: first wire 133b: second wire 310a: first intermediary card 310b: second intermediary card 411: Connection line Step 210: Insert one end of at least one intermediary card into a slot that matches the specification, and connect the other end of each intermediary card to a corresponding connection line Step 220: Electrically connect the connection line to a universal adapter card device, the universal adapter card device includes multiple connectors and a controller, wherein the connector includes a first connector, a second connector, a third connector, a fourth connector, and a fifth connector, the first connector and the second connector are electrically connected to each other through multiple first wires, and the second connector and the third connector are electrically connected to each other through multiple second wires. When the connection line is connected to the second connector and the intermediary card is inserted into one of the slots, the universal adapter card device, the intermediary card, and the unit to be tested are electrically connected to each other Step 230: electrically connect an input/output carrier board to the universal riser card device, wherein the input/output carrier board includes an input/output connector, a SATA connector, and a power connector, the input/output connector and the third connector are electrically connected to each other, the SATA connector and the fourth connector are electrically connected to each other, and the power connector and the fifth connector are electrically connected to each other to provide power to the intermediate card and the input/output carrier board Step 240: connect the first connector of the PCIe interface to a virtual PCIe card Step 250: The controller executes a plurality of test instructions to enable the universal adapter device to test a plurality of differential signals, a plurality of ground signals, and a plurality of out-of-band (Sideband) signals provided by the unit under test as test signals, wherein when the out-of-band signal is abnormal, the out-of-band signal is sequentially transmitted to the input/output carrier through the second connector, the second wire, the third connector, and the input/output connector to perform a functional test, wherein the out-of-band signal includes an IIC function, a clock signal, and an abnormal input/output signal.

Figure 1 is a device block diagram of the universal PCIe test device of the present invention. Figure 2A and Figure 2B are method flow charts of the universal PCIe test method of the present invention. Figure 3 is a schematic diagram of using the present invention to test multiple intermediate cards at the same time. Figure 4 is a schematic diagram of the connection line pins of the present invention.

100: PCIe test device

101: Unit to be tested

102: Virtual storage device

103: Slot

110: Intermediary card

111:Connection cable

120: Input/output carrier board

121: Input/output connector

122: SATA connector

123: Power connector

130: Universal adapter card device

131: Connector

131a: First connector

131b: Second connector

131c: Third connector

131d: Fourth connector

131e: Fifth connector

132: Controller

133a: First conductor

133b: Second conductor

Claims (10)

A universal PCIe test device is applied to an environment of testing a unit under test (UUT), the UUT is connected to a plurality of dummy storage devices, and comprises at least one UUT interface for providing a plurality of UUT signals, the UUT interface having a corresponding slot for electrical connection, the PCIe test device comprising: at least one intermediate card, one end of the intermediate card allows insertion into the slot that matches the specification, the other end of the intermediate card is connected to a corresponding connection line; an input/output carrier board, comprising an input/output connector, a SATA connector and a power connector; A device for receiving a plurality of out-of-band (Sideband) signals to perform functional testing, wherein the out-of-band signals include IIC functions, clock signals, and unconventional input/output signals; and a universal adapter card device, which includes: a plurality of connectors, wherein the connectors include a first connector, a second connector, a third connector, a fourth connector, and a fifth connector, wherein the first connector is a PCIe interface for connecting a virtual PCIe card, and the first connector and the second connector are connected via The first wires are electrically connected to each other, and the second connector is connected to the connection wires, so that when the intermediate card is inserted into one of the slots, the universal adapter card device, the intermediate card and the unit to be tested are electrically connected to each other, the second connector and the third connector are electrically connected to each other through the second wires, the third connector and the input/output connector are electrically connected to each other, the fourth connector and the SATA connector are electrically connected to each other, and the fifth connector and the power connector are electrically connected to each other. Providing power to the intermediate card and the input/output carrier board; and a controller electrically connected to the connector and executing multiple test instructions to enable the universal adapter card device to test multiple differential signals, multiple ground signals and the out-of-band signal provided by the unit under test as the test signal, wherein when the out-of-band signal is abnormal, the out-of-band signal is sequentially transmitted to the input/output carrier board through the second connector, the second wire, the third connector and the input/output connector to perform a functional test. As in claim 1, the universal PCIe test device, wherein when the controller tests the differential signal, the virtual PCIe card, the first connector of the universal riser card device, the first wire and the second connector, the connection line, the intermediate card, the unit to be tested and the virtual storage device sequentially form a signal loop, the virtual PCIe card sends a test vector on the transmission line (TX) of the differential signal for the virtual storage device to receive, and the virtual storage device sends the test vector on the reception line (RX) of the differential signal for the virtual PCIe card to receive, so as to complete the differential signal test. A universal PCIe test device as claimed in claim 1, wherein the controller electrically connects the ground pin of the unit under test to the ground pin of the virtual PCIe card through the intermediate card and its corresponding connection line when testing the ground signal, and ensures that the ground pin returns to a low potential after issuing a high potential. A universal PCIe test device as claimed in claim 1, wherein the connection line includes a first IIC signal and a second IIC signal, and when testing the IIC function of the out-of-band signal, the controller distributes the first IIC signal to the fourth connector and the input/output (Dummy PCIe IO) of the virtual PCIe card, and distributes the second IIC signal to the input/output of the virtual PCIe card and the third connector (IO Connect). A universal PCIe test device as claimed in claim 1, wherein the connection line includes a first clock signal and a second clock signal, and when testing the clock signal of the out-of-band signal, the controller distributes the first clock signal to the clock pin (Dummy PCIe CLK) and the output/input pin (Dummy PCIe IO) of the virtual PCIe card, and distributes the second clock signal to the input/output (Dummy PCIe IO) of the virtual PCIe card and the third connector (IO Connect). A universal PCIe testing method is applied to an environment of testing a unit under test (UUT), wherein the UUT is connected to a plurality of dummy storage devices and comprises at least one interface under test to provide a plurality of test signals, wherein the interface under test has a corresponding slot for electrical connection, and the steps include: inserting one end of at least one intermediate card into the slot that matches the specification, and connecting the other end of the intermediate card to a corresponding connection line; electrically connecting the connection line to a universal adapter card device, wherein the universal adapter card device comprises a plurality of connectors and a controller, wherein the connection line The connector includes a first connector, a second connector, a third connector, a fourth connector and a fifth connector. The first connector and the second connector are electrically connected to each other through a plurality of first wires, and the second connector and the third connector are electrically connected to each other through a plurality of second wires. When the connecting wires are connected to the second connector and the intermediary card is inserted into one of the slots, the universal adapter card device, the intermediary card and the unit to be tested are electrically connected to each other. An input/output carrier board is connected to the intermediary card. The input/output carrier comprises an input/output connector, a SATA connector and a power connector, the input/output connector and the third connector are electrically connected to each other, the SATA connector and the fourth connector are electrically connected to each other, and the power connector and the fifth connector are electrically connected to each other to provide power to the intermediate card and the input/output carrier; the first connector of the PCIe interface is connected to a virtual PCIe card; and the controller executes multiple A test instruction is provided to enable the universal adapter card device to test multiple differential signals, multiple ground signals and multiple out-of-band (Sideband) signals provided by the unit to be tested as the signals to be tested, wherein when the out-of-band signal is abnormal, the out-of-band signal is sequentially transmitted to the input/output carrier through the second connector, the second wire, the third connector and the input/output connector to perform a functional test, and the out-of-band signal includes an IIC function, a clock signal and an abnormal input/output signal. As in claim 6, the universal PCIe test method, wherein when the controller tests the differential signal, the virtual PCIe card, the first connector of the universal adapter device, the first wire and the second connector, the connection line, the intermediate card, the unit to be tested and the virtual storage device sequentially form a signal loop, the virtual PCIe card sends a test vector on the transmission line (TX) of the differential signal for the virtual storage device to receive, and the virtual storage device sends the test vector on the receiving line (RX) of the differential signal for the virtual PCIe card to receive, so as to complete the differential signal test. As in claim 6, the universal PCIe test method, wherein when testing the ground signal, the controller electrically connects the ground pin of the unit under test to the ground pin of the virtual PCIe card through the intermediate card and its corresponding connection line, and ensures that the ground pin returns to a low potential after issuing a high potential. As in claim 6, the universal PCIe test method, wherein the connection line includes a first IIC signal and a second IIC signal, and when the controller tests the IIC function of the out-of-band signal, the first IIC signal is assigned to the fourth connector and the input/output (Dummy PCIe IO) of the virtual PCIe card, and the second IIC signal is assigned to the input/output of the virtual PCIe card and the third connector (IO Connect). As in claim 6, the universal PCIe test method, wherein the connection line includes a first clock signal and a second clock signal, and when the controller tests the clock signal of the out-of-band signal, the first clock signal is assigned to the clock pin (Dummy PCIe CLK) and the output/input pin (Dummy PCIe IO) of the virtual PCIe card, and the second clock signal is assigned to the input/output pin (Dummy PCIe IO) of the virtual PCIe card and the third connector (IO Connect).