TWI877951B - Testing device for pcie gen5 interface and method thereof - Google Patents

Abstract

A testing device for PCIe gen5 interface and method thereof is disclosed. By using N MCIO (Mini Cool Edge IO) connectors and their corresponding cables to electrically interconnect a test motherboard and a UUT (Unit Under Test), so as to the test motherboard's reception of PCIe Gen5 a plurality of differential signals, differential clock signals, input/output signals, and I2C signals from the UUT, and then executing testing through a testing logic circuit of a CPLD (Complex Programmable Logic Device) and a testing program of a BMC (Baseboard Management Controller). The mechanism is help to the convenience and coverage of testing.

Description

PCIe Gen5 interface testing device and method

The present invention relates to a testing device and a method thereof, in particular to a PCIe Gen5 interface testing device and a method thereof.

In recent years, with the popularization and rapid development of semiconductor technology, various electronic products have sprung up like mushrooms after rain. However, the motherboards of electronic products have many components and complex circuits. How to ensure the good quality of the motherboard has always been one of the problems that manufacturers are eager to solve.

Generally speaking, the traditional way to test motherboards is to use a large number of MCIO (Mini Cool Edge IO) connectors to lead out the PCIe bus, and then connect it to external devices such as the backplane through a cable. When testing these PCIe signals, it is necessary to connect a large number of external boards and use various PCIe devices, such as hard drives, various PCIe expansion cards, etc. However, this method is not only relatively complicated and costly, but also cannot fully cover all types of motherboards. For example, when using the MCIO to PCIe CEM slot part connected to the AIC Riser, there will be more differential clock signals that cannot be tested, and these signals may be used in other forms of configuration. Therefore, the traditional method has the problems of poor testing convenience and insufficient coverage.

In summary, it can be seen that the previous technology has long had problems with poor testing convenience and insufficient coverage, so it is necessary to propose improved technical means to solve this problem.

The present invention discloses a PCIe Gen5 interface testing device and method thereof.

First, the present invention discloses a PCIe Gen5 interface test device, which includes: a test motherboard, a first daughterboard and a second daughterboard. The test motherboard includes: a PCIe switch, a plurality of slots and N MCIO connectors. The PCIe switch is used to expand and manage the connection of the PCIe bus, providing multi-channel connection and data exchange; the slots include at least a first slot and a second slot; one end of each of the MCIO connectors is connected to the PCIe switch, and the other end of each of the MCIO connectors is connected to the PCIe interface of the unit under test (UUT) through a corresponding MCIO connection line, wherein N is a positive integer. Next, in the part of the first daughter board, it is inserted into the first slot to be electrically connected to the test motherboard, and the first daughter board includes a complex programmable logic device (CPLD), wherein the complex programmable logic device includes input/output (I/O) signals, differential clocks (REFCLK) and multiple serial communication test logic circuits suitable for the test board; and the second daughter board is inserted into the second slot to be electrically connected to the test motherboard, and the second daughter board includes a baseboard management controller (BMC) for executing a test program, and the test program drives the complex programmable logic device to test the input/output signals, differential clocks and the serial communication.

In addition, the present invention also discloses a PCIe Gen5 interface testing method, the steps of which include: electrically connecting a test motherboard and a test motherboard, wherein the test motherboard includes a PCIe switch, a plurality of slots and N MCIO connectors, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to the test motherboard through a corresponding MCIO connection line, wherein the slots include at least a first slot and a second slot, and N is a positive integer; inserting a first daughter board into a first slot to be electrically connected to a test motherboard, the first daughter board comprising a complex programmable logic device, wherein the complex programmable logic device comprises input/output signals, differential clocks and a plurality of serial communication test logic circuits applicable to the test motherboard; inserting a second daughter board into a second slot to be electrically connected to the test motherboard, the second daughter board comprising a baseboard management controller; and when performing a PCIe Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input/output signals, differential clocks and the serial communication.

The device and method disclosed in the present invention are as described above. The difference from the prior art is that the present invention electrically connects the test motherboard and the board to be tested to each other through N MCIO connectors and their corresponding connection lines, so that the test motherboard receives the PCIe Gen5 differential signal, differential clock signal, input/output signal and I2C signal from the board to be tested, and then performs testing through the test logic circuit of the complex programmable logic device and the test program of the baseboard management controller.

Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the convenience and coverage of testing.

The following will be used in conjunction with drawings and embodiments to explain the implementation of the present invention in detail, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

Please refer to "Figure 1" first. "Figure 1" is a device block diagram of the PCIe Gen5 interface test device of the present invention. The device includes: a test motherboard 100, a first daughterboard 110 and a second daughterboard 120. The test motherboard 100 includes: a PCIe switch 101, a plurality of slots 102 and N MCIO connectors 103, wherein N is a positive integer. In actual implementation, each MCIO connector 103 of the test motherboard 100 can support differential clock test (REFCLK test), out-of-band (Sideband) signal test, I2C function test and SPI/UART function test. It is particularly important to note that if the number of MCIO connectors of the board under test 130 exceeds the number of MCIO connectors 103 of the test board 100, multiple test boards 100 can be used simultaneously for testing. For example, assuming that the board under test 130 has 16 MCIO connectors and the test board 100 has only 8 MCIO connectors 103, two test boards 100 (such as Lightning devices) can be used simultaneously for testing. In other words, the 8 MCIO connectors 103 of the first test board 100 and the 8 MCIO connectors 103 of the second test board 100 are connected to the 16 MCIO connectors of the board under test 130, so that the two test boards 100 can complete the test at one time without having to distinguish the order of priority. In this way, the traditional PCIe interface test equipment can be simplified by using the test motherboard 100, and the test cost can be reduced and the test coverage can be improved.

The PCIe switch 101 is used to expand and manage the connection of the PCIe bus, providing multi-channel connection and data exchange. In actual implementation, the PCIe switch 101 refers to a PCI Express (Peripheral Component Interconnect Express) switch, which is a high-speed data bus technology used to connect various hardware devices in a computer, such as: display card, network card, storage device, etc. The PCIe switch 101 allows multiple PCIe devices to connect and communicate.

The slot 102 at least includes a first slot 102a and a second slot 102b. In actual implementation, the present invention does not limit the type of the slot 102. As long as the slot 102 can provide the first daughter board 110 and the second daughter board 120 for insertion, various types of the first daughter board 110 and the second daughter board 120 that can be electrically connected to the test motherboard 100 are within the scope of application of the present invention.

One end of each MCIO connector 103 is connected to the PCIe switch 101, and the other end of each MCIO connector 103 is connected to the PCIe interface of the test board 130 through the corresponding MCIO connection line 104. In actual implementation, the MCIO connection line 104 includes M channels for transmitting differential signals between the test motherboard 100 and the test board 130, and the differential signal transmitted in each channel is tested by the complex programmable logic device, wherein M is a positive integer, which will be explained later with reference to the figure.

Next, the first daughter board 110 is inserted into the first slot 102a to be electrically connected to the test motherboard 100. The first daughter board 110 includes a complex programmable logic device, wherein the complex programmable logic device includes input/output signals, differential clocks and multiple serial communication test logic circuits suitable for the test board 130. In actual implementation, the serial communication may include an Inter-Integrated Circuit (I2C), a Serial Peripheral Interface (SPI) and a Universal Asynchronous Receiver/Transmitter (UART), and the complex programmable logic device may complete out-of-band signal testing by testing input/output signals and the serial communication. In addition, when the complex programmable logic device is testing a differential clock, the differential frequency of one of the MCIO connectors 103 may be used as a differential clock, and the differential frequencies of N-1 of the MCIO connectors 103 may be transmitted to the complex programmable logic device to detect the frequency of the differential frequency.

In addition, in the part of the second daughter board 120, it is inserted into the second slot 102b to be electrically connected to the test motherboard 100. This second daughter board 120 includes a baseboard management controller for executing a test program, and the test program drives the complex programmable logic device to test the input/output signal, the differential clock and the serial communication. In addition, the second daughter board 120 can also be connected to various ports, such as: RS232, USB, RJ45 or the like. In actual implementation, the baseboard management controller runs the OpenBMC system to allow integration with the factory business system process, and provides a Redfish application programming development interface to allow control and testing through a third-party vendor system. For example: the third-party vendor system connects to the second daughter board through the above-mentioned port for remote control and testing. The baseboard management controller is responsible for monitoring and managing various hardware information of the test motherboard 100, such as temperature, voltage, PCIe status, etc., and can provide remote system management functions. The OpenBMC it runs is an open source embedded Linux system, that is, a Linux distribution suitable for the baseboard management controller.

It should be particularly noted that, in actual implementation, the present invention can be partially or completely implemented based on hardware. For example, in addition to complex programmable logic devices, it can also be implemented through hardware components such as integrated circuit chips, system on chip (SoC), field programmable gate array (FPGA), etc. The test logic circuit can be written by assembly language instructions, instruction set architecture instructions, machine instructions, machine-related instructions, microinstructions, firmware instructions, or any combination of one or more programming languages, wherein the programming language includes object-oriented programming languages such as Common Lisp, Python, C++, Objective-C, Smalltalk, Delphi, Java, Swift, C#, Perl, Ruby and PHP, as well as conventional procedural programming languages such as C language or similar programming languages.

Please refer to "FIG. 2", which is a flow chart of the PCIe Gen5 interface test method of the present invention, wherein the steps include: electrically connecting a test motherboard 100 and a test board 130 to each other, wherein the test motherboard 100 includes a PCIe switch 101, a plurality of slots 102, and N MCIO connectors 103, wherein one end of each MCIO connector 103 is connected to the PCIe switch 101, and the other end of each MCIO connector 103 is connected to the test board 130 via a corresponding MCIO connection line 104, wherein the slots 102 include at least a first slot 102a and a second slot 102b, and N is a positive integer (step 210); inserting the first daughter board 110 into the first slot 102a to electrically connect to the test motherboard 100, the first daughter board 110 includes a complex programmable logic device, wherein the complex programmable logic device includes input/output signals suitable for the test board 130, a differential clock (REFCLK) and a plurality of serial communication test logic circuits (step 220); inserting the second daughter board 120 into the second slot 102b to electrically connect to the test motherboard 100, the second daughter board 120 includes a baseboard management controller (step 230); and performing PCIe During the Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input/output signal, differential clock and the serial communication (step 240). Through the above steps, the test motherboard 100 and the board to be tested 130 can be electrically connected to each other through N MCIO connectors 103 and their corresponding MCIO connection lines 104, so that the test motherboard 100 receives the PCIe Gen5 differential signal, differential clock signal, input/output signal and I2C signal from the board to be tested 130, and then tests through the test logic circuit of the complex programmable logic device and the test program of the baseboard management controller.

The following is explained in the form of an embodiment with reference to "Figure 3" to "Figure 5". Please refer to "Figure 3" first. "Figure 3" is a schematic diagram of the application of the present invention to test PCIe Gen5 differential signals. In actual implementation, the PCIe signal can be realized by directly connecting the MCIO connector of the test board 130 and the MCIO connector 103 of the test motherboard 100 through the MCIO connection line 104. In practice, the port width of x8 (also known as the number of channels of the port) is adopted by default. Different port width designs can be used for different test situations, such as: x1, x2, x4, x8, x16, etc., where x1 represents a single channel; x2 represents a dual channel, x4 represents a quad channel, and so on. The wider the channel width, the higher the data transmission speed that can be supported.

As shown in FIG. 4 , FIG. 4 is a schematic diagram of applying the present invention to test differential clocks. Assuming that the test board 130 has two CPUs (i.e., CPU0 and CPU1) and their corresponding frequency buffers 410, when the differential clock is to be tested, a differential clock of one of the MCIO connectors 103 can be connected to the PCIe switch 101 of the test motherboard 100 to provide a PCIe differential clock, and the differential clocks of the remaining MCIO connectors 103 are connected to the CPLD so that the frequency of the input clock can be detected through the frequency detection logic circuit on the CPLD.

As shown in FIG. 5 , FIG. 5 is a schematic diagram of applying the present invention to test out-of-band signals. In actual implementation, out-of-band signal testing may include out-of-band input/output signal testing, I2C interconnection testing, I2C/SPI/UART terminal testing, etc. Taking out-of-band input/output signal testing as an example, it is assumed that the MCIO connector of the board under test 130 includes pins numbered A1 to A37 and B1 to B37, which include 8 sets of PCIe Gen5 differential signals, 2 sets of differential clock (REFCLK) signals, a number of input/output signals and power signals, and 3 sets of I2C signals. At this time, the out-of-band input/output signal pins, such as numbered A8, A9, A26, A27, B8/B9, B10, B11, B12, B26/B27, B28 and B29/B30, etc., can be connected to the test motherboard 100 to read the power-on status for testing, and the remaining pins are connected to the first daughter board 110 to implement testing through input/output methods, voltage measurement methods or simulation of I2C Slave devices. For example, pins B8/B9, B26/B27 and B28/B29 can be tested by analog I2C Slave equipment, and the remaining pins can be tested by input/output testing (i.e. I/O testing). Even pins A9 and B12 can be tested by voltage measurement in addition to input/output testing.

Next, taking the I2C interconnection test as an example, the CPLD of the first daughter board 110 is responsible for monitoring the start/stop status of the I2C bus, for example: the pin 530 of each connector numbered B26/B27, and then dynamically switching the I2C interconnection relationship, automatically selecting the I2C bus to communicate, a basic test connection logic is shown in "Figure 5", 16 groups of I2C come from the same I2C master 510 (Master). Therefore, there is no need to implement independent testing for each I2C interface, only the bus needs to be automatically switched, and the I2C slave 520 (Slave) is notified which line of the I2C master 510 is currently connected. In other words, the CPLD is responsible for monitoring the start/stop state of the I2C bus, and then switching the corresponding bus to the I2C slave terminal 520 (or terminal Slave), so that the I2C slave terminal 520 can implement the corresponding response according to the selected line. It should be particularly noted that the specific implementation of the present invention is not limited to the above examples, and any similar I2C interconnection test does not deviate from the scope of application of the present invention.

Next, taking I2C/SPI/UART terminal testing as an example, there are two specific implementation methods. The first is to implement a standard protocol, such as the Universal Backplane Management (UBM) protocol, which can handle basic protocol commands. In this method, the relevant terminal needs to be set up, and the corresponding response packet format is set according to the topological structure of the board 130 to be tested. Another way is the copy mode, that is, at the beginning, by connecting the I2C of the test motherboard 100 to the traditional host line, at this time, the test motherboard 100 works in the monitoring mode, and the overall bus data can be captured and stored in this mode. When testing, the test motherboard 100 will respond to the request of the test board 130 according to the pre-captured and stored data.

In summary, the difference between the present invention and the prior art is that the test motherboard 100 and the board under test 130 are electrically connected to each other through N MCIO connectors 103 and their corresponding MCIO connection lines 104, so that the test motherboard 100 receives the PCIe Gen5 differential signal, differential clock signal, input/output signal and I2C signal from the board under test 130, and then performs the test through the test logic circuit of the complex programmable logic device and the test program of the baseboard management controller. This technical means can solve the problems existing in the prior art, thereby achieving the technical effect of improving the convenience and coverage of the test.

Although the present invention is disclosed as above by the aforementioned embodiments, they are not used to limit the present invention. Anyone skilled in similar techniques can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be subject to the scope of the patent application attached to this specification.

100: test motherboard 101: PCIe switch 102: slot 102a: first slot 102b: second slot 103: MCIO connector 104: MCIO cable 110: first daughter board 120: second daughter board 130: board to be tested 410: frequency buffer 510: I2C master 520: I2C slave 530: pin Step 210: electrically connect a test motherboard and a board to be tested (Unit Under Test, UUT), wherein the test motherboard includes a PCIe switch, multiple slots and N MCIO (Mini Cool Edge IO) connector, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to the board under test through a corresponding MCIO connection line, wherein the slot includes at least a first slot and a second slot, and N is a positive integer Step 220: insert a first daughter board into the first slot to electrically connect to the test motherboard, the first daughter board includes a complex programmable logic device (CPLD), wherein the complex programmable logic device includes input/output (I/O) signals, differential clocks (REFCLK) and multiple serial communication test logic circuits suitable for the board under test Step 230: insert a second daughter board into the second slot to electrically connect to the test motherboard, the second daughter board includes a baseboard management controller (BMC) Step 240: when performing a PCIe Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input/output signal, differential clock and the serial communication

FIG. 1 is a device block diagram of the PCIe Gen5 interface test device of the present invention. FIG. 2 is a method flow chart of the PCIe Gen5 interface test method of the present invention. FIG. 3 is a schematic diagram of the present invention for testing PCIe Gen5 differential signals. FIG. 4 is a schematic diagram of the present invention for testing differential clocks. FIG. 5 is a schematic diagram of the present invention for testing out-of-band signals.

100: Test motherboard

101: PCIe switch

102: Slot

102a: First slot

102b: Second slot

103:MCIO connector

104:MCIO connection cable

110: First sub-board

120: Second sub-board

130: Board under test

Claims (8)

A PCIe Gen5 interface test device, the device comprising: A test motherboard, the test motherboard comprising: A PCIe switch for expanding and managing the connection of the PCIe bus, providing multi-channel connection and data exchange; A plurality of slots, the slots comprising at least a first slot and a second slot; and N MCIO (Mini Cool Edge IO) connectors, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to a PCIe interface of a unit under test (UUT) through a corresponding MCIO connection line, wherein N is a positive integer; A first daughterboard, inserted into the first slot to be electrically connected to the test motherboard, the first daughterboard comprising a complex programmable logic device (Complex Programmable Logic Device, CPLD), wherein the complex programmable logic device includes input/output (I/O) signals, differential clocks (REFCLK) and multiple serial communication test logic circuits suitable for the test board; and a second daughter board inserted into the second slot to be electrically connected to the test motherboard, the second daughter board including a baseboard management controller (Baseboard Management Controller, BMC) is used to execute a test program, which drives the complex programmable logic device to test the input/output signal, the differential clock and the serial communication, wherein the complex programmable logic device uses the differential frequency of one of the MCIO connectors as the differential clock when testing the differential clock, and transmits the differential frequencies of N-1 of the MCIO connectors to the complex programmable logic device to detect the frequency of the differential clock. A PCIe Gen5 interface test device as claimed in claim 1, wherein the serial communication includes an Inter-Integrated Circuit (I2C), a Serial Peripheral Interface (SPI) and a Universal Asynchronous Receiver/Transmitter (UART), and the complex programmable logic device completes out-of-band (Sideband) signal testing by testing input/output signals and the serial communication. A PCIe Gen5 interface test device as claimed in claim 1, wherein the MCIO connection line includes M channels for transmitting differential signals between the test motherboard and the board to be tested, and the differential signal transmitted in each of the channels is tested by the complex programmable logic device, wherein M is a positive integer. A PCIe Gen5 interface test device as claimed in claim 1, wherein the baseboard management controller runs the OpenBMC system to allow integration with factory business system processes, and provides a Redfish application programming development interface to allow control and testing through a third-party vendor system. A PCIe Gen5 interface test method, the steps of which include: Electrically connecting a test motherboard and a unit under test (UUT), wherein the test motherboard includes a PCIe switch, multiple slots and N MCIO (Mini Cool Edge IO) connectors, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to the unit under test through a corresponding MCIO connection line, wherein the slots include at least a first slot and a second slot, and N is a positive integer; Inserting a first daughter board into the first slot to electrically connect to the test motherboard, the first daughter board includes a complex programmable logic device (Complex Programmable Logic Device, CPLD), wherein the complex programmable logic device includes input/output (I/O) signals, differential clocks (REFCLK) and multiple serial communication test logic circuits suitable for the test board; Inserting a second daughter board into the second slot to electrically connect to the test motherboard, the second daughter board includes a baseboard management controller (BMC); and During PCIe During the Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input/output signal, differential clock and the serial communication, wherein the complex programmable logic device uses the differential frequency of one of the MCIO connectors as the differential clock when testing the differential clock, and transmits the differential frequencies of N-1 of the MCIO connectors to the complex programmable logic device to detect the frequency of the differential clock. As in claim 5, the PCIe Gen5 interface testing method, wherein the serial communication includes an Inter-Integrated Circuit (I2C), a Serial Peripheral Interface (SPI) and a Universal Asynchronous Receiver/Transmitter (UART), and the complex programmable logic device completes out-of-band (Sideband) signal testing by testing input/output signals and the serial communication. A PCIe Gen5 interface testing method as claimed in claim 5, wherein the MCIO connection line includes M channels for transmitting differential signals between the test motherboard and the board to be tested, and the differential signal transmitted in each of the channels is tested by the complex programmable logic device, wherein M is a positive integer. A PCIe Gen5 interface testing method as claimed in claim 5, wherein the baseboard management controller runs the OpenBMC system to allow integration with factory business system processes, and provides a Redfish application programming development interface to allow control and testing through a third-party vendor system.

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