TWI852824B - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a light emitting diode, first to fifth transistors, first to third capacitors, a first compensation writing circuit, a second compensation writing circuit and a voltage adjustment circuit. The first transistor and the second transistor are coupled in series between a cathode of the light-emitting diode and a system low voltage. The third transistor, the fourth transistor and the fifth transistor are coupled in series between the first compensation writing circuit and a first reference voltage. The first capacitor is coupled between the second transistor and the first reference voltage. The second capacitor and the third capacitor are coupled in series between the third transistor and a swing signal. The second compensation writing circuit is coupled to the first transistor. The voltage adjustment circuit is coupled to a connection point between the second capacitor and the third capacitor.

Description

Pixel circuit

The present invention relates to a pixel circuit, and in particular to a light emitting diode pixel circuit.

As environmental awareness rises, energy saving, lifespan, color saturation, and power quality are gradually becoming factors that consumers consider when purchasing. At the same time, the rapid development of semiconductor technology and the reduction of costs have driven light-emitting components to become the mainstream of future lighting and display markets. Among them, organic light-emitting diodes (OLEDs) and micro-light-emitting diodes (uLEDs) are the main components currently used in self-luminous display panels.

However, the luminance curves of micro-LEDs (uLEDs) and organic LEDs (OLEDs) are different, that is, when operating at the same brightness, the luminous efficiency of the LEDs is very low. In addition, since the current range operated by the driving circuit of the organic LED falls within the low luminous efficiency range of the micro-LED, the driving circuit of the organic LED developed earlier cannot be directly applied to the micro-LED. Therefore, in order to drive the micro-LED, the existing driving circuit needs to be modified or redesigned accordingly.

The present invention provides a pixel circuit which can reduce the cross-voltage of power supply and shorten the time required to turn on a light-emitting diode.

The pixel circuit of the present invention includes a light-emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, a third capacitor, a first compensation write circuit, a second compensation write circuit and a voltage adjustment circuit. The light-emitting diode has an anode and a cathode for receiving a high voltage of a system. The first transistor has a first end coupled to the cathode of the light-emitting diode, a control end, and a second end. The second transistor has a first end coupled to the second end of the first transistor, a control end, and a second end for receiving a low voltage of a system. The third transistor has a first end, a control end, and a second end. The fourth transistor has a first end coupled to the second end of the third transistor, a control end for receiving a light-emitting signal, and a second end coupled to the control end of the second transistor. The fifth transistor has a first end coupled to the control end of the second transistor, a control end receiving a multiple light-emitting signal, and a second end receiving a first reference voltage. The first capacitor is coupled between the control end of the second transistor and the first reference voltage. The second capacitor is coupled to the control end of the third transistor. The third capacitor is coupled between the second capacitor and the swing signal. The first compensation write circuit receives the pulse width data voltage and is coupled to the first end, the control end, and the second end of the third transistor to compensate for the critical voltage of the third transistor and write data based on the pulse width data voltage. The second compensation writing circuit receives the pulse amplitude data voltage and is coupled to the first end, the control end and the second end of the first transistor to compensate for the critical voltage of the first transistor and write data based on the pulse amplitude data voltage. The voltage adjustment circuit is coupled to the connection point between the second capacitor and the third capacitor and is coupled to the second end of the fourth transistor to respond to the voltage level of the light-emitting diode's light-emitting adjustment connection point.

Based on the above, the pixel circuit of the embodiment of the present invention has only two transistors on the current path, which can reduce the cross-voltage of the power supply; and in the light-emitting stage of the light-emitting diode, the gate voltage of the third transistor is adjusted through voltage coupling to adjust and increase the opening degree of the third transistor, thereby reducing the time required to turn on the light-emitting diode. Therefore, the critical voltage of the driving transistor (i.e., the first transistor) and the control transistor (i.e., the third transistor) can be effectively compensated, as well as the current resistance voltage drop of the high voltage of the system, and the proportion of the rising time of the gate voltage of the second transistor to the overall light-emitting time can be greatly reduced, thereby improving the grayscale control capability.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such in this document.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "include" specify the presence and/or parts of the features, regions, entireties, steps, operations, elements, components and/or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and/or combinations thereof.

FIG1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Referring to FIG1 , in this embodiment, the pixel circuit 100 includes a light-emitting diode LED1, transistors T1 to T5 (corresponding to the first transistor to the fifth transistor), capacitors C1 to C3 (corresponding to the first capacitor to the third capacitor), a first compensation writing circuit PCT1, a second compensation writing circuit PCT2, and a voltage adjustment circuit PLCT, wherein the light-emitting diode LED1 includes, for example, a micro light-emitting diode, transistors T1 and T3 to T5 are respectively P-type transistors, and transistor T2 is an N-type transistor.

The light-emitting diode LED1 has an anode and a cathode receiving a system high voltage V _DD . The transistor T1 has a first end coupled to the cathode of the light-emitting diode LED1, a control end, and a second end. The transistor T2 has a first end coupled to the second end of the transistor T1, a control end, and a second end coupled to the system low voltage V _SS . The driving current I _DR is provided to the light-emitting diode LED1 only through the transistor T1 and the transistor T2, that is, between the system high voltage V _DD and the system low voltage V _SS , the driving current I _DR only flows through the light-emitting diode LED1, the transistors T1 and T2.

The transistor T3 has a first terminal, a control terminal, and a second terminal. The transistor T4 has a first terminal coupled to the second terminal of the transistor T3, a control terminal receiving the luminous signal EM[n], and a second terminal coupled to the control terminal of the transistor T2, wherein n is a positive integer greater than or equal to 1. The transistor T5 has a first terminal coupled to the control terminal of the transistor T2, a control terminal receiving the multiple luminous signals mEM[n], and a second terminal receiving the first reference voltage V _REF1 .

Capacitor C1 is coupled between the control terminal of transistor T2 and the first reference voltage V _REF1 . Capacitor C2 is coupled to the control terminal of transistor T3. Capacitor C3 is coupled between the second capacitor C2 and the swing signal V _SWEEP [n], and capacitors C2 and C3 are connected in series between the control terminal of transistor T3 and the swing signal V _SWEEP [n].

The first compensation write circuit PCT1 receives the pulse width data voltage V _{DATA_PWM} and is coupled to the first end, the control end and the second end of the transistor T3 to compensate for the critical voltage of the transistor T3 and write data based on the pulse width data voltage V _{DATA_PWM} . The second compensation write circuit PCT2 receives the pulse amplitude data voltage V _{DATA_PAM} and is coupled to the first end, the control end and the second end of the transistor T1 to compensate for the critical voltage of the transistor T1 and write data based on the pulse amplitude data voltage V _{DATA_PAM} . The voltage adjustment circuit PLCT is coupled to the connection point between the capacitors C2 and C3 (ie, the node G), and is coupled to the second end of the transistor T4 to respond to the voltage level of the light-emitting adjustment node G of the light-emitting diode LED1.

According to the above, in the pixel circuit 100, there are only two transistors T1 and T2 on the current path, which can reduce the cross-voltage of the power supply; and in the light-emitting stage of the light-emitting diode LED1, the turn-on degree of the transistor T3 can be increased by adjusting the voltage level of the node G, thereby reducing the time required to turn on the light-emitting diode LED1, that is, the time required for the gate voltage of the transistor T2 to rise to the critical voltage. Therefore, the critical voltage of the driving transistor and the control transistor (i.e., transistors T1 and T3) and the current-resistance drop (IR drop) of the system high voltage V _DD can be effectively compensated, and the proportion of the gate voltage rise time of transistor T2 to the overall luminescence time can be greatly reduced, thereby improving the grayscale control capability.

In this embodiment, the first compensation write circuit PCT1 includes transistors T6 to T9 (corresponding to the sixth transistor to the ninth transistor), wherein the transistors T6 to T9 are respectively P-type transistors. The transistor T6 has a first end for receiving the second reference voltage V _REF2 , a control end for receiving the luminous signal EM[n], and a second end coupled to the first end of the transistor T3. The transistor T7 has a first end coupled to the first end of the transistor T3, a control end for receiving the control signal S1[n] (corresponding to the first control signal), and a second end for receiving the pulse width data voltage V _{DATA_PWM} .

Transistor T8 has a first end receiving a first reference voltage V _REF1 , a control end receiving a control signal S1[n-1] (corresponding to a second control signal), and a second end coupled to the control end of transistor T3, wherein the control signal S1[n-1] may be a control signal S1[n] provided to an upper level or upper row pixel circuit (such as 100), that is, the phase of the control signal S1[n-1] is ahead of the first control signal S1[n]. Transistor T9 has a first end coupled to the control end of transistor T3, a control end receiving the control signal S1[n], and a second end coupled to the second end of transistor T3.

In this embodiment, the second compensation write circuit PCT2 includes transistors T10-T14 (corresponding to the tenth transistor to the fourteenth transistor) and a capacitor C4 (corresponding to the fourth capacitor), wherein the transistors T10, T11, T13 and T14 are respectively exemplified by P-type transistors, and the transistor T12 is exemplified by an N-type transistor. The transistor T10 has a first end receiving the third reference voltage V _REF3 , a control end receiving the multiple luminous signals mEM[n], and a second end coupled to the first end of the transistor T1. The transistor T11 has a first end coupled to the first end of the transistor T1, a control end receiving the luminous signal EM[n], and a second end. The transistor T12 has a first end coupled to the second end of the transistor T11, a control end receiving the luminous signal EM[n], and a second end receiving the pulse width data voltage V _{DATA_PWM} .

Capacitor C4 is coupled between the second terminal of transistor T11 and the control terminal of transistor T1. Transistor T13 has a first terminal coupled to the second terminal of transistor T1, a control terminal receiving control signal S1[n], and a second terminal coupled to the control terminal of transistor T3. Transistor T14 has a first terminal coupled to the control terminal of transistor T3, a control terminal receiving control signal S1[n-1], and a second terminal receiving first reference voltage V _REF1 .

In this embodiment, the voltage adjustment circuit PLCT includes transistors T15 and T16 (corresponding to the fifteenth transistor and the sixteenth transistor), wherein the transistor T5 is a P-type transistor, and the transistor T16 is an N-type transistor. The transistor T15 has a first end receiving the third reference voltage V _REF3 , a control end receiving the multiple light-emitting signal mEM[n], and a second end coupled to the node G. The transistor T16 has a first end coupled to the node G, a control end coupled to the second end of the transistor T4, and a second end receiving the first reference voltage V _REF1 .

FIG2 is a schematic diagram of a driving waveform of a pixel circuit according to an embodiment of the present invention. Referring to FIG1 and FIG2, in the present embodiment, the operation of the pixel circuit 100 in a single frame period is roughly divided into five stages: a reset period (1), a compensation period (2), a stabilization period (3), a light-emitting period (4), and a shutdown period (5), wherein the reset period (1), the compensation period (2), the stabilization period (3), and the light-emitting period (4) are located in two shutdown periods (5), and the stabilization period (3) and the light-emitting period (4) are repeated to achieve a repeated light-emitting function.

In this embodiment, the voltage levels of the control signals S1[n-1] and S1[n], the luminous signal EM[n], and the multiple luminous signal mEM[n] are switched between a gate high voltage V _GH and a gate low voltage V _GL , and the voltage level of the swing signal V _SWEEP [n] swings between a swing high voltage V _SH and a swing low voltage V _SL .

During the reset period (1), the control signal S1[n-1] and the multiple luminescence signal mEM[n] are at a gate low voltage V _GL , and the control signal S1[n] and the luminescence signal EM[n] are at a gate high voltage V _GH . At this time, transistors T5, T8, T10, T12, T14 and T15 are turned on, and transistors T4, T6, T7, T9, T11, T13 and T16 are turned off (i.e., not turned on). Therefore, the voltage level of node A is the first reference voltage V _REF1 , the voltage level of node B is the third reference voltage V _REF3 , the voltage level of node C is the pulse amplitude data voltage V _{DATA — PAM} , the voltage level of node D is the first reference voltage V _REF1 , the voltage level of node E is the second reference voltage V _REF2 , the voltage level of node F is the first reference voltage V _REF1 , and the voltage level of node G is the third reference voltage V _REF3 . Furthermore, the transistor T1 is turned on due to the voltage level of the node A, the transistors T2 and T16 are turned off due to the voltage level of the node F, and the transistor T3 is turned on due to the voltage level of the node D. Thus, the operation state of the pixel circuit 100 can be reset.

During the compensation period (2), the control signal S1[n] and the multiple luminescence signal mEM[n] are at a gate low voltage V _GL , and the control signal S1[n-1] and the luminescence signal EM[n] are at a gate high voltage V _GH . At this time, transistors T5, T7, T9, T10, T12, T13, and T15 are turned on, and transistors T4, T6, T8, T11, T14, and T16 are turned off (i.e., not turned on). Therefore, the voltage level of node A is the third reference voltage V _REF3 minus the critical voltage of transistor T1, the voltage level of node B is the third reference voltage V _REF3 , the voltage level of node C is the pulse amplitude data voltage V _{DATA_PAM} , the voltage level of node D is the pulse width data voltage V _{DATA_PWM} minus the critical voltage of transistor T3, the voltage level of node E is the pulse width data voltage V _{DATA_PWM} , the voltage level of node F is the first reference voltage V _REF1 , and the voltage level of node G is the third reference voltage V _REF3 . Furthermore, transistor T1 is turned on due to the voltage level of node A, transistors T2 and T16 are turned off due to the voltage level of node F, and transistor T3 is turned on due to the voltage level of node D. Thus, the critical voltages of transistors T1 and T3 of the pixel circuit 100 can be compensated, and the pulse amplitude data voltage V _{DATA_PAM} and the pulse width data voltage V _{DATA_PWM} can be written into the pixel circuit 100.

During the stable period (3), the luminous signal EM[n] and the multiple luminous signal mEM[n] are at a gate low voltage V _GL , and the control signal S1[n] and the control signal S1[n-1] are at a gate high voltage V _GH . At this time, transistors T4, T5, T6, T10, T11 and T15 are turned on, and transistors T7, T8, T9, T12, T13, T14 and T16 are turned off (i.e., not turned on). Therefore, the voltage level of node A is the third reference voltage V _REF3 −the critical voltage of transistor T1 + the third reference voltage V _REF3 −the pulse amplitude data voltage V _{DATA_PAM} , the voltage level of node B is the third reference voltage V _REF3 , the voltage level of node C is the third reference voltage V _REF3 , the voltage level of node D is the pulse width data voltage V _{DATA_PWM} minus the critical voltage of transistor T3 , the voltage level of node E is the second reference voltage V _REF2 , the voltage level of node F is the first reference voltage V _REF1 , and the voltage level of node G is the third reference voltage V _REF3 . Furthermore, the transistor T1 is turned on due to the voltage level of the node A, the transistors T2 and T16 are turned off due to the voltage level of the node F, and the transistor T3 is turned off due to the voltage level of the node D. Thus, the pulse amplitude data voltage V _{DATA_PAM} can be moved to the node A.

During the luminescence period (4), the luminescence signal EM[n] is at a gate low voltage V _GL , and the control signal S1[n], the control signal S1[n-1] and the multiple luminescence signal mEM[n] are at a gate high voltage V _GH . At this time, transistors T4, T6 and T11 are turned on, and transistors T5, T7, T8, T9, T10, T12, T13, T14, T15 and T16 are turned off (i.e., not turned on). Therefore, the voltage level of node A is the third reference voltage _VREF3 - the critical voltage of transistor T1 + the third reference voltage _VREF3 - the pulse amplitude data voltage _{VDATA_PAM} , the voltage level of node B is the third reference voltage _VREF3 , the voltage level of node C is the third reference voltage _VREF3 , the voltage level of node D is the pulse width data voltage _{VDATA_PWM} - the critical voltage of transistor T3 - |∆V| (i.e., the voltage variation), the voltage level of node E is the second reference voltage _VREF2 , and the voltage level of node F is the first reference voltage _VREF1 , and the voltage level of the node G is the third reference voltage _VREF3 minus |∆V|. Furthermore, the transistor T1 is turned on by the voltage level of the node A, the transistors T2 and T16 are turned off by the voltage level of the node F, and the transistor T3 is turned off by the voltage level of the node D.

In this embodiment, transistor T3 is turned on when the voltage difference between point E and point D is greater than the critical voltage of transistor T3, that is, the second reference voltage V _REF2 - (pulse width data voltage V _{DATA_PWM} - critical voltage of transistor T3 - |∆V|)> the critical voltage of transistor T3. Through deduction, the above can be simplified to |∆V|> pulse width data voltage V _{DATA_PWM} - second reference voltage V _REF2 , that is, when the voltage variation ∆V is greater than the pulse width data voltage V _{DATA_PWM} - second reference voltage V _REF2 , transistor T3 will be turned on. Then, the voltage level of the node F is charged from the first reference voltage V _REF1 to the second reference voltage V _REF2 , thereby turning on the transistors T2 and T16 .

After transistors T2 and T16 are turned on, the voltage level of node A is the third reference voltage _VREF3 - the critical voltage of transistor T1 - the pulse amplitude data voltage _{VDATA_PAM} + the system high voltage _{VDD -VLED} (i.e., the voltage across the light-emitting diode LED1), the voltage level of node B is the system high voltage _{VDD -VLED} , the voltage level of node C is the system high voltage _{VDD -VLED} , the voltage level of node D is the pulse width data voltage _{VDATA_PWM} - the critical voltage of transistor T3 + the first reference voltage _VREF1 - the third reference voltage _VREF3 , and the voltage level of node E is the second reference voltage V _REF2 , the voltage level of the node F is the second reference voltage V _REF2 , and the voltage level of the node G is the first reference voltage V _REF1 . At this time, the driving current I _DR =K(V _{DATA — PWM} -V _REF3 ) ² , where K is the current coefficient.

In the present embodiment, after transistor T16 is turned on, node G is discharged to a first reference voltage _VREF1 which is lower than the third reference voltage _VREF3 , so that node D is coupled to a lower potential, allowing transistor T8 to be further opened (i.e., the degree of conduction is increased), thereby increasing the charging speed of node F (i.e., shortening the time required for the voltage level of node F to charge from the first reference voltage _VREF1 to the second reference voltage _VREF2 ).

During the off period (5), the multiple luminous signal mEM[n] is at a gate low voltage V _GL , and the control signal S1[n], the control signal S1[n-1] and the luminous signal EM[n] are at a gate high voltage V _GH . At this time, transistors T5, T10, T12 and T15 are turned on, and transistors T4, T6, T7, T8, T9, T11, T13, T14 and T16 are turned off (i.e., not turned on). Therefore, the voltage level of node A is the third reference voltage V _REF3 - the critical voltage of transistor T1, the voltage level of node B is the third reference voltage V _REF3 , the voltage level of node C is the pulse amplitude data voltage V _{DATA_PAM} , the voltage level of node D is the pulse width data voltage V _{DATA_PWM} - the critical voltage of transistor T3, the voltage level of node E is the second reference voltage V _REF2 , the voltage level of node F is the first reference voltage V _REF1 , and the voltage level of node G is the third reference voltage V _REF3 . Furthermore, the transistor T1 is turned off due to the voltage level of the node A, the transistors T2 and T16 are turned off due to the voltage level of the node F, and the transistor T3 is turned off due to the voltage level of the node D.

In the embodiment of the present invention, the sizes of the system high voltage V _DD , the system low voltage V _SS , the gate high voltage V _GH , the gate low voltage V _GL , the swing high voltage V _SH , the swing low voltage V _SL , the pulse amplitude data voltage V _{DATA_PAM} , the first reference voltage V _REF1 , the second reference voltage V _REF2 , and the third reference voltage V _REF3 can refer to the following inequality: V _GH > V _SH > V _{DATA_PAM} > V _REF3 > V _DD > V _REF2 > V _SL > V _SS > V _REF1 > V _GL , but the present invention is not limited thereto.

In the embodiment of the present invention, the duration of the reset period (1), the compensation period (2), and the stabilization period (3) can be one horizontal scanning period respectively, and the duration of the light-emitting period (4) can be two horizontal scanning periods. This depends on the circuit design, and the embodiment of the present invention is not limited thereto.

In summary, the pixel circuit of the embodiment of the present invention has only two transistors in the current path, which can reduce the cross-voltage of the power supply; and in the light-emitting stage of the light-emitting diode, the gate voltage of the third transistor is adjusted through voltage coupling to adjust and increase the opening degree of the third transistor, thereby reducing the time required to turn on the light-emitting diode. Therefore, the critical voltage of the driving transistor (i.e., the first transistor) and the control transistor (i.e., the third transistor) can be effectively compensated, as well as the current resistance voltage drop of the high voltage of the system, and the proportion of the rising time of the gate voltage of the second transistor to the overall light-emitting time can be greatly reduced, thereby improving the grayscale control capability.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: Pixel circuit A~G: Nodes C1~C4: Capacitor EM[n]: Light emitting signal I _DR : Driving current LED1: Light emitting diode mEM[n]: Multiple light emitting signals PCT1: First compensation write circuit PCT2: Second compensation write circuit PLCT: Voltage adjustment circuit S1[n], S1[n-1]: Control signal T1~T16: Transistor V _{DATA_PAM} : Pulse amplitude data voltage V _{DATA_PWM} : Pulse width data voltage V _DD : System high voltage V _GH : Gate high voltage V _GL : Gate low voltage V _REF1 : First reference voltage V _REF2 : Second reference voltage V _REF3 : Third reference voltage V _SH : Swing high voltage V _SL : Swing low voltage V _SS : System low voltage V _SWEEP [n]: Swing signal (1): Reset period (2): Compensation period (3): Stabilization period (4): Lighting period (5): Shutdown period

FIG1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. FIG2 is a driving waveform diagram of a pixel circuit according to an embodiment of the present invention.

100: Pixel circuit

A~G: Node

C1~C4: Capacitor

EM[n]: luminous signal

I _DR : Driving current

LED1: light emitting diode

mEM[n]: multiple luminescence signals

PCT1: First compensation write circuit

PCT2: Second compensation writing circuit

PLCT: Voltage regulation circuit

S1[n], S1[n-1]: control signal

T1~T16: Transistor

V _{DATA_PAM} : Pulse amplitude data voltage

V _{DATA_PWM} : Pulse width data voltage

V _DD : System high voltage

V _REF1 : First reference voltage

V _REF2 : Second reference voltage

V _REF3 : Third reference voltage

V _SS : System low voltage

V _SWEEP [n]: Swing signal

Claims (8)

A pixel circuit includes: a light-emitting diode having an anode and a cathode for receiving a system high voltage; a first transistor having a first end coupled to the cathode of the light-emitting diode, a control end, and a second end; a second transistor having a first end coupled to the second end of the first transistor, a control end, and a second end for receiving a system low voltage; a third transistor having a first end, a control end, and a third end. a fourth transistor having a first end coupled to the second end of the third transistor, a control end receiving a light-emitting signal, and a second end coupled to the control end of the second transistor; a fifth transistor having a first end coupled to the control end of the second transistor, a control end receiving a multiple light-emitting signal, and a second end receiving a first reference voltage; a first capacitor coupled between the control end of the second transistor and the first transistor; a reference voltage; a second capacitor coupled to the control end of the third transistor; a third capacitor coupled between the second capacitor and a swing signal; a first compensation write circuit receiving a pulse width data voltage and coupled to the first end, the control end and the second end of the third transistor to compensate for a critical voltage of the third transistor and write data based on the pulse width data voltage; a second compensation write circuit, Receive a pulse amplitude data voltage, and couple the first end, the control end and the second end of the first transistor to compensate a critical voltage of the first transistor, and write data based on the pulse amplitude data voltage; and a voltage adjustment circuit, coupled to a connection point between the second capacitor and the third capacitor, and coupled to the second end of the fourth transistor, to adjust a voltage level of the connection point in response to the light emission of the light-emitting diode. The pixel circuit as described in claim 1, wherein the first compensation writing circuit comprises: a sixth transistor having a first end receiving a second reference voltage, a control end receiving the light-emitting signal, and a second end coupled to the first end of the third transistor; a seventh transistor having a first end coupled to the first end of the third transistor, a control end receiving a first control signal, and a second end receiving the pulse width data voltage; an eighth transistor having a first end receiving the first reference voltage, a control end receiving a second control signal, and a second end coupled to the control end of the third transistor; and a ninth transistor having a first end coupled to the control end of the third transistor, a control end receiving the first control signal, and a second end coupled to the second end of the third transistor. The pixel circuit as described in claim 2, wherein the second compensation writing circuit comprises: a tenth transistor having a first end receiving a third reference voltage, a control end receiving the multiple light-emitting signals, and a second end coupled to the first end of the first transistor; an eleventh transistor having a first end coupled to the first end of the first transistor, a control end receiving the light-emitting signals, and a second end; a twelfth transistor having a first end coupled to the second end of the eleventh transistor, a control end receiving the light-emitting signals, and a second end. a second end receiving the pulse width data voltage; a fourth capacitor coupled between the second end of the eleventh transistor and the control end of the first transistor; a thirteenth transistor having a first end coupled to the second end of the first transistor, a control end receiving the first control signal, and a second end coupled to the control end of the third transistor; and a fourteenth transistor having a first end coupled to the control end of the third transistor, a control end receiving the second control signal, and a second end receiving the first reference voltage. The pixel circuit as described in claim 3, wherein the voltage adjustment circuit comprises: a fifteenth transistor having a first end receiving the third reference voltage, a control end receiving the multiple light-emitting signals, and a second end coupled to the connection point; and a sixteenth transistor having a first end coupled to the connection point, a control end coupled to the second end of the fourth transistor, and a second end receiving the first reference voltage. The pixel circuit as described in claim 4, wherein the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are each a P-type transistor, and the second transistor, the twelfth transistor and the sixteenth transistor are each an N-type transistor. A pixel circuit as described in claim 2, wherein the phase of the second control signal leads the first control signal. A pixel circuit as described in claim 1, wherein a driving current is provided to the light-emitting diode only through the first transistor and the second transistor. A pixel circuit as described in claim 1, wherein the light-emitting diode comprises a micro light-emitting diode.

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