TWI868975B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a driving transistor, a control circuit, a first transistor, a pulse input circuit and a light-emitting element. A first terminal of the driving transistor is configured to receive a first working voltage through a first node, and a second terminal of the driving transistor is coupled to a second node. The control circuit is coupled to a control terminal of the driving transistor and the second node, configured to control a conduction degree of the driving transistor according to a data voltage and a threshold voltage of the driving transistor. The first terminal and the control terminal of the first transistor are coupled to the first node and the second node, respectively. The pulse input circuit is coupled to the second node, configured to be controlled by a light-emitting signal to couple a clock signal to the second node. A first terminal of the light-emitting element is coupled to the second terminal of the first transistor, and a second terminal of the light-emitting element is configured to receive a second working voltage.

Description

Pixel circuit

This disclosure relates to display technology, and more particularly to a light emitting diode pixel circuit.

Compared with liquid crystal displays, micro LED displays have advantages such as low power consumption, high color saturation and high response speed, making micro LED displays one of the hot technologies for the next generation of mainstream display products. Traditional micro LED displays control the brightness of the light generated by the micro LED in the pixel circuit by adjusting the current supplied to the pixel circuit. This method is called pulse amplitude modulation (PAM).

On the other hand, pulse width modulation (PWM) uses the phenomenon of visual retention to make the micro-LED present different grayscale values visually by adjusting the signal duty ratio within a pulse cycle. Compared with PAM, which controls the brightness of the light generated by the micro-LED by current, PWM controls the duration of the light emission, so it can avoid the problem of different light efficiency and wavelength of the micro-LED under different currents, thereby reducing color deviation.

However, in the prior art, PWM pixel circuits require a large number of signals for switching operations and usually require more components, thus limiting the circuit layout space.

The present disclosure document provides a pixel circuit, which includes a driving transistor, a control circuit, a first transistor, a pulse input circuit and a light-emitting unit. The driving transistor includes a first end, a second end and a control end. The first end of the driving transistor is used to receive a first working voltage through a first node, and the second end of the driving transistor is coupled to the second node. The control circuit is coupled to the control end and the second node of the driving transistor, and is used to control the conduction degree of the driving transistor according to the data voltage and the critical voltage of the driving transistor. The first transistor includes a first end, a second end and a control end. The first end and the control end of the first transistor are coupled to the first node and the second node respectively. The pulse input circuit is coupled to the second node, and is used to couple the clock signal to the second node according to the control of the light-emitting control signal. The light-emitting unit comprises a first end and a second end. The first end of the light-emitting unit is coupled to the second end of the first transistor, and the second end of the light-emitting unit is used to receive a second working voltage.

The present disclosure document provides a pixel circuit, which includes a light-emitting unit, a driving transistor, a first transistor, a control circuit, and a pulse input circuit. The driving transistor is used to receive a first working voltage through a first node to charge a second node. The first transistor is coupled between the first node and the light-emitting unit, and includes a control end coupled to the second node, which is used to determine the length of time the light-emitting unit receives the first working voltage. The control circuit is coupled to the control end of the driving transistor and the second node, and is used to control the conduction degree of the driving transistor according to the data voltage and the critical voltage of the driving transistor. The pulse input circuit is coupled to the second node, and is used to couple a clock signal to the second node according to the control of a light-emitting control signal.

One of the advantages of the above pixel circuit is that it has a small number of components and a small circuit area.

The following will be used in conjunction with the relevant drawings to illustrate the embodiments of the present disclosure. In the drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a functional block diagram of a pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a driving transistor Td, a pulse input circuit 110, a control circuit 120, a first transistor T1, a first node N1, a second node N2, and a light-emitting unit 130. The first node N1 receives a first operating voltage OVDD and is coupled to a first end of the driving transistor Td. The light-emitting unit 130 includes a first end (e.g., an anode end) and a second end (e.g., a cathode end). The first end of the light-emitting unit 130 is coupled to the second end of the first transistor T1, and the second end of the light-emitting unit 130 is used to receive a second operating voltage OVSS.

The pulse input circuit 110 includes a second transistor T2 and a first capacitor C1, and is coupled to the second node N2. The pulse input circuit 110 is used to couple the clock signal EM_pulse to the second node N2 through the first capacitor C1 according to the control of the luminous control signal EM. The second transistor T2 includes a first end, a second end and a control end, wherein the second end and the control end of the second transistor T2 are used to receive the clock signal EM_pulse and the luminous control signal EM respectively. The first capacitor C1 is coupled between the second node N2 and the first end of the second transistor T2.

The control circuit 120 includes a second capacitor C2, a data write circuit 121, a compensation circuit 122, and a reset circuit 123. The control circuit 120 is used to receive the data voltage Vdata, the luminous control signal EM, the first reference voltage VrefP, and the second reference voltage VrefN, and is coupled to the control terminal of the driving transistor Td and the second node N2. The control circuit 120 is also used to operate the driving transistor Td in the saturation region according to the data voltage Vdata, and to compensate for the critical voltage variation of the driving transistor Td. Therefore, the control circuit 120 is used to control the conduction degree of the driving transistor Td according to the data voltage Vdata and the critical voltage of the driving transistor Td. In some embodiments, the “conductivity” may be the magnitude of the current flowing through the driving transistor Td.

The data write circuit 121 includes a third transistor T3 and a fourth transistor T4, which are used to receive a first reference voltage VrefP, a light-emitting control signal EM, and a data voltage Vdata. The third transistor T3 and the fourth transistor T4 each include a first end, a second end, and a control end. The first end and the control end of the third transistor T3 are respectively used to receive the first reference voltage VrefP and the light-emitting control signal EM. The first end and the control end of the fourth transistor T4 are respectively used to receive the data voltage Vdata and the first control signal S1. In addition, the second end of the third transistor T3 and the second end of the fourth transistor T4 are coupled to the second end of the second capacitor C2. The first end of the second capacitor C2 is coupled to the control end of the driving transistor Td.

The compensation circuit 122 includes a fifth transistor T5 for receiving the first control signal S1. The fifth transistor T5 includes a first terminal, a second terminal and a control terminal. The first terminal and the second terminal of the fifth transistor T5 are respectively coupled to the control terminal of the driving transistor Td and the second node N2, and the control terminal of the fifth transistor T5 is used to receive the first control signal S1.

The reset circuit 123 includes a sixth transistor T6 for receiving the second control signal S2 and the second reference voltage VrefN. The sixth transistor T6 includes a first terminal, a second terminal and a control terminal. The first terminal and the control terminal of the sixth transistor T6 are respectively used to receive the second reference voltage VrefN and the second control signal S2, and the second terminal of the sixth transistor T6 is coupled to the control terminal of the driving transistor Td.

In some embodiments, the first transistor T1 to the sixth transistor T6 can be implemented by various suitable P-type transistors, such as thin film transistors or metal oxide semiconductor field effect (MOS) transistors. In some embodiments, the light-emitting unit 130 can be implemented by various suitable light-emitting diodes, such as organic light-emitting diodes (OLEDs) or micro-light-emitting diodes (micro-LEDs).

In some embodiments, the first operating voltage OVDD is greater than the second operating voltage OVSS. In other embodiments, the first reference voltage VrefP is greater than the second reference voltage VrefN.

FIG. 2 is a waveform diagram of a pixel circuit 100 according to an embodiment of the present disclosure. The operation of the pixel circuit 100 in each frame includes a reset phase TR, a compensation phase TC, and an emission phase TE; in some embodiments, the operation of the pixel circuit 100 in each frame includes a reset phase TR, a compensation phase TC, and an emission phase TE arranged in sequence. In the following paragraphs, "enable level" refers to a voltage level sufficient to turn on a transistor, and "disable level" refers to a voltage level sufficient to turn off a transistor. In some embodiments, the enable levels of the first control signal S1, the second control signal S2, and the emission control signal EM may be the same or different, and the disable levels of the above three signals may also be the same or different.

Please refer to FIG. 2 and FIG. 3 together, wherein FIG. 3 is a schematic diagram of the operation state of the pixel circuit 100 in the reset stage according to an embodiment of the present disclosure document. In the reset stage TR, the first control signal S1 and the second control signal S2 are at an enable level (e.g., a low voltage level), and the light control signal EM is at a disable level (e.g., a high voltage level). Therefore, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on, and the second transistor T2 and the third transistor T3 are turned off. Therefore, the first end of the second capacitor C2 is charged to the data voltage Vdata, and the second node N2, the second end of the second capacitor C2, and the second node N2 are reset to approximately the second reference voltage VrefN.

Please refer to FIG. 2 and FIG. 4 together, wherein FIG. 4 is a schematic diagram of the operation state of the pixel circuit 100 in the compensation stage according to an embodiment of the present disclosure document. In the compensation stage TC, the first control signal S1 is an enable level (e.g., a low voltage level), and the second control signal S2 and the light control signal EM are a disable level (e.g., a high voltage level). Therefore, the fourth transistor T4 and the fifth transistor T5 are turned on, and the second transistor T2, the third transistor T3 and the sixth transistor T6 are turned off. Therefore, the second node N2 and the second end of the second capacitor C2 are charged to OVDD-Vthd by the driving transistor Td, where "Vthd" is the critical voltage of the driving transistor Td. The first end of the second capacitor C2 is maintained at the data voltage Vdata.

Please refer to FIG. 2 and FIG. 5 together, wherein FIG. 5 is a schematic diagram of the operation state of the pixel circuit 100 in the light-emitting stage according to an embodiment of the present disclosure document. In the light-emitting stage TE, the light-emitting control signal EM is at an enable level (e.g., a low voltage level), and the first control signal S1 and the second control signal S2 are at a disable level (e.g., a high voltage level). Therefore, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. The voltage at the first end of the second capacitor C2 changes from the data voltage Vdata to the first reference voltage VrefP. Therefore, based on the capacitive coupling effect, the voltage at the control end of the driving transistor Td becomes OVDD-Vthd+VrefP-Vdata.

In the light-emitting stage TE, the current passing through the driving transistor Td can be obtained by the following formula 1, where " "Idri" is the current passing through the driving transistor Td: Formula 1

In some embodiments, in the light-emitting stage TE, when the clock signal EM_pulse decreases, the voltage of the first end of the first capacitor C1 (i.e., the second node N2) decreases due to the capacitive coupling effect. Therefore, the first transistor T1 is turned on and generates a current Iled transmitted to the light-emitting unit 130, so that the light-emitting unit 130 emits light. At the same time, the driving transistor Td charges the second node N2 until the voltage of the second node N2 becomes OVDD. Therefore, the first transistor T1 is turned off, so that the light-emitting unit 130 is extinguished. Since the clock signal EM_pulse rises and falls multiple times in a frame, the light-emitting unit 130 emits light and extinguishes multiple times in the light-emitting stage TE.

Please refer to Formula 1 and FIG. 6, wherein FIG. 6 is a schematic diagram of the circuit simulation result of the pixel circuit 100 according to an embodiment of the present disclosure document. The driving transistor Td will charge the second node N2 multiple times in the light-emitting stage TE, and the charging speed of the driving transistor Td to the second node N2 can be controlled by the data voltage Vdata. The voltage of the second node N2 is marked as voltage V2 in FIGS. 5-6, and the multiple curves of voltage V2 represent multiple changes of voltage V2 under different multiple data voltages Vdata. Next, it can be seen from the multiple curves of the current Iled that the faster the voltage V2 reaches OVDD, the smaller the pulse width of the current Iled (that is, the shorter the conduction time of the first transistor T1 in the light-emitting phase TE). Therefore, the charging speed of the driving transistor Td to the second node N2 determines the light-emitting time of the light-emitting unit 130 each time it is lit. Due to the phenomenon of visual retention, the conduction degree of the driving transistor Td (that is, the charging speed of the second node N2) determines the grayscale value felt by the user in one frame.

As can be seen from the above, the pixel circuit 100 is a PWM dimming circuit (that is, the current Iled has a PWM waveform), so the pixel circuit 100 can avoid the problem of luminous efficiency and luminous wavelength deviation of the light-emitting unit 130. In addition, compared with the traditional PWM dimming pixel circuit which usually requires more than 10 transistors, the pixel circuit 100 only needs 7 transistors, so the pixel circuit 100 has the advantages of a small number of components and a small total circuit area.

As used herein, "about", "approximately" or "roughly" generally refers to a numerical value with an error or range of less than 20%, preferably within 10%, and more preferably within 5%. If not explicitly stated in the text, the numerical values mentioned are deemed to be approximate values, that is, the error or range indicated by "about", "approximately" or "roughly".

Certain terms are used in the specification and patent application to refer to specific components. However, a person with ordinary knowledge in the art should understand that the same component may be referred to by different terms. The specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of the components as the basis for distinction. The term "including" mentioned in the specification and patent application is an open term and should be interpreted as "including but not limited to". In addition, "coupling" includes any direct and indirect connection means. Therefore, if the text describes a first component coupled to a second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second component through other components or connection means.

In addition, unless otherwise specified in the specification, any singular term also includes the plural term.

The above are only the preferred embodiments of this disclosure. Various modifications and equivalent changes can be made to this disclosure without departing from the scope or spirit of this disclosure. In summary, all modifications and equivalent changes made to this disclosure within the scope of the following claims are covered by this disclosure.

100: Pixel circuit

110: Pulse input circuit

120: Control circuit

130: Light-emitting unit

121: Data writing circuit

122: Compensation circuit

123: Reset circuit

T1: First transistor

T2: Second transistor

T3: The third transistor

T4: The fourth transistor

T5: The fifth transistor

T6: The sixth transistor

Td: driving transistor

N1: First node

N2: Second node

C1: First capacitor

C2: Second capacitor

Vdata: data voltage

OVDD: First operating voltage

OVSS: Second operating voltage

S1: First control signal

S2: Second control signal

EM: luminous control signal

EM_pulse: pulse signal

VrefP: First reference voltage

VrefN: Second reference voltage

V2: Voltage of the second node

Iled: current of the light-emitting unit

FIG. 1 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure document. FIG. 2 is a schematic diagram of a control signal waveform of a pixel circuit according to an embodiment of the present disclosure document. FIG. 3 is a schematic diagram of the operation state of a pixel circuit in a reset phase according to an embodiment of the present disclosure document. FIG. 4 is a schematic diagram of the operation state of a pixel circuit in a compensation phase according to an embodiment of the present disclosure document. FIG. 5 is a schematic diagram of the operation state of a pixel circuit in a light-emitting phase according to an embodiment of the present disclosure document. FIG. 6 is a schematic diagram of the circuit simulation result of a pixel circuit according to an embodiment of the present disclosure document.

100: Pixel circuit

110: Pulse input circuit

120: Control circuit

130: Light-emitting unit

121: Data writing circuit

122: Compensation circuit

123: Reset circuit

T1: First transistor

T2: Second transistor

T3: The third transistor

T4: The fourth transistor

T5: The fifth transistor

T6: Sixth transistor

Td: driving transistor

N1: First node

N2: Second node

C1: first capacitor

C2: Second capacitor

Vdata: data voltage

OVDD: first operating voltage

OVSS: Second operating voltage

S1: First control signal

S2: Second control signal

EM: luminous control signal

EM_pulse: pulse signal

VrefP: first reference voltage

VrefN: Second reference voltage

Claims (9)

A pixel circuit includes: a driving transistor including a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a first working voltage through a first node, and the second end of the driving transistor is coupled to a second node; a control circuit coupled to the control end and the second node of the driving transistor, and used to control the conduction degree of the driving transistor according to a data voltage and a critical voltage of the driving transistor; a first transistor including a first end, a second end and a control end, wherein the first end and the control end of the first transistor are coupled to the first node and the second node respectively; a pulse The wave input circuit is coupled to the second node and is used to couple a clock signal to the second node according to the control of a light-emitting control signal, comprising: a second transistor, comprising a first end, a second end and a control end, wherein the second end and the control end of the second transistor are respectively used to receive the clock signal and the light-emitting control signal; and a first capacitor, coupled between the second node and the first end of the second transistor; and a light-emitting unit, comprising a first end and a second end, wherein the first end of the light-emitting unit is coupled to the second end of the first transistor, and the second end of the light-emitting unit is used to receive a second working voltage. A pixel circuit as described in claim 1, wherein the control circuit comprises: a second capacitor comprising a first end and a second end, wherein the first end of the second capacitor is coupled to the control end of the drive transistor; a compensation circuit for connecting the second node and the control end of the drive transistor to each other during a compensation period; a data writing circuit for transmitting a data voltage to the second end of the second capacitor during the compensation period, and for transmitting a first reference voltage to the second end of the second capacitor during a light-emitting period; and a reset circuit for transmitting a second reference voltage to the control end of the drive transistor during a reset period. The pixel circuit as described in claim 2, wherein the reset period, the compensation period and the luminous period are arranged in sequence, and the luminous control signal is a first disable voltage level in the reset period and the compensation period, and is a first enable voltage level in the luminous period. A pixel circuit as described in claim 2, wherein the data writing circuit comprises: a third transistor, comprising a first end, a second end and a control end, wherein the first end and the control end of the third transistor are respectively used to receive the first reference voltage and the light emitting control signal; and a fourth transistor, comprising a first end, a second end and a control end, wherein the first end and the control end of the fourth transistor are respectively used to receive the data voltage and a first control signal, wherein the second end of the third transistor and the second end of the fourth transistor are coupled to the second end of the second capacitor. A pixel circuit as described in claim 2, wherein the compensation circuit comprises: a fifth transistor, comprising a first end, a second end and a control end, wherein the first end and the second end of the fifth transistor are respectively coupled to the control end and the second node of the driving transistor, and the control end of the fifth transistor is used to receive a first control signal. The pixel circuit as described in claim 5, wherein the reset period, the compensation period and the light-emitting period are arranged in sequence, and the light-emitting control signal is a first disable voltage level in the reset period and the compensation period, and a first enable voltage level in the light-emitting period; the first control signal is a second enable voltage level in the reset period and the compensation period, and a second disable voltage level in the light-emitting period. A pixel circuit as described in claim 2, wherein the reset circuit comprises: a sixth transistor, comprising a first end, a second end and a control end, wherein the first end and the control end of the sixth transistor are respectively used to receive the second reference voltage and a second control signal, and the second end of the sixth transistor is coupled to the control end of the drive transistor. The pixel circuit as described in claim 7, wherein the reset period, the compensation period and the light-emitting period are arranged in sequence, and the light-emitting control signal is a first disable voltage level in the reset period and the compensation period, and a first enable voltage level in the light-emitting period, and the second control signal is a third enable voltage level in the reset period, and a third disable voltage level in the compensation period and the light-emitting period. A pixel circuit includes: a light-emitting unit; a driving transistor for receiving a first working voltage through a first node to charge a second node; a first transistor coupled between the first node and the light-emitting unit, including a control terminal coupled to the second node, for determining the length of time for the light-emitting unit to receive the first working voltage; a control circuit coupled to a control terminal of the driving transistor and the second node, for controlling the light-emitting unit to receive the first working voltage according to a data voltage and a voltage of the driving transistor. A threshold voltage controls the conduction degree of the driving transistor; and a pulse input circuit coupled to the second node, used to couple a clock signal to the second node according to the control of a light-emitting control signal, comprising: a second transistor, comprising a first end, a second end and a control end, wherein the second end and the control end of the second transistor are used to receive the clock signal and the light-emitting control signal respectively; and a capacitor coupled between the second node and the first end of the second transistor.

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